Signal receiving device

Abstract

The present invention provides a signal receiving device. The signal receiving device includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage and a bias voltage. The first amplifier generates a first common current according to the bias voltage, and generates a complementary first output signal and a second output signal according to the first common current and by comparing the input signal and the reference voltage. The duty cycle adjuster performs charging and discharging operations on a selected capacitor according to the first output signal or the second output signal to generate a detection voltage, and generates a common reference voltage according to the detection voltage. The common mode feedback circuit generates a bias voltage according to comparing the common reference voltage and the reference voltage to compensate for the distortion generated by the first amplifier due to the change in the transconductance value.

Description

Technical Field

[0001] The present invention relates to a signal receiving device, and in particular to a signal receiving device capable of adjusting the duty cycle of an output signal. Background Art

[0002] In the prior art, the preamplifier in the signal receiver is often implemented by a differential amplifier, wherein the differential amplifier operates based on a common current, and the voltage value of the output signal can be determined according to the current flowing through the differential transistor.

[0003] In the prior art, based on the fact that the size of the common current is fixed, when the on-voltage of the differential transistor varies due to process drift or environmental factors, the conductance value of the differential transistor will change accordingly. Such a change may make it impossible for the duty cycle of the output signal generated by the differential amplifier to be maintained within the correct range, causing the received signal to be distorted. Summary of the invention

[0004] The present invention is directed to a signal receiving device which can dynamically adjust the duty cycle of an output signal.

[0005] According to an embodiment of the present invention, a signal receiving device includes a first amplifier, a duty cycle adjuster, and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage, and a bias voltage. The first amplifier generates a first common current according to the bias voltage, and generates a complementary first output signal and a second output signal according to the first common current and by comparing the input signal and the reference voltage. The duty cycle adjuster receives the first output signal and the second output signal, performs a charge and discharge operation on a selected capacitor according to the first output signal or the second output signal to generate a detection voltage, and generates a common reference voltage according to the detection voltage. The common mode feedback circuit receives the common reference voltage, and generates a bias voltage according to comparing the common reference voltage and the reference voltage.

[0006] According to the above, the embodiment of the present invention provides a duty cycle adjuster to detect the change of the duty cycle of the output signal of the amplifier, and adjust the bias voltage used by the amplifier to generate the common current according to the change of the duty cycle of the output signal. In this way, the distortion of the output signal of the amplifier caused by the change of the transconductance value can be compensated to maintain the accuracy of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 A schematic diagram of a signal receiving device according to an embodiment of the present invention is shown;

[0009] Figure 2 A schematic diagram of an implementation scheme of a duty cycle adjuster according to an embodiment of the present invention is shown;

[0010] Figure 3 A circuit diagram of another implementation of a duty cycle adjuster according to an embodiment of the present invention is shown;

[0011] Figure 4 A schematic diagram of a signal receiving device according to another embodiment of the present invention is shown;

[0012] Figure 5 A circuit diagram of an implementation of a common-mode feedback circuit according to an embodiment of the present invention is shown.

[0013] Description of Figure Numbers

[0014] 100, 400: signal receiving device;

[0015] 110, 410, 440, OP51, OP52: amplifier;

[0016] 120, 200, 420: duty cycle adjuster;

[0017] 130, 430, 500: common mode feedback circuit;

[0018] 210: detection circuit;

[0019] 220: common reference voltage generating circuit;

[0020] 311: differential pair;

[0021] 312: current source;

[0022] 321: decoder;

[0023] 323: voltage divider;

[0024] A, B: comparison results;

[0025] COD: adjustment code;

[0026] RL1, RL2: load;

[0027] CA, CB: capacitance;

[0028] OP1, OP2: operational amplifiers;

[0029] OP3, OP4: comparator;

[0030] RE1, RE2, Ra, Rb, Rc, R1, R2: resistance;

[0031] M1~M3, M51: transistors;

[0032] VDD, VSS, Vref_res: reference power supply terminals;

[0033] I1, I2, IT: current;

[0034] VA, VB: detection voltage;

[0035] Vin: input signal;

[0036] Vref: reference voltage;

[0037] Vbias: bias voltage;

[0038] Vout1, Vout1_n: output signal;

[0039] Vout2: output signal of the next stage;

[0040] Vcom_ref: common reference voltage. DETAILED DESCRIPTION

[0041] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0042] Figure 1 A schematic diagram of a signal receiving device according to an embodiment of the present invention is shown. The signal receiving device 100 includes an amplifier 110, a duty cycle adjuster 120, and a common mode feedback circuit 130. The amplifier 110 receives an input signal Vin, a reference voltage Vref, and a bias voltage Vbias. The amplifier 110 generates a common current according to the bias voltage Vbias, and based on the common current, generates a complementary output signal Vout1 and an output signal Vout1_n according to a comparison between the input signal Vin and the reference voltage Vref. The amplifier 110 may be a differential amplifier circuit. The amplifier 110 may determine the common mode voltage level of the output signals Vout1 and Vout1_n according to the common current generated by the bias voltage Vbias.

[0043] The duty cycle adjuster 120 is coupled to the amplifier 110. The duty cycle adjuster 120 receives the complementary output signals Vout1 and Vout1_n. The duty cycle adjuster 120 performs charging and discharging operations on a selected capacitor according to the output signal Vout1 or the output signal Vout1_n to generate a detection voltage. The duty cycle adjuster 120 also generates a common reference voltage Vcom_ref according to the detection voltage.

[0044] In this embodiment, the duty cycle adjuster 120 uses one of the output signals Vout1 and Vout1_n to charge and discharge the selected capacitor to detect the duty cycle of the output signals Vout1 and Vout1_n, and obtains the common reference voltage Vcom_ref according to the generated detection voltage.

[0045] The common reference voltage Vcom_ref is provided to the common mode feedback circuit 130. The common mode feedback circuit 130 also receives the reference voltage Vref, and adjusts the voltage value of the bias voltage Vbias according to comparing the common reference voltage Vcom_ref with the reference voltage Vref.

[0046] According to the above, by adjusting the voltage value of the bias voltage Vbias, the common current in the amplifier 110 can be adjusted. In this way, when the on-voltage of the differential transistor in the amplifier 110 varies, the conductance of the differential transistor can be automatically adjusted by adjusting the current flowing through the differential transistor, thereby maintaining the duty cycle of the output signal Vout1 and the output signal Vout1_n.

[0047] Please refer to the following Figure 2 , Figure 2 A schematic diagram of an implementation of a duty cycle adjuster according to an embodiment of the present invention is shown. The duty cycle adjuster 200 includes a detection circuit 210 and a common reference voltage generating circuit 220. The detection circuit 210 receives an output signal Vout1 and an output signal Vout1_n. A selected capacitor may be provided in the detection circuit 210, and a charge and discharge operation is performed on the selected capacitor based on the output signal Vout1 or the output signal Vout1_n to generate a detection voltage VA. The detection circuit 210 provides the detection voltage VA to the common reference voltage generating circuit 220. The common reference voltage generating circuit 220 provides a plurality of threshold voltages, and compares the detection voltage VA with the plurality of threshold voltages to generate a plurality of comparison results. The common reference voltage generating circuit 220 adjusts the voltage value of the common reference voltage Vcom_ref according to the obtained comparison results.

[0048] For details, please refer to Figure 3A circuit diagram of another embodiment of the duty cycle adjuster of the embodiment of the present invention is shown. The duty cycle adjuster 300 includes a detection circuit 310 and a common reference voltage generating circuit 320. In this embodiment, the detection circuit 310 includes a differential pair 311, a current source 312, loads RL1, RL2, capacitors CA, CB, operational amplifiers OP1, OP2, and resistors RE1, RE2. The differential pair 311 is composed of transistors M1 and M2. The loads RL1 and RL2 are respectively coupled to the first ends of the transistors M1 and M2, and the loads RL1 and RL2 are commonly coupled to the reference power supply terminal VDD. The first ends of the transistors M1 and M2 respectively form two load ends of the differential pair 311. The control ends of the transistors M1 and M2 respectively form two input ends of the differential pair 311, and receive the output signals Vout1 and Vout1_n respectively.

[0049] In addition, the second terminals of transistors M1 and M2 are connected to each other and form a common terminal of differential pair 311. Current source 312 is constructed by transistor M3. Transistor M3 is coupled between the common terminal of differential pair 311 and reference power terminal VSS, and the control terminal of transistor M3 is coupled to operational amplifier OP2.

[0050] The current source 312 provides a current IT as a common current of the differential pair 310. The transistors M1 and M2 generate currents I1 and I2 respectively according to the received output signals Vout1 and Vout1_n, wherein the sum of the currents I1 and I2 is equal to the current IT.

[0051] On the other hand, capacitor CA is connected in series between the first end of transistor M1 and reference power supply terminal VSS, and capacitor CB is connected in series between the first end of transistor M2 and reference power supply terminal VSS. Capacitors CA and CB can be charged and discharged according to the voltage values ​​on the first ends of transistors M1 and M2, respectively, and generate detection voltages VA and VB respectively.

[0052] In this embodiment, capacitor CA is coupled to the common reference voltage generating circuit 320, so capacitor CA can be used as a selected capacitor. In other embodiments of the present invention, capacitor CB can also be coupled to the common reference voltage generating circuit 320 and used as a selected capacitor, without any limitation.

[0053] In terms of action details, since the output signal Vout1 is a signal that repeatedly switches between a first voltage and a second voltage (for example, the first voltage is greater than the second voltage), when the output signal Vout1 is equal to a relatively large first voltage, the current I1 flowing through the load RL1 increases, and the detection voltage VA decreases. When the output signal Vout1 is equal to a relatively small second voltage, the current I1 flowing through the load RL1 decreases, and the detection voltage VA increases. Therefore, the duty cycle of the output signal Vout1 can be inversely proportional to the voltage value of the detection voltage VA. Therefore, according to the change in the voltage value of the detection voltage VA, the change in the duty cycle of the output signal Vout1 can be known.

[0054] Incidentally, in this embodiment, the operational amplifiers OP1 and OP2 are used to generate the bias voltage received by the current source 312. The operational amplifier OP1 receives the reference voltage Vref, and the output terminal of the operational amplifier OP1 is coupled to the positive input terminal of the operational amplifier OP2. The negative input terminal of the operational amplifier OP2 is coupled to the resistor string formed by the resistors RE1 and RE2. The resistors RE1 and RE2 are coupled between the reference power supply terminal Vref_res and VSS.

[0055] The common reference voltage generating circuit 320 includes a decoder 321, a threshold voltage generator 322, a voltage divider 323, a comparator OP3 and a comparator OP4. The decoder 321 is an analog-to-digital converter. The threshold voltage generator 322 is formed by a plurality of resistors Ra, Rb and Rc. The resistors Ra, Rb and Rc are sequentially coupled in series between the reference power supply terminal Vref_res and the reference power supply terminal VSS. The threshold voltage generator 322 divides the reference power provided by the reference power supply terminal Vref_res through the resistors Ra, Rb and Rc to generate a plurality of threshold voltages. In the present embodiment, the threshold voltage generator 322 has three resistors Ra, Rb and Rc, and can generate two threshold voltages.

[0056] The comparators OP3 and OP4 can be constructed by an operational amplifier. The positive input terminal of the comparator OP3 receives the detection voltage VA, and the negative input terminal of the comparator OP3 is coupled to the connection terminal of the resistors Ra and Rb, and receives the first threshold voltage. The negative input terminal of the comparator OP4 receives the detection voltage VA, and the positive input terminal of the comparator OP4 is coupled to the connection terminal of the resistors Rb and Rc, and receives the second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

[0057] The comparators OP3 and OP4 compare the detection voltage VA with the first threshold voltage and the second threshold voltage, and respectively generate comparison results A and B. When the detection voltage VA is greater than the first threshold voltage and greater than the second threshold voltage, the comparators OP3 and OP4 may respectively generate comparison results A of a logic high level and comparison results B of a logic low level; when the detection voltage VA is less than the first threshold voltage but greater than the second threshold voltage, the comparators OP3 and OP4 may respectively generate comparison results A of a logic low level and comparison results B of a logic low level; when the detection voltage VA is less than the first threshold voltage and less than the second threshold voltage, the comparators OP3 and OP4 may respectively generate comparison results A of a logic low level and comparison results B of a logic high level.

[0058] The decoder 321 receives the comparison results A and B, and decodes the comparison results A and B to generate an adjustment code COD. The voltage divider 323 includes resistors R1 and R2. The resistors R1 and R2 are coupled in series between the reference power supply terminal Vref_res and VSS. The resistors R1 and R2 divide the reference power provided by the reference power supply terminal Vref_res to generate a common reference voltage Vcom_ref. In this embodiment, the resistor R2 is a variable resistor. The resistance value of the resistor R2 can be determined based on the adjustment code COD. By increasing the resistance value of the resistor R2, the voltage value of the common reference voltage Vcom_ref can be increased. Conversely, by decreasing the resistance value of the resistor R2, the voltage value of the common reference voltage Vcom_ref can be reduced.

[0059] Regarding the adjustment action of the common reference voltage Vcom_ref, the relationship between the detection voltage VA and the comparison results A and B in this embodiment, please refer to Table 1 shown below:

[0060] Table 1:

[0061] Duty Cycle Detection voltage VA Comparison results A Comparison results B Vcom_ref 50％ 1V L L maintain 30％ 1.2V H L reduce 70％ 0.8V L H promote

[0062] In Table 1, L represents a logic low level, and H represents a logic high level. When the detection voltage VA is 1V, the comparison results A and B are both logic low levels (L), and the duty cycle of the output signal Vout1 is 50%, and there is no need to adjust the voltage value of the common reference voltage Vcom_ref; when the detection voltage VA is 1.2V, the comparison results A and B are logic high levels (H) and logic low levels (L), respectively, and the duty cycle of the output signal Vout1 is 30%, and the voltage value of the common reference voltage Vcom_ref can be adjusted to increase the duty cycle of the output signal Vout1; when the detection voltage VA is 0.8V, the comparison results A and B are logic low levels (L) and logic high levels (H), respectively, and the duty cycle of the output signal Vout1 is 70%, and the voltage value of the common reference voltage Vcom_ref can be increased to reduce the duty cycle of the output signal Vout1.

[0063] Incidentally, in this embodiment, the resistor R1 can also be set as a variable resistor, and the resistor R1 receives the adjustment code COD to adjust the provided resistance value, thereby generating the common reference voltage Vcom_ref. Under such a mechanism, under the condition that the voltage value of the common reference voltage Vcom_ref needs to be increased, the adjustment code COD generated by the decoder 321 needs to reduce the resistance value of the resistor R1. Conversely, under the condition that the voltage value of the common reference voltage Vcom_ref needs to be reduced, the adjustment code COD generated by the decoder 321 needs to increase the resistance value of the resistor R1.

[0064] Please refer to the following Figure 4 , Figure 4 A schematic diagram of a signal receiving device according to another embodiment of the present invention is shown. The signal receiving device 400 includes amplifiers 410, 440, a common mode feedback circuit 430, and a duty cycle adjuster 420. The amplifier 410 can be used as a pre-amplifier. The amplifier 410 receives an input signal Vin, a reference voltage Vref, and a bias voltage Vbias. The amplifier 410 generates a common current according to the bias voltage Vbias, and based on the common current, generates complementary output signals Vout1 and Vout1_n according to the comparison of the input signal Vin and the reference voltage Vref. The amplifier 440 is coupled to the output end of the amplifier 410, receives the output signals Vout1 and Vout1_n, and receives the bias voltage Vbias. The amplifier 440 generates a common current according to the bias voltage Vbias, and based on the common current, generates a post-stage output signal Vout2 according to the output signals Vout1 and Vout1_n.

[0065] The common mode feedback circuit 430 is coupled to the amplifiers 410 and 440, and generates a bias voltage Vbias according to the reference voltage Vref and the common reference voltage Vcom_ref. In this embodiment, the common mode feedback circuit 430 can be implemented by any common mode feedback circuit (CMFB circuit) known to those skilled in the art, without any specific limitation.

[0066] The duty cycle adjuster 420 is coupled to the amplifier 410 and the common mode feedback circuit 430. The implementation details of the duty cycle adjuster 420 can be found in the implementation of the aforementioned embodiment (eg Figure 3 The duty cycle adjuster 300) will not be described in detail here.

[0067] For details on the implementation of the common-mode feedback circuit, refer to Figure 5 The circuit diagram of the common-mode feedback circuit of the embodiment of the present invention is shown. Figure 5 In the embodiment, the common mode feedback circuit 500 includes amplifiers OP51, OP52 and a transistor M51. The two input terminals of the amplifier OP51 receive the reference voltage Vref synchronously, and the output terminal of the amplifier OP51 is coupled to the positive input terminal of the amplifier OP52. The transistor M51 serves as a current source of the amplifier OP51 and is coupled between the amplifier OP51 and the reference power supply terminal VSS. The negative input terminal of the amplifier OP52 receives the common reference voltage Vcom_ref and is used to generate a bias voltage Vbias. In addition, the bias voltage Vbias is also provided to the gate terminal of the transistor M51.

[0068] It is worth mentioning that, in the embodiment of the present invention, the circuit architecture of the amplifier OP51 can be Figure 1 , Figure 4 The amplifiers 110, 410 in the embodiments are identical.

[0069] According to the above, the embodiment of the present invention detects the duty cycle of the output signal of the amplifier and adjusts the voltage value of the common reference voltage through the common mode feedback circuit to compensate for the variation of the conduction voltage of the differential transistor of the amplifier and maintain the duty cycle of the output signal within the effective range.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A signal receiving device, characterized in that: include: A first amplifier receives an input signal, a reference voltage and a bias voltage, wherein the first amplifier generates a first common current according to the bias voltage, and generates a complementary first output signal and a second output signal according to comparing the input signal and the reference voltage based on the first common current; a duty cycle adjuster, receiving the first output signal and the second output signal, performing a charge and discharge operation on a selected capacitor according to the first output signal or the second output signal to generate a detection voltage, and generating a common reference voltage according to the detection voltage; as well as A common mode feedback circuit receives the common reference voltage and generates the bias voltage by comparing the common reference voltage with the reference voltage. The duty cycle adjuster comprises: a detection circuit, performing a charge and discharge operation on the selected capacitor according to the first output signal or the second output signal to generate the detection voltage; as well as The common reference voltage generating circuit provides a plurality of threshold voltages for comparison with the detection voltage to generate a plurality of comparison results, and adjusts the voltage value of the common reference voltage according to the plurality of comparison results.

2. The signal receiving device according to claim 1, characterized in that: The detection circuit comprises: A differential pair, having a common terminal receiving a first current, and two input terminals of the differential pair receiving the first output signal and the second output signal respectively; A current source, coupled to the common end of the differential pair and to a first reference power supply end, the current source providing the first current; A first load and a second load are respectively coupled to two load ends of the differential pair, and the first load and the second load are commonly coupled to a second reference power supply end; and The first capacitor and the second capacitor are respectively coupled to the two load terminals of the differential pair and are commonly coupled to the first reference power terminal.

3. The signal receiving device according to claim 2, characterized in that: The first capacitor or the second capacitor is the selected capacitor.

4. The signal receiving device according to claim 1, characterized in that: The detection voltage is inversely proportional to a duty cycle of the first output signal or the second output signal.

5. The signal receiving device according to claim 1, characterized in that: The common reference voltage generating circuit comprises: A threshold voltage generator, dividing the voltage of the first reference power source to generate the plurality of threshold voltages; a plurality of comparators, receiving the plurality of threshold voltages respectively, each of the comparators comparing the detection voltage with each of the threshold voltages to generate the plurality of comparison results; and A digital-to-analog converter generates a plurality of adjustment codes according to the plurality of digital comparison results; and The voltage divider comprises a first resistor and a second resistor coupled in series, wherein the first resistor and the second resistor divide the first reference power supply to generate the common reference voltage, the first resistor or the second resistor is a variable resistor, and the plurality of adjustment codes are used to adjust the resistance value of the variable resistor.

6. The signal receiving device according to claim 5, characterized in that: The digital-to-analog converter is a decoder for decoding the plurality of digital comparison results to generate the plurality of adjustment codes.

7. The signal receiving device according to claim 5, characterized in that: When the multiple threshold voltages are a first threshold voltage and a second threshold voltage, when the detection voltage is between the first threshold voltage and the second threshold voltage, the common reference voltage generating circuit does not adjust the voltage value of the common reference voltage; when the detection voltage is greater than the first threshold voltage and greater than the second threshold voltage, the common reference voltage generating circuit lowers the voltage value of the common reference voltage; when the detection voltage is less than the first threshold voltage and less than the second threshold voltage, the common reference voltage generating circuit increases the voltage value of the common reference voltage.

8. The signal receiving device according to claim 5, characterized in that: The threshold voltage generator comprises: The first resistor, the second resistor and the third resistor are sequentially coupled in series between the first reference power supply and the second reference power supply. The coupling end of the first resistor and the second resistor provides a first threshold voltage, and the coupling end of the second resistor and the third resistor provides a second threshold voltage.

9. The signal receiving device according to claim 1, characterized in that: Also includes: The second amplifier receives the first output signal, the second output signal and the bias voltage, generates a second common current according to the bias voltage, and generates a subsequent output signal according to the first output signal and the second output signal based on the second common current.

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