A filter wafer level packaging process

Abstract

The application discloses a filter wafer level packaging process and belongs to the technical field of filter packaging. The filter wafer level packaging process comprises the following steps: S1, a first insulating layer is arranged on a working surface of a wafer, and a hole is formed in the first insulating layer to expose a first region, a second region and a third region of the wafer; S2, a second insulating layer is arranged on the first insulating layer, and a hole is formed in the second insulating layer to expose the first region and the third region of the wafer; the third region is not closed by the second insulating layer, and the chips are designed to be separated, so that the shrinkage difference generated in the subsequent process is effectively weakened, and the warping phenomenon of the packaged filter is avoided; S3, metal is filled on electrodes in the first region to form a metal layer, and a preset pattern is generated on the metal layer; S4, a solder joint is made on the preset pattern; and S5, the wafer is cut along the third region to form a plurality of chips. The process improves the packaging efficiency and packaging effect.

Description

Technical Field

[0001] The present invention relates to the technical field of filter packaging, and in particular to a filter wafer-level packaging process. Background Art

[0002] The filter can effectively filter out the frequency point of a specific frequency or frequencies other than the frequency point in the power line to obtain a power signal of a specific frequency. Therefore, the filter is widely used as a frequency selection device in the signal processing process.

[0003] The steps for wafer-level packaging of the filter are as follows: Step 1: Paste a base film on the working surface of the wafer; Step 2: Photoetch on the base film to form through holes, cutting paths and cavities; Step 3: Paste a top film on the base film and photoetch on the top film to expose the through holes; Step 4: Electroplate a metal layer in the through holes; and make a preset pattern on the metal layer; Step 5: Make solder joints on the through holes; Step 6: Cut along the cutting paths to cut the entire wafer into multiple pre-designed chips.

[0004] In the aforementioned packaging method, the top film seals the cut lanes, connecting multiple chips together. However, the top film material and the wafer have different thermal expansion coefficients, which can lead to differential shrinkage during subsequent processing, causing warping of the encapsulated wafer. Furthermore, sealing the cut lanes with the top film not only increases cutting difficulty but also makes the two insulating layers more susceptible to delamination after cutting.

[0005] Therefore, it is urgent to provide a filter wafer-level packaging process to solve the above problems. Summary of the Invention

[0006] The purpose of the present invention is to provide a filter wafer-level packaging process, which solves the problem that ordinary filters are prone to warping after wafer-level packaging, and at the same time solves the problem that cutting is difficult and the two insulating layers are prone to delamination after cutting, thereby improving the packaging efficiency and packaging effect.

[0007] To achieve the above objectives, the following technical solutions are provided:

[0008] A filter wafer-level packaging process comprises the following steps:

[0009] S1. A first insulating layer is provided on a working surface of a wafer, and holes are opened in the first insulating layer to expose a first region, a second region, and a third region of the wafer; an electrode is provided in the first region; and an interdigital transducer is provided in the second region;

[0010] S2. Disposing a second insulating layer on the first insulating layer, and opening a hole in the second insulating layer to expose the first region and the third region of the wafer;

[0011] S3, filling metal on the electrode in the first region to form a metal layer; and generating a preset pattern on the metal layer;

[0012] S4, making welding spots on the preset pattern;

[0013] S5. Cutting the wafer along the third region to form a plurality of chips.

[0014] As an optional solution to the above filter wafer level packaging process, step S3 includes the following steps:

[0015] S31, providing a metal seed layer above the electrode in the second region;

[0016] S32, electroplating a filling metal on the metal seed layer to form the metal layer;

[0017] S33, performing photolithography on the metal layer to form the preset pattern.

[0018] As an optional solution to the above filter wafer level packaging process, step S33 includes the following steps:

[0019] S331, providing a layer of photoresist on the metal layer;

[0020] S332, according to the preset pattern, providing a photoresist layer on the photoresist in areas other than the preset pattern;

[0021] S333, exposing and developing so that the preset pattern appears on the photoresist;

[0022] S334 , etching the other areas of the metal layer except the preset pattern to generate the preset pattern.

[0023] As an optional solution to the above filter wafer-level packaging process, the first insulating layer and the second insulating layer are both photosensitive organic insulating coatings.

[0024] As an optional solution of the above filter wafer level packaging process, the first insulating layer is provided by semiconductor spin coating, spray coating technology or lamination technology;

[0025] The second insulating layer is provided by semiconductor spin coating, spray coating or lamination technology.

[0026] As an optional solution of the above filter wafer level packaging process, the thickness of the first insulating layer is greater than 1 μm.

[0027] As an optional solution of the above filter wafer level packaging process, the thickness of the second insulating layer is greater than 5 μm.

[0028] As an optional solution for the filter wafer-level packaging process, the position of the preset pattern is at least 1 μm higher than the second insulating layer.

[0029] As an optional solution for the above-mentioned filter wafer-level packaging process, the material used to make the solder joints is a single metal or alloy such as Sn, Cu, Ag, Au, etc.

[0030] As an optional solution of the above filter wafer level packaging process, the height of the solder joint is greater than 5 μm.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] In the filter wafer-level packaging process provided by the present invention, a hole is opened in the second insulating layer to expose the third region of the wafer. This means that the third region is not enclosed by the second insulating layer. The separation between the chips effectively reduces shrinkage differences that may occur during subsequent processing, thereby preventing warping of the packaged wafer. Furthermore, during the cutting process, only the exposed wafer needs to be cut along the third region, reducing the cutting difficulty and avoiding the undesirable consequences of delamination between the first and second insulating layers due to stress on the second insulating layer during cutting, thereby improving packaging efficiency and effectiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Flowchart of a filter wafer-level packaging process according to an embodiment of the present invention;

[0034] Figure 2 This is a flow chart of step S3 in an embodiment of the present invention;

[0035] Figure 3 Flowchart of step S33 in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of step S1 in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of step S2 in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of step S3 in an embodiment of the present invention;

[0039] Figure 7 Schematic diagram of step S4 in an embodiment of the present invention.

[0040] Reference numerals:

[0041] 1. Wafer; 2. First insulating layer; 3. Second insulating layer; 4. Metal layer; 5. Solder joint;

[0042] 11, first region; 111, electrode; 12, second region; 121, interdigital transducer; 13, third region. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor fall within the scope of protection of the present application.

[0045] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0046] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0047] In the description of the present application, it should also be noted that, unless otherwise specified and limited, the terms "provided", "connected" should be understood broadly, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0049] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0050] In common filter wafer-level packaging methods, the top film seals the cutting paths and connects multiple chips together. However, due to the different thermal expansion coefficients of the top film material and the wafer, it is easy to produce shrinkage differences during the subsequent process, which can cause the wafer to warp after packaging. Moreover, the top film sealing the cutting paths not only increases the difficulty of cutting, but also makes the two insulating layers after cutting easy to delaminate. Therefore, if Figures 1-7 As shown, this embodiment provides a filter wafer-level packaging process to solve the above problems.

[0051] The filter wafer-level packaging process includes the following steps:

[0052] S1. A first insulating layer 2 is provided on the working surface of the wafer 1, and holes are opened in the first insulating layer 2 to expose the first area 11, the second area 12 and the third area 13 of the wafer 1. An electrode 111 is provided in the first area 11, and the electrode 111 is used to achieve electrical connection with an external circuit. An interdigital transducer 121 is provided in the second area 12 to achieve acoustic-electrical transduction. Specifically, the thickness of the first insulating layer 2 is greater than 1 μm so as to form sufficient space for accommodating the electrode 111 and the interdigital transducer 121. Furthermore, the first insulating layer 2 is provided on the working surface of the wafer 1 by semiconductor spin coating, spraying technology or lamination technology. The specific setting method is determined according to the actual working conditions and is not limited here. In this embodiment, the first insulating layer 2 is a photosensitive organic insulating coating.

[0053] S2. A second insulating layer 3 is provided on the first insulating layer 2, and a hole is opened in the second insulating layer 3 to expose the first area 11 and the third area 13 of the wafer 1. The second insulating layer 3 exposes the first area 11 to facilitate the connection of the electrode 111 to the external circuit. The second insulating layer 3 encloses the second area 12 to protect the interdigital transducer 121 and prevent damage to the interdigital transducer 121 during subsequent processes. The second insulating layer 3 exposes the third area 13, that is, the third area 13 is not enclosed by the second insulating layer 3. The separation design between the chips effectively weakens the shrinkage difference generated during the subsequent process, thereby avoiding warping of the filter after packaging. Specifically, the thickness of the second insulating layer 3 is greater than 5μm. Furthermore, the second insulating layer 3 is provided on the first insulating layer 2 by semiconductor spin coating, spraying technology or lamination technology. The specific setting method is determined according to the actual working conditions and is not limited here. In this embodiment, the second insulating layer 3 is a photosensitive organic insulating coating.

[0054] S3. Filling the electrodes 111 in the first region 11 with metal to form a metal layer 4, and generating a predetermined pattern on the metal layer 4. As can be seen from the above process, the electrodes 111 are lower than the surface of the second insulating layer 3. To connect the electrodes 111 to an external circuit, a metal layer 4 is provided on the electrodes 111 to elevate the predetermined pattern beyond the second insulating layer 3. Specifically, the predetermined pattern is positioned at least 31 μm above the second insulating layer.

[0055] S4. Create solder joints 5 on the preset pattern. The filter is electrically connected to the external circuit via solder joints 5. Specifically, solder joints 5 are made of a single metal or alloy such as Sn, Cu, Ag, or Au. Furthermore, solder joints 5 are created through a series of processes including printing, ball placement, electroplating, and sintering. Furthermore, the height of solder joints 5 is greater than 5 μm.

[0056] S5. Cut the wafer 1 along the third region 13 to form a plurality of chips. During the cutting process, it is only necessary to cut the exposed wafer 1 along the third region 13, which reduces the difficulty of cutting and avoids the adverse consequences of delamination of the first insulating layer 2 and the second insulating layer 3 due to the force applied to the second insulating layer 3 during the cutting process, thereby improving the packaging efficiency and packaging effect. Specifically, the wafer 1 is cut using mechanical cutting technology or laser cutting technology. The specific cutting method is determined according to the actual working conditions and is not limited here.

[0057] In order to ensure normal electrical connection between the chip and the external circuit, each chip should be provided with a positive electrode 111 and a negative electrode 111, so each chip is provided with two first regions 11. Moreover, a third region 13 is provided between two adjacent chips.

[0058] Optionally, step S3 includes the following steps:

[0059] S31. A metal seed layer is provided above the electrode 111 in the second region 12. The provision of the metal seed layer allows the subsequent metal filling to be evenly distributed. Specifically, the metal seed layer is formed by PVD (Physical Vapor Deposition) sputtering.

[0060] S32 , electroplating the metal seed layer to form a filling metal to form a metal layer 4 .

[0061] S33 , performing photolithography on the metal layer 4 to form a preset pattern.

[0062] Further optionally, step S33 includes the following steps:

[0063] S331 , a layer of photoresist is provided on the metal layer 4 to meet the initial conditions for the smooth progress of the photolithography process.

[0064] S332 , according to the preset pattern, a photoresist layer is provided on the photoresist in areas other than the preset pattern.

[0065] S333: Expose and develop, so that the preset pattern appears on the photoresist.

[0066] S334 , etching the other areas on the metal layer 4 except for the preset pattern to generate the preset pattern.

[0067] Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A filter wafer level packaging process, characterized in that: The following steps are involved: S1. A first insulating layer (2) is provided on a working surface of a wafer (1), and holes are opened in the first insulating layer (2) to expose a first region (11), a second region (12), and a third region (13) of the wafer (1); an electrode (111) is provided in the first region (11); and an interdigital transducer (121) is provided in the second region (12); S2, providing a second insulating layer (3) on the first insulating layer (2), and opening a hole in the second insulating layer (3) to expose the first region (11) and the third region (13) of the wafer (1); S3, filling metal on the electrode (111) in the first region (11) to form a metal layer (4); and generating a preset pattern on the metal layer (4); S4, making welding points (5) on the preset pattern; S5, cutting the wafer (1) along the third region (13) to form a plurality of chips.

2. The filter wafer level packaging process according to claim 1, characterized in that: Step S3 includes the following steps: S31, providing a metal seed layer above the electrode (111) in the first region (11); S32, electroplating a filling metal on the metal seed layer to form the metal layer (4); S33, performing photolithography on the metal layer (4) to form the preset pattern.

3. The filter wafer level packaging process according to claim 2, characterized in that: Step S33 includes the following steps: S331, providing a layer of photoresist on the metal layer (4); S332, according to the preset pattern, providing a photoresist layer on the photoresist in areas other than the preset pattern; S333, exposing and developing so that the preset pattern appears on the photoresist; S334, etching the other areas of the metal layer (4) except the preset pattern to generate the preset pattern.

4. The filter wafer level packaging process according to claim 1, characterized in that: The first insulating layer (2) and the second insulating layer (3) are both photosensitive organic insulating coatings.

5. The filter wafer level packaging process according to claim 1, characterized in that: The first insulating layer (2) is provided by semiconductor spin coating, spray coating technology or lamination technology; The second insulating layer (3) is provided by semiconductor spin coating, spray coating technology or lamination technology.

6. The filter wafer level packaging process according to claim 1, characterized in that: The thickness of the first insulating layer (2) is greater than 1 μm.

7. The filter wafer level packaging process according to claim 1, characterized in that: The thickness of the second insulating layer (3) is greater than 5 μm.

8. The filter wafer level packaging process according to claim 1, characterized in that: The position of the preset pattern is at least 1 μm higher than the second insulating layer (3).

9. The filter wafer level packaging process according to claim 1, characterized in that: The solder joints are made of single metals such as Sn, Cu, Ag and Au.

10. The filter wafer level packaging process according to claim 1, characterized in that: The height of the solder joint (5) is greater than 5 μm.

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