A delay circuit

Abstract

A time delay circuit includes a current source, an input and initialization module, a capacitor C0, a feedback control module and a judgment output module; the capacitor C0 is connected between the positive input terminal Vcn of the judgment output module and the output terminal Vcp of the feedback control module; the negative input terminal of the comparator is connected to the reference voltage Vref2; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcn; the input and initialization module is connected between the voltage terminal Vcn and the voltage terminal Vss; the positive input terminal of the feedback control module is connected to Vref1, the positive input terminal of the feedback control module is connected to the voltage terminal Vcn, and the negative input terminal of the judgment output module is connected to Vref2. When the input voltage IN of the input module increases, the voltage change value at both ends of the capacitor C0 is increased by adding the feedback control module. Therefore, under the same delay time requirement, the present invention can use a smaller capacitor C0 to make the chip area of ​​the circuit formed about 30% or less of the chip area of ​​the traditional circuit, thereby achieving its production cost of less than 30% of the traditional circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design and relates to a delay circuit. Background Art

[0002] The delay circuit is a circuit that can output the enable function after a period of time after the input enable signal. Normally, when you press the switch, the motor starts or shuts down immediately, but with the delay circuit, you can wait for a period of time (the time can be adjusted) before starting or shutting down. For example, the voice-activated LED light will turn off after a period of time after the voice-activated light is turned on, which is to provide convenience for passers-by to walk later.

[0003] In integrated circuit design, in order to design a larger delay Tdelay and ensure accuracy, the same current source is used. Currently, most current sources are used to charge the capacitor C0 to a certain threshold to make a signal delay circuit. Figure 1 , Figure 1 FIG. 1 is a functional block diagram of a delay circuit in the prior art. Figure 1 As shown, the delay circuit includes a current source, an input module, a capacitor C0 and a comparator. The capacitor C0 and the input module are connected in parallel between the positive input terminal Vc and the voltage terminal Vss of the comparator, the negative input terminal of the comparator is connected to the reference voltage Vref, and the current source is connected between the voltage terminal Vcc and the voltage terminal Vc. Once the input module inputs the control signal IN for opening and closing, the voltage difference on the capacitor C0 slowly rises from 0V in the initial state to Vref, and the change value is Vref. At this time, the comparator outputs the control signal for opening and closing, that is, the control signal is delayed by a time Tdelay.

[0004] See also Figure 2 , Figure 2 Shown Figure 1 Schematic diagram of waveforms of each node in the delay circuit. Figure 2 As shown, when the input voltage IN is at a high level, the voltage terminal Vc starts to increase from 0. When its voltage value increases to the reference voltage Vref, the comparator outputs a high level after a delay time Tdelay.

[0005] Assuming the current source is I0, and usually the reference voltage Vref is fixed in the circuit, then:

[0006] I0*Tdelay=C0*Vref

[0007] However, many application circuits require a relatively large delay time Tdelay. Based on the above formula, to obtain a more ideal state, a large capacitor C0 and a small I0 are required. If I0 is reduced in the integrated circuit design, the proportion of the error current due to the parasitic effect will increase, and the design accuracy of the circuit will decrease. Therefore, after selecting the appropriate I0, the capacitor C0 value can only be increased in the integrated circuit design, which requires a larger layout area, which means more cost. Summary of the invention

[0008] In order to solve the above technical problems, the present invention proposes a delay circuit, and its technical solution is as follows:

[0009] A delay circuit, comprising a current source, an input and initialization module, a capacitor C0, a feedback control module and a judgment output module; the capacitor C0 is connected between the positive input terminal Vcn of the judgment output module and the output terminal Vcp of the feedback control module; the negative input terminal of the judgment output module is connected to a reference voltage Vref2; the current source is connected between a voltage terminal Vcc and a voltage terminal Vcn; the input and initialization module is connected between a voltage terminal Vcn and a voltage terminal Vss; the positive input terminal of the feedback control module is connected to Vref1, the positive input terminal of the feedback control module is connected to the voltage terminal Vcn, and the negative input terminal of the judgment output module is connected to Vref2;

[0010] When the input voltage IN of the input module, wherein the absolute value of Vref2 is greater than Vref1;

[0011] Phase 1: Vcn slowly rises from the low voltage in the initial state to Vref1, Vcp maintains a high level, and the output of the judgment output module is a non-enable signal;

[0012] The second stage: Vcn maintains Vref1, Vcp slowly decreases from a high level to a low voltage, and the output of the judgment output module is a non-enable signal;

[0013] The third stage: when Vcn slowly rises from Vref1 to Vref2, Vcp maintains a low voltage, the judgment output module outputs an enable signal, and the time difference between the enable signal and the enable signal of the input voltage IN is the delay time Tdelay.

[0014] Furthermore, the feedback control module is an operational amplifier.

[0015] Furthermore, the judgment output module is a comparison module.

[0016] Furthermore, the current source includes a current mirror and a bias current module, the current mirror includes a first transistor PFET1 and a second transistor PFET2, the first transistor PFET1, the second transistor PFET2 and the bias current module are used to form a current constant current source to charge the Vcn terminal of the capacitor C0.

[0017] Furthermore, the input and initialization module includes an inverter INV and a third transistor NFET1; the inverter INV is connected between the input terminal IN and the gate of the third transistor NFET1, the drain of the third transistor NFET1 is connected to the voltage Vcn terminal, and the source of the third transistor NFET1 is connected to the voltage Vss terminal.

[0018] From the above technical solution, it can be concluded that the capacitance of the capacitor C0 used in the delay circuit of the present invention is only vref / (Vcc+vref2) of the traditional circuit. If Vcc=5V, vref=Vref2=2V in the technology, the capacitor C0 occupies the main area during layout. At this time, the chip area of ​​the circuit formed by the present invention is about 30% less than the chip area of ​​the traditional circuit, so that its production cost is less than 30% of the traditional circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The figure shows a functional block diagram of a delay circuit in the prior art;

[0020] Figure 2 Shown Figure 1 Schematic diagram of waveforms of each node in the delay circuit;

[0021] Figure 3 The figure is a functional block diagram of a delay circuit in an embodiment of the present invention;

[0022] Figure 4 Shown is a schematic diagram of a preferred embodiment of a delay circuit in an embodiment of the present invention;

[0023] Figure 5 FIG. 4 is a schematic diagram showing waveforms of various nodes of the delay circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following is combined with Figure 3-5 , the specific implementation modes of the present invention are further described in detail.

[0025] Please see attached Figure 3 , Figure 3 FIG. 2 is a functional block diagram of a delay circuit in an embodiment of the present invention. Figure 3 As shown, the delay circuit includes a current source, an input and initialization module, a capacitor C0, a feedback control module and a judgment output module.

[0026] Among them, the capacitor C0 is connected between the positive input terminal Vcn of the judgment output module and the output terminal Vcp of the feedback control module; the negative input terminal of the comparator is connected to the reference voltage Vref2; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcn; the input and initialization module is connected between the voltage terminal Vcn and the voltage terminal Vss; the positive input terminal of the feedback control module is connected to Vref1, the positive input terminal of the feedback control module is connected to the voltage terminal Vcn, and the negative input terminal of the judgment output module is connected to Vref2.

[0027] When the input voltage of the input module is IN, where the absolute value of Vref2 is greater than Vref1;

[0028] The first stage: Vcn slowly rises from the low voltage in the initial state to Vref1, Vcp remains at a high level, and the judgment output module outputs a non-enable signal.

[0029] Specifically, the input signal IN enables the signal (in the rising edge of IN in the embodiment of the present invention, IN enable is high), the current mirror charges C0, Vcn slowly rises from Vss in the initial state to Vref1 (overcharging during charging), the feedback control module operates as a comparator. Since Vcn < Vref1, the output Vcp of the feedback control module remains at a high level (the high level is Vcc in the embodiment of the present invention). Also, because Vcn < Vref2 in this stage, the output signal OUT of the judgment output module is a non-enable signal (the non-enable is low in the embodiment of the present invention).

[0030] The second stage: Vcn remains at Vref1, Vcp slowly drops from a high level to a low voltage, and the judgment output module outputs a non-enable signal.

[0031] Specifically, the feedback control module operates as an operational amplifier. At this time, when the current mirror charges C0, Vcn remains at Vref1, while Vcp slowly drops from a high level to a low level (the low level is Vss in the embodiment of the present invention). Also, because Vcn < Vref2 in this stage, the output signal OUT of the judgment output module is a non-enable signal.

[0032] The third stage: When Vcn slowly rises from Vref1 to Vref2, Vcp remains at a low voltage, the judgment output module outputs an enable signal, and the time difference between the enable signal and the enable signal of the input voltage IN is the delay time Tdelay.

[0033] Specifically, since Vcp has dropped to a low level, when the current mirror charges C0, Vcn continues to slowly rise and exceed Vref2. Once Vcn>Vref2, the judgment output module outputs the OUT enable signal, and the time difference from the input signal IN enable signal to the output signal OUT enable signal is the delay time Tdelay.

[0034] That is to say, it increases the change value of the voltage on the capacitor (Vcp-Vcn) through the feedback control module, and changes the initial voltage Vcc to -Vref2, and the change value is VCC+Vref2 (absolute value); that is:

[0035] VCC+Vref2>Vref

[0036] According to the formula: Tdelay=C*V / I, without increasing the capacitance of the capacitor C0 and maintaining the current constant current source, the delay circuit of the present invention can increase the delay time Tdelay.

[0037] See also Figure 4 , Figure 4 FIG. 2 is a schematic diagram of a preferred embodiment of a delay circuit in an embodiment of the present invention. In an embodiment of the present invention, the feedback control module may be an operational amplifier, and the judgment output module may be a comparison module which may be a comparator.

[0038] The supply voltage Vcc of the operational amplifier and the comparator can be, for example, 5 V. The negative input terminal of the operational amplifier, the positive input terminal of the comparator and one end of the capacitor are connected to the voltage Vcn terminal, the negative input terminal of the comparator is connected to the reference voltage Vref2, and the output terminal U2 is used to output the delayed start and stop control signal; the positive input terminal of the operational amplifier is connected to Vref1, and the output terminal U1 is connected to the other end of the capacitor C0 (the voltage Vcp terminal).

[0039] The current source may include a current mirror and a bias current module. The current mirror includes a first transistor PFET1 and a second transistor PFET2. The first transistor PFET1, the second transistor PFET2 and the bias current module are used to form a current constant current source to charge the Vcn terminal of the capacitor C0.

[0040] The input and initialization module may include an inverter INV and a third transistor NFET1; the inverter INV is connected between the input terminal IN and the gate of the third transistor NFET1, the drain of the third transistor NFET1 is connected to the voltage Vcn terminal, and the source of the third transistor NFET1 is connected to the voltage Vss terminal.

[0041] Please combine Figure 4 See also Figure 5 , Figure 5The waveform diagrams of each node of the delay circuit in the embodiment of the present invention are shown. In the embodiment of the present invention, for the convenience of description, it can be assumed that VSS = 0V and Vref1 < Vref2.

[0042] In the initial working state of the delay circuit, the input voltage IN of the input and initialization module is 0V, the third transistor NFET1 is turned on, Vcn = 0V, and the output of U1 of the operational amplifier is high, that is, Vcp = Vcc; at this time, the delay circuit does not work and is in a standby state.

[0043] When the delay circuit starts to work, the input voltage IN of the input and initialization module becomes high to Vcc, and the third transistor NFET1 is turned off; at this time, the first transistor PFET1, the second transistor PFET2, and the bias current module form a current constant current source to charge from the voltage Vcn terminal of the capacitor C0, and the voltage at the voltage Vcn terminal increases. When Vcn < Vref1, the voltage Vcp maintains the voltage Vcc.

[0044] Next, when Vcn = Vref1, U1 of the comparator works as an operational amplifier. At this time, the current constant current source charges the voltage Vcn terminal of the capacitor C0, the voltage Vcn remains unchanged, and the voltage Vcp decreases until Vcp = 0V.

[0045] When the voltage Vcp drops to 0V and the voltage Vcn continues to rise, when Vcn > Vref2, the output of U2 of the feedback control module is high, that is, the output OUT = VCC. That is to say, the delay time Tdelay is the rising edge when the input voltage IN becomes high to the rising edge when the output OUT becomes high. When the input voltage IN becomes low, that is, the entire circuit enters the initial state again.

[0046] In summary, the present invention increases the feedback control module, increases the voltage change value across the capacitor C0, so that the chip area of the formed circuit is about 30% or less of the chip area of the traditional circuit, thereby realizing that its manufacturing cost is 30% or less of the traditional circuit.

[0047] The above are only the preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, all equivalent structural changes made by using the description and drawings of the present invention should be included in the protection scope of the present invention by the same token.

Claims

1. A delay circuit, characterized in that: It includes a current source, an input and initialization module, a capacitor C0, a feedback control module and a judgment output module; the capacitor C0 is connected between the positive input terminal Vcn of the judgment output module and the output terminal Vcp of the feedback control module; the negative input terminal of the judgment output module is connected to the reference voltage Vref2; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcn; the input and initialization module is connected between the voltage terminal Vcn and the voltage terminal Vss; the positive input terminal of the feedback control module is connected to Vref1, the positive input terminal of the feedback control module is connected to the voltage terminal Vcn, and the negative input terminal of the judgment output module is connected to Vref2; When the input voltage IN of the input and initialization module, wherein the absolute value of Vref2 is greater than Vref1; Phase 1: Vcn slowly rises from the low voltage in the initial state to Vref1, Vcp maintains a high level, and the output of the judgment output module is a non-enable signal; The second stage: Vcn maintains Vref1, Vcp slowly decreases from a high level to a low voltage, and the output of the judgment output module is a non-enable signal; The third stage: when Vcn slowly rises from Vref1 to Vref2, Vcp maintains a low voltage, the judgment output module outputs an enable signal, and the time difference between the enable signal and the enable signal of the input voltage IN is the delay time Tdelay.

2. The delay circuit according to claim 1, characterized in that: The feedback control module is an operational amplifier.

3. The delay circuit according to claim 1, characterized in that: The judgment output module is a comparison module.

4. The delay circuit according to claim 1, characterized in that: The current source includes a current mirror and a bias current module. The current mirror includes a first transistor PFET1 and a second transistor PFET2. The first transistor PFET1, the second transistor PFET2 and the bias current module are used to form a current constant current source to charge the Vcn terminal of the capacitor C0.

5. The delay circuit according to claim 1, characterized in that: The input and initialization module includes an inverter INV and a third transistor NFET1; the inverter INV is connected between the input terminal IN and the gate of the third transistor NFET1, the drain of the third transistor NFET1 is connected to the voltage Vcn terminal, and the source of the third transistor NFET1 is connected to the voltage Vss terminal.

Images