Frequency Multiplier and Delay Multiplexing Duty Cycle Calibration Method

Abstract

The present invention provides a frequency multiplier and a method for calibrating the duty cycle of delay multiplexing. The frequency multiplier includes a first calibration circuit, a second calibration circuit, and a controller. In the calibration mode of the frequency multiplier, the output end of the delay unit is coupled to the input end of the delay unit. The first calibration circuit re-uses the delay unit M times to generate a first delay signal. The controller controls the delay unit according to the first delay signal to obtain the delay of the delay unit, such that M times the delay is equal to one period of the input clock signal. After finding the delay, the delay unit is re- used M / 2 times to generate a second delay signal. The controller controls the second calibration circuit according to the second delay signal to make the input calibration signal have a target duty cycle.

Description

Technical Field

[0001] The present invention relates to duty cycle calibration, and more particularly to a frequency multiplier and a delay-reused duty cycle calibration method. Background Art

[0002] To implement a frequency doubler, it is necessary to delay a reference signal by 25% of a cycle of the reference signal to generate a delayed signal. Thus, a doubled frequency output signal can be generated based on the reference signal and the delayed signal. To minimize output spurs, the output signal needs to have an exact 50% duty cycle, which means that the above-mentioned 25% cycle delay needs to be generated precisely. Some related technologies use different methods to generate this 25% cycle delay. More specifically, analog building blocks are used in the related technologies, such as loop filters, comparators, passive devices (e.g., resistors or comparators), skew inverters, or operational amplifiers.

[0003] Advanced processes such as 22nm, 16nm, 12nm, 7nm, etc. offer some advantages, such as less gate delay, higher operating speed, and less circuit area. However, there are also some disadvantages. Advanced processes are expensive. In addition, analog design using advanced processes is challenging. More specifically, it occupies a large area and is difficult to optimize performance. In addition, the above-mentioned analog building blocks for generating the above-mentioned 25% cycle delay may encounter some problems in the related technologies. For example, loop filters and passive devices occupy a large area, comparator offsets and device mismatches reduce the accuracy of the generated delay, skew inverters are affected by phase noise, and operational amplifiers are difficult to scale down in advanced processes.

[0004] Therefore, a novel method and related architecture are needed to be able to generate the above-mentioned 25% cycle delay through all-digital circuits, to prevent suffering from the above-mentioned analog design problems, and to make full use of advanced processes. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a frequency multiplier and a delay-reused duty cycle calibration method to solve the above problems of the related technologies without likely introducing side effects.

[0006] At least one embodiment of the present invention provides a frequency multiplier. The frequency multiplier may include a first calibration circuit, a second calibration circuit, and a controller coupled to the first calibration circuit and the second calibration circuit. The first calibration circuit may include a first delay unit configured to provide a first delay amount. The second calibration circuit is configured to generate an input calibration signal according to an input clock signal. In the calibration mode of the frequency multiplier, the output end of the first delay unit is coupled to the input end of the first delay unit, and the first delay unit is reused M times to delay the input calibration signal or its derivative signal by M times the first delay amount to generate a first delay signal, where M is a predetermined positive integer. In addition, the controller controls the first delay amount according to the first delay signal to obtain a target delay amount such that M times the target delay amount is equal to one period of the input clock signal. After finding the target delay amount, the first delay unit is reused M / 2 times to delay the input calibration signal or its derivative signal by M / 2 times the target delay amount to generate a second delay signal; and the controller controls the second calibration circuit according to the second delay signal such that the input calibration signal has a target duty cycle.

[0007] In one embodiment, the frequency multiplier further includes: a phase detector coupled to the controller for detecting a phase difference between a delayed edge of the first delay signal and a target edge of the input calibration signal; wherein the controller controls the first delay amount such that the delayed edge of the first delay signal is aligned with the target edge of the input calibration signal.

[0008] In one embodiment, the delayed edge of the first delay signal is generated by delaying a first edge of the input calibration signal or its derivative signal, and the target edge of the input calibration signal is a second edge that is one cycle later than the first edge.

[0009] In one embodiment, the first calibration circuit further includes: a counter coupled to the output end of the first delay unit, wherein the counter generates the delayed edge of the first delay signal when the first delay unit is reused M times.

[0010] In one embodiment, the second calibration circuit includes: a second delay unit for providing a second delay amount; wherein the controller controls the second delay amount according to the second delay signal such that the input calibration signal has the target duty cycle.

[0011] In one embodiment, the second delay unit includes: a unit delay component for providing a unit delay, wherein the output end of the unit delay component is coupled to the input end of the unit delay component; wherein the unit delay component is reused N times such that the second delay amount is equal to N times the unit delay, where N is a positive integer corresponding to a digital code controlled by the controller.

[0012] In one embodiment, the second calibration circuit further includes: an inverter for generating an inverted clock signal according to the input clock signal; and a multiplexer coupled to the second delay unit for selecting one of the input clock signal and the inverted clock signal to be sent to the second delay unit according to a comparison between the current duty cycle of the input clock signal and the target duty cycle.

[0013] In one embodiment, when the current duty cycle is greater than the target duty cycle, the multiplexer selects the input clock signal to be delayed by the second delay unit for calibrating the input calibration signal; and when the current duty cycle is less than the target duty cycle, the multiplexer selects the inverted clock signal to be delayed by the second delay unit for calibrating the input calibration signal.

[0014] In one embodiment, the frequency multiplier further includes a third calibration circuit, and the third calibration circuit includes: a third delay unit for providing a third delay amount; wherein, after obtaining the target delay amount, the first delay unit is reused M / 4 times to delay the input calibration signal or its derived signal by M / 4 times the target delay amount to generate a third delay signal; and the controller controls the third calibration circuit according to the third delay signal so that the third delay amount is equal to M / 4 times the target delay amount.

[0015] In one embodiment, the frequency multiplier further includes: at least one exclusive OR (XOR) logic circuit coupled to the first calibration circuit for performing at least one XOR operation on the input calibration signal or its derived signal and the final delay signal in the normal mode of the frequency multiplier to generate a frequency-doubled output signal, where the final delay signal is generated by using the first delay unit M / 4 times to delay the input calibration signal by M / 4 times the target delay amount; or the final delay signal is generated by using the first delay unit M / 8 times to delay the derived signal of the input calibration signal by M / 8 times the target delay amount.

[0016] At least one embodiment of the present invention provides a method for calibrating the duty cycle of delayed multiplexing. The method for calibrating the duty cycle of delayed multiplexing may include: coupling the output terminal of a first delay unit to the input terminal of the first delay unit (e.g., in a calibration mode), wherein the first delay unit is located in a first calibration circuit, the first delay unit is configured to provide a first delay amount, and the first delay unit is reused M times to delay an input calibration signal or its derived signal by M times the first delay amount, thereby generating a first delay signal, wherein M is a predetermined positive integer; a controller controls the first delay amount according to the first delay signal to obtain a target delay amount of the first delay unit, such that M times the target delay amount is equal to one period of an input clock signal, wherein the input calibration signal is generated by a second calibration circuit according to the input clock signal; after finding the target delay amount, the first delay unit is reused M / 2 times to delay the input calibration signal or its derived signal by M / 2 times the target delay amount, thereby generating a second delay signal; and controlling the second calibration circuit according to the second delay signal to make the input calibration signal have a target duty cycle.

[0017] In one embodiment, the controller controls the first delay amount according to the first delay signal to obtain the target delay amount, including: detecting a phase difference between a delayed edge of the first delay signal and a target edge of the input calibration signal; and controlling the first delay amount to align the delayed edge of the first delay signal with the target edge of the input calibration signal.

[0018] In one embodiment, the delayed edge of the first delay signal is generated by delaying a first edge of the input calibration signal or its derived signal, and the target edge of the input calibration signal is a second edge that is one period later than the first edge.

[0019] In one embodiment, the output terminal of the first delay unit is coupled to a counter, and the counter generates the delayed edge of the first delay signal when the first delay unit is reused M times.

[0020] In one embodiment, the second calibration circuit includes a second delay unit for providing a second delay amount, and controlling the second calibration circuit according to the second delay signal to make the input calibration signal have the target duty cycle includes: controlling the second delay amount according to the second delay signal to make the input calibration signal have the target duty cycle.

[0021] In one embodiment, the second delay unit includes unit delay components for providing unit delay. The output terminal of the unit delay component is coupled to the input terminal of the unit delay component. Moreover, controlling the second delay amount includes: reusing the unit delay component N times so that the second delay amount is equal to N times the unit delay, where N is a positive integer corresponding to the digital code controlled by the controller.

[0022] In one embodiment, controlling the second calibration circuit according to the second delay signal to make the input calibration signal have the target duty cycle further includes: selecting one of the input clock signal and the inverted clock signal according to the comparison between the current duty cycle of the input clock signal and the target duty cycle, and sending it to the second delay unit, where the inverted clock signal is the inverted signal of the input clock signal.

[0023] In one embodiment, selecting one of the input clock signal and the inverted clock signal according to the comparison between the current duty cycle of the input clock signal and the target duty cycle and sending it to the second delay unit includes: in response to the comparison indicating that the current duty cycle is greater than the target duty cycle, selecting the input clock signal to be delayed by the second delay unit for calibrating the input calibration signal.

[0024] In one embodiment, selecting one of the input clock signal and the inverted clock signal according to the comparison between the current duty cycle of the input clock signal and the target duty cycle and sending it to the second delay unit includes: in response to the comparison indicating that the current duty cycle is less than the target duty cycle, selecting the inverted clock signal to be delayed by the second delay unit for calibrating the input calibration signal.

[0025] In one embodiment, the method further includes: after obtaining the target delay amount, reusing the first delay unit M / 4 times to delay the input calibration signal or its derived signal by M / 4 times the target delay amount to generate a third delay signal; and controlling a third calibration circuit according to the third delay signal so that the third delay amount provided by the third delay unit in the third calibration circuit is equal to M / 4 times the target delay amount.

[0026] Embodiments of the present invention can enable the first delay unit to be reused M times to obtain an accurate time corresponding to 1 / M times the period of the input clock signal, and the first delay unit is further reused M / 2 times, M / 4 times, and M / 8 times to generate accurate times corresponding to 50%, 25%, and 12.5% of the period of the input clock signal CKIN, and the accurate times corresponding to 50%, 25%, and 12.5% of the period of the input clock signal CKIN can be guaranteed. Since there are no problems such as device mismatch and offset in the present invention, the above problems in the related art can be solved.

[0027] Those skilled in the art can undoubtedly understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the drawings. Description of the Drawings

[0028] The present invention can be more comprehensively understood by reading the subsequent detailed description and referring to the examples given in the accompanying drawings, wherein:

[0029] Figure 1 is a simplified schematic diagram of a frequency doubler according to an embodiment of the present invention.

[0030] Figure 2 is illustrated according to an embodiment of the present invention Figure 1 a schematic diagram of the detailed circuit diagram of the shown frequency doubler.

[0031] Figure 3 is a timing schematic diagram of some signals during the stage of calibrating the first delay amount according to an embodiment of the present invention.

[0032] Figure 4 is a timing schematic diagram of some signals during the stage of calibrating the first delay amount according to another embodiment of the present invention.

[0033] Figure 5 is a timing schematic diagram of some signals during the stage of calibrating the second delay amount according to an embodiment of the present invention.

[0034] Figure 6 is a timing schematic diagram of some signals during the stage of calibrating the second delay amount according to another embodiment of the present invention.

[0035] Figure 7 is a timing schematic diagram of some signals after the calibration is completed according to an embodiment of the present invention.

[0036] Figure 8 is a simplified schematic diagram of a frequency quadrupler according to an embodiment of the present invention.

[0037] Figure 9 is illustrated according to an embodiment of the present invention Figure 8 a schematic diagram of the detailed circuit diagram of the shown frequency quadrupler.

[0038] Figure 10 is a timing schematic diagram of some signals during the stage of calibrating the first delay amount according to an embodiment of the present invention.

[0039] Figure 11It is a timing schematic diagram of some signals during the stage of calibrating the second delay amount according to an embodiment of the present invention.

[0040] Figure 12 It is a timing schematic diagram of some signals during the stage of calibrating the third delay amount according to an embodiment of the present invention.

[0041] Figure 13 It is a timing schematic diagram of some signals after the calibration is completed according to an embodiment of the present invention.

[0042] Figure 14 It is a flowchart schematic diagram of a delay multiplexing duty cycle calibration method according to an embodiment of the present invention.

[0043] In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can better understand the embodiments of the present invention. However, it is obvious that one or more embodiments can be implemented without these specific details, and different embodiments can be combined according to requirements, and should not be limited to the embodiments listed in the drawings. Detailed implementation manners

[0044] The following description is a preferred embodiment of the implementation of the present invention, which is only used to illustrate and explain the technical features of the present invention, and is not used to limit the scope of the present invention. Certain terms are used throughout the specification and claims to refer to particular elements. Those skilled in the art should understand that manufacturers may use different names to refer to the same element. Therefore, this specification and claims do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as the basis for distinction. The terms "element", "system" and "device" used in the present invention may be entities related to a computer, where the computer may be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" mentioned in the following description and claims are open terms, and should be interpreted as meaning "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as being coupled to another device in the text, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0045] Wherein, unless otherwise indicated, the corresponding numbers and symbols in different drawings of each drawing generally refer to the corresponding parts. The drawn drawings clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0046] As used herein, the terms "substantially" or "approximately" mean within an acceptable range, where those skilled in the art can solve the technical problem to be solved and substantially achieve the technical effect to be achieved. For example, "substantially equal to" means a manner with a certain error from "exactly equal to" that is acceptable to those skilled in the art without affecting the correctness of the result.

[0047] To generate a double frequency that is twice the frequency of the original clock signal, the original clock signal is subjected to an exclusive OR (XOR) operation with a delayed signal to generate a double-frequency clock signal with a double frequency, where the original clock signal is delayed by 25% of the period of the original clock signal (abbreviated as "25% delay") to generate a 25% delayed signal (i.e., a signal delayed by 25% of the period). For the spurious-related requirements of a Phase Locked Loop (PLL), it is preferred that the duty cycle of the double-frequency clock signal is equal to or substantially equal to 50% and at least two calibration operations are employed. The delay applied to the original clock signal (i.e., the aforementioned 25% delay) needs to be calibrated, and also the duty cycle of the original clock signal needs to be calibrated. The mechanism for generating a quadruple frequency that is four times the frequency of the original clock signal is similar, and in addition to the 25% delay, a 12.5% delay (understandably, i.e., a delay corresponding to 12.5% of the period of the original clock signal) also needs to be generated and calibrated. Therefore, the present invention aims to provide embodiments of duty cycle calibration, and more particularly, to calibrate the aforementioned 25% delay and / or 12.5% delay.

[0048] Figure 1 is a simplified schematic diagram of a frequency multiplier according to an embodiment of the present invention. For example, a frequency doubler 10, where the frequency doubler 10 can be applied in a PLL. As Figure 1As shown, the doubler 10 may include: at least one XOR (Exclusive OR) logic circuit (e.g., XOR logic circuit 100, which is labeled "XOR" for simplicity), a first calibration circuit (e.g., delay calibration circuit 120), a second calibration circuit (e.g., input duty cycle calibration circuit 140), and a controller (e.g., digital control circuit 160). The delay calibration circuit 120 may include a first delay cell 122 configured to provide a first delay amount τ1, where "τ1" is labeled on the first delay cell 122 for better understanding. The delay calibration circuit 120 may further include a multiplexer 124 controlled by an enable signal EN, where the enable signal EN may be transmitted from the control circuit of a phase-locked loop (PLL) or from the digital control circuit 160, but the present invention is not limited thereto. The input duty cycle calibration circuit 140 may be configured to generate an input calibration signal CK1X according to an input clock signal CKIN. For example, the input duty cycle calibration circuit 140 adjusts the duty cycle of the input clock signal CKIN to generate the input calibration signal CK1X by means of a second delay amount τ2 (which is labeled on the input duty cycle calibration circuit 140 for better understanding).

[0049] For example, when the doubler 10 operates in the calibration mode, the enable signal EN can be set to "1", and the output terminal of the first delay unit 122 is coupled to the input terminal of the first delay unit through the multiplexer 124 (for example, the first delay unit 122 and the multiplexer form a ring-oscillator (RO) type delay unit). Therefore, the first delay unit 122 is reused multiple times (for example, M times, where M is a predetermined positive integer, such as four) to delay the input calibration signal CK1X or its derived signal (for example, the derived signal of the input calibration signal CK1X) by a multiple of the first delay amount τ1 (for example, delay M×τ1) to generate a delayed signal CKOUT or its derived signal (for example, the derived signal of the delayed signal CKOUT). In another example, when the doubler 10 operates in the normal mode, the enable signal EN can be set to "0", and the signal(s) on the output terminal of the first delay unit 122 will not be fed back to the input terminal of the first delay unit 122. Therefore, the first delay unit 122 is only used once to delay the input calibration signal CK1X (or its derived signal) by the first delay amount τ1 to generate a delayed signal CKOUT, and the exclusive-OR (XOR) logic circuit 100 can be configured to perform at least one XOR operation on the input calibration signal CK1X (or its derived signal) and the final delayed signal (for example, the delayed signal CKOUT) to generate an output signal with a multiplied frequency, for example, a doubled clock signal CK2X.

[0050] In this embodiment, when the first delay unit 122 receives a rising edge, the first delay unit 122 will output a falling edge with the first delay amount τ1; and when the first delay unit 122 receives a falling edge, the first delay unit 122 will output a rising edge with the first delay amount τ1.

[0051] In this embodiment, the digital control circuit 160 can be coupled to a first calibration circuit (such as the delay calibration circuit 120) and a second calibration circuit (such as the input duty cycle calibration circuit 140), and is used to adjust the first delay amount τ1 and the second delay amount τ2 (for simplicity, labeled as "adjust τ1" and "adjust τ2") in the calibration mode. For example, the first delay unit 122 can be reused M times (for example, four times) to delay the input calibration signal CK1X (or its derived signal) by M times the first delay amount τ1 (for example, delay M×τ1) to generate a first delay signal. The digital control circuit 160 can control the first delay amount τ1 (for example, adjust τ1) according to the first delay signal to obtain a target delay amount such that M times the target delay amount is equal to one cycle period of the input clock signal CKIN. That is to say, the target delay amount is equal to 1 / M of the cycle of the input clock signal CKIN, which can be an example of the aforementioned 25% delay. After finding the target delay amount, the first delay unit 122 can be reused M / 2 times (for example, two times) to delay the input calibration signal CK1X (or its derived signal) by M / 2 times the target delay amount (which can be equal to 50% of the cycle of the input clock signal CKIN) to generate a second delay signal. The digital control circuit 160 can control the input duty cycle calibration circuit 140 according to the second delay signal so that the input calibration signal CK1X has a target duty cycle, such as 50%. For example, the second delay signal carries information related to a time interval corresponding to an exact 50% duty cycle, and this information can be used as a reference for calibrating the duty cycle of the input calibration signal CK1X.

[0052] In this embodiment, the doubler 10 may further include a phase detector (PD) 180 coupled to the digital control circuit 160. Specifically, when calibrating the first delay amount τl, the phase detector 180 may detect the phase difference between the delayed edge of the first delay signal and the target edge of the input calibration signal CK1X, and the digital control circuit 160 may control the first delay amount τ1 according to this phase difference so that the delayed edge of the first delay signal is aligned with the target edge of the input calibration signal CK1X. For example, the delayed edge of the first delay signal may be generated by delaying the first edge of the input calibration signal CK1X (or its derivative signal), and the target edge of the input calibration signal CK1X may be the second edge that is one cycle later than the first edge. That is, when the delayed edge of the first delay signal is aligned with the target edge of the input calibration signal CK1X, M×τ1 is equal to one cycle of the input clock signal CKIN (or the input calibration signal CK1X), thereby obtaining the target delay amount equal to 1 / M of the cycle of the input clock signal CKIN. After finding this target delay amount, the phase detector 180 generates another phase difference based on the second delay signal and the input calibration signal CK1X, and the digital control circuit 160 calibrates the duty cycle of the input calibration signal CK1X according to this phase difference. For ease of understanding and illustration, in the embodiments of the present invention, the delayed edge, the target edge, the first edge, and the second edge are exemplified by the rising edge, but the present invention is not limited thereto. For example, it may also be the falling edge, as long as the target delay amount equal to 1 / M of the cycle of the input clock signal CKIN can be obtained.

[0053] Figure 2 shown according to an embodiment of the present invention Figure 1Schematic diagram of the detailed circuit diagram of the doubler 10 shown. In this example, the delay calibration circuit 120 may further include a counter 126, which is coupled to the output of the first delay unit 122. During the process of calibrating the first delay amount τ1, the counter 126 may generate an edge of the first delay signal (e.g., the above-mentioned delayed edge of the first delay signal) when the first delay unit 122 has been reused M times. For example, the counter 126 receives the transition edge of the delay signal CKOUT from the first delay unit 122 at intervals of the first delay amount τ1, and when the counter 126 receives the Mth transition edge of the delay signal CKOUT from the first delay unit 122 (which means that a duration of M×τ1 has elapsed), the counter 126 may output the delayed edge of the first delay signal (e.g., the output signal of the counter 126 can be regarded as a derivative signal of the delay signal CKOUT) to the phase detector 180. During the stage of calibrating the second delay amount τ2, when the first delay unit 122 has been reused M / 2 times (e.g., when the counter 126 receives the (M / 2)th transition edge from the first delay unit 122, which means that a duration of (M / 2)×τ1 has elapsed), the counter 126 may generate an edge of the second delay signal.

[0054] As Figure 2As shown, the input duty cycle calibration circuit 140 may include an AND (AND gate) logic circuit 141 (labeled as "AND" for simplicity) and a second delay unit. The second delay unit may be configured to provide a second delay amount τ2, and the digital control circuit 160 may control the second delay amount τ2 according to the second delay signal to make the input calibration signal CK1X have a target duty cycle. In this embodiment, the second delay unit may include a unit delay component 142 (labeled as "τ2" for better understanding), a multiplexer 143, and a counter 144. The unit delay component 142 is configured to provide a unit delay, and the multiplexer 143 is controlled by a control signal CONTROL1. In addition, the input duty cycle calibration circuit 140 may further include an inverter 145 and a multiplexer 146 coupled to the second delay unit. The inverter 145 is used to generate an inverted clock signal according to the input clock signal CKIN. The multiplexer 146 is configured to select one of the input clock signal CKIN and the inverted clock signal to be sent to the second delay unit according to the comparison between the current duty cycle of the input clock signal CKIN and the target duty cycle. For example, the multiplexer 146 may select one of the input clock signal CKIN and the inverted clock signal as the selected clock signal CKIN_PL according to a polarity signal PL. The selected clock signal CKIN_PL is used to be transmitted to the second delay unit, where the polarity signal PL may represent the aforementioned comparison and may indicate whether the current duty cycle of the input clock signal CKIN is greater than the target duty cycle. Specifically, when the current duty cycle is greater than the target duty cycle, the polarity signal PL is "1", and the multiplexer 146 may select the input clock signal CKIN to be delayed by the second delay unit for calibrating the input calibration signal CK1X; when the current duty cycle is less than the target duty cycle, the polarity signal PL is "0", and the multiplexer 146 may select the inverted clock signal to be delayed by the second delay unit for calibrating the input calibration signal CK1X. In addition, the AND logic circuit 141 may perform an AND logic operation on the selected clock signal and the delay signal output from the second delay unit. The second delay unit delays the selected clock signal by the second delay amount τ2 to generate the delay signal.

[0055] Specifically, when a transition edge of the selected clock signal CKIN_PL is detected (e.g., detected by the digital control circuit 160 or the control circuit of the PLL), the control signal CONTROLl can be triggered and pulled from low to high (e.g., changed from the logical value "0" to the logical value "1"), and the output terminal of the unit delay component 142 is coupled to the input terminal of the unit delay component 142 through the multiplexer 143, thereby forming an RO-type delay cell to generate a second delay amount τ2. For example, the unit delay component 142 can be reused N1 times so that the second delay amount τ2 is equal to N1 times the unit delay provided by the unit delay component 142, where the counter 144 is configured to output a signal delayed by the second delay cell. The operation of the counter 144 can be analogized according to the operation of the counter 126, which will not be elaborated here. In this embodiment, N1 can be a positive integer, which corresponds to the digital code controlled by the digital control circuit 160, and the digital control circuit 160 can control the second delay amount τ2 by controlling the digital code, thereby controlling the number of times the unit delay component 142 is reused. It should be noted that the label "τ2" on the unit delay component 142 is only for illustration, and the second delay amount τ2 is actually generated by reusing the unit delay component 142 (e.g., τ2 is equal to N1 times the unit delay provided by the unit delay component 142).

[0056] In this embodiment, when the unit delay component 142 receives a rising edge, the unit delay component 142 will output a falling edge with that unit delay; and when the unit delay component 142 receives a falling edge, the unit delay component 142 will output a rising edge with that unit delay.

[0057] Figure 3 To illustrate the timing diagrams of some signals during the stage of calibrating the first delay amount τ1 according to an embodiment of the present invention (e.g., Figure 2 the input calibration signal CK1X, the enable signal EN, the delayed signal CKOUT finally output after being delayed M times, and the output signal of the counter 126 as shown), where the output signal of the counter 126 is represented by Figure 3 the counter output signal COUNTER in Figure 3As shown, during the odd periods of the input calibration signal CK1X, the operation of reusing the first delay amount τ1 is performed, labeled "Odd Period: Reuse Delay"; while during the even periods of the input calibration signal CK1X, the operation of calculating the adjustment of the first delay amount τ1 is performed, labeled "Even Period: Calculate". In this embodiment, at the start of the odd periods of the input calibration signal CK1X (e.g., when the first rising edge of the input calibration signal CK1X is received), the enable signal EN is triggered and pulled high, and the operation of reusing the first delay unit 122 starts. When the first delay unit 122 has been reused four times and thus generates a rising edge of the counter output signal COUNTER as shown in the circled part of Figure 3 , the phase difference between the second rising edge of the input calibration signal CK1X and this rising edge of the counter output signal COUNTER can be detected. Assume that the original value of the first delay amount is τ1', and the detected phase difference indicates that four times the first delay amount τ1' is greater than one period of the input calibration signal CK1X (or one period of the input clock signal CKIN). Accordingly, the digital control circuit 160 can adjust (e.g., reduce) the first delay amount from τ1’ to τ1 so that this rising edge of the counter output signal COUNTER is aligned with the rising edge of the input calibration signal CK1X, as shown in the circled part of Figure 3 .

[0058] In another embodiment, as shown in Figure 4 , assume that the detected phase difference indicates that four times the first delay amount τ1' is less than one period of the input calibration signal CK1X (or one period of the input clock signal CKIN). Accordingly, the digital control circuit 160 can adjust (e.g., increase) the first delay amount from τ1' to τ1 so that this rising edge of the counter output signal COUNTER is aligned with the rising edge of the input calibration signal CK1X, as shown in the circled part of Figure 4 .

[0059] Figure 5 is a timing diagram showing some signals (e.g., the input clock signal CKIN, the polarity signal PL, the selection signal CKIN_PL, the input calibration signal CK1X, the enable signal EN, the delay signal CKOUT, and Figure 2 the output signal of the counter 126 as shown) during the stage of calibrating the second delay amount τ2, where the output signal of the counter 126 is shown by the counter output signal COUNTER in Figure 5 . As shown in Figure 5As shown, the counter 126 generates a rising edge of the counter output signal COUNTER when the first delay unit 122 has been reused twice, and this rising edge can be used as a reference edge for calibrating the duty cycle of the input calibration signal CK1X. Assume that the duty cycle of the input clock signal CKIN is greater than the target duty cycle (for example, the duty cycle of the input clock signal CKIN is 53%, which is greater than 50%), the polarity signal PL is set to "1", and the input clock signal CKIN is selected as the selected clock signal CKIN_PL. The input duty cycle calibration circuit 140 reduces the time when the input calibration signal CK1X is "1" to reduce the duty cycle of the input calibration signal CK1X. More specifically, the digital control circuit 160 can adjust the second delay amount τ2 so that the falling edge of the input calibration signal CK1X aligns with this reference edge, as shown in the circled part of Figure 5 as shown.

[0060] In another embodiment, assume that the duty cycle of the input clock signal CKIN is less than the target duty cycle (for example, the duty cycle of the input clock signal CKIN is 47%, which is less than 50%), the polarity signal PL is set to "0", and the inverted clock signal generated according to the input clock signal CKIN is selected as the selected clock signal CKIN_PL. Therefore, the duty cycle of CKIN_PL can be greater than the target duty cycle (for example, the duty cycle of CKIN_PL is 53%, which is greater than 50%), as shown in Figure 6 as shown. The input duty cycle calibration circuit 140 can reduce the time when the input calibration signal CK1X is "1" to reduce the duty cycle of the input calibration signal CK1X. More specifically, the digital control circuit 160 can adjust the second delay amount τ2 so that the falling edge of the input calibration signal CK1X aligns with the reference edge, as shown in the circled part of Figure 6 as shown.

[0061] After the calibration of the first delay amount τ1 and the second delay amount τ2 is completed, the duty cycle of the input calibration signal CK1X can be equal to or substantially equal to 50%, and the first delay amount τ1 can be equal to or substantially equal to 25% of one period of the input clock signal CKIN (or the input calibration signal CK1X), as shown in Figure 7 as shown. Based on this calibration result, the XOR logic circuit 100 can generate a double-frequency clock signal CK2X by performing an XOR operation on the input calibration signal CK1X and the final delay signal CKOUT, where the duty cycle of the double-frequency clock signal can be equal to or substantially equal to 50%.

[0062] Figure 8 is a simplified schematic diagram of a frequency multiplier (for example, a quadruple frequency multiplier 80) shown according to an embodiment of the present invention, where the quadruple frequency multiplier 80 can be modified byFigure 1 obtained by the frequency doubler 10 shown. The quadrupler 80 can be applied in a phase-locked loop. In addition to the XOR logic circuit 100, the delay calibration circuit 120, the input duty cycle calibration circuit 140, and the digital control circuit 160, the quadrupler 80 may further include an XOR logic circuit 200, a third calibration circuit (e.g., the delay calibration circuit 220), and phase detectors 181 / 182. In this embodiment, the delay calibration circuit 220 may be configured to delay the input calibration signal CK1X by a third delay amount τ3 to generate a delayed signal CK1X_25, where "τ3" is marked on the delay calibration circuit 220 for better understanding. The exclusive OR (XOR) logic circuit 200 performs an exclusive OR (XOR) operation on the input calibration signal CK1X and the delayed signal CK1X_25 to generate a double-frequency clock signal CK2X, where the double-frequency clock signal CK2X may be an example of a derivative of the input calibration signal CK1X.

[0063] In this embodiment, the operation of calibrating the first delay amount τ1 can be performed by repeatedly using the first delay unit 122 M times (e.g., eight times) to delay the double-frequency clock signal CK2X by M times the first delay amount τ1 (e.g., 8×τ1) to generate a delayed signal CKOUT or its derivative. The phase detector 181 detects the phase difference between the delayed edge of the derivative of the delayed signal CKOUT and the target edge of the input calibration signal CK1X, and the digital control circuit 160 controls the first delay amount τ1 (e.g., adjusts τ1) according to this phase difference. After the calibration of the first delay amount τ1 is completed (e.g., the target delay amount of the first delay unit 122 is found), the first delay unit 122 can be repeatedly used M / 2 times (e.g., four times) to delay the double-frequency clock signal CK2X by M / 2 times the first delay amount τ1 (e.g., 4×τ1) to provide a reference edge for calibrating the duty cycle of the input calibration signal CK1X (more specifically, for calibrating / adjusting the second delay amount τ2), and the first delay unit 122 can be repeatedly used M / 4 times (e.g., two times) to delay the double-frequency clock signal CK2X by M / 4 times the first delay amount τ1 (e.g., 2×τ1) to generate a third delayed signal and provide a reference edge of the third delayed signal by means of the phase detector 182, which is used to calibrate / adjust the third delay amount τ3 (e.g., calibrate the delayed signal CK1X_25). For example, the digital control circuit 160 controls the delay calibration circuit 220 according to the third delayed signal so that the third delay amount τ3 is equal to M / 4 times the target delay amount (e.g., 2×τ1).

[0064] After the calibration of the first delay amount τ1, the second delay amount τ2, and the third delay amount τ3 is completed, the first delay unit 122 is reused M / 8 times (for example, once) to generate a final delayed signal, for example, the delayed signal CKOUT or its derivative signal in the normal mode of the quadrupler 80, and the XOR logic circuit 100 performs an XOR operation on the double-frequency clock signal CK2X and the final delayed signal (for example, the delayed signal CKOUT or its derivative signal) to generate a quadrupled clock signal CK4X. Since the calibration of the first delay amount τ1 and the second delay amount τ2 is similar to the above embodiment, the calibration of the third delay amount τ3 can be analogized based on the calibration of the first delay amount τ1 and the second delay amount τ2. For the sake of brevity, the relevant details are omitted here.

[0065] Figure 9 According to an embodiment of the present invention, Figure 8 The detailed circuit diagram of the quadruple frequency multiplier 80 is shown in FIG. 1 , wherein the delay calibration circuit 120 and the input duty cycle calibration circuit 140 are implemented in the same manner as in FIG. Figure 2 The embodiment of the present invention is the same as that of the present invention, and therefore, the relevant details are not repeated here. In the present embodiment, the multiplexer 143 is controlled by the control signal CONTROL1. In addition, the delay calibration circuit 220 may include a third delay unit configured to provide a third delay amount τ3. Similar to the second delay unit in the input duty cycle calibration circuit 140, the third delay unit may include a unit delay component 222, a multiplexer 223 and a counter 226, wherein the unit delay component 222 is configured to provide a unit delay, and the multiplexer 223 is controlled by the control signal CONTROL2. In one embodiment, the unit delay provided by the unit delay component 222 may be the same as the unit delay provided by the unit delay component 142. In other embodiments, the unit delay provided by the unit delay component 222 may be different from the unit delay provided by the unit delay component 142.

[0066] Specifically, when a transition edge of the input calibration signal CK1X is detected (e.g., detected by the digital control circuit 160 or the control circuit of the PLL), the control signal CONTROL2 is triggered and pulled high from low (e.g., from the logical value "0" to the logical value "1"), and the output terminal of the unit delay component 222 can be coupled to the input terminal of the unit delay component 222 through the multiplexer 223, so as to form an RO-type delay unit for generating a third delay amount τ3. For example, the unit delay component 222 can be reused N2 times so that the third delay amount τ3 is equal to N2 times the unit delay provided by the unit delay component 222. The counter 224 is used to output the delayed signal CK1X_25 that has passed through the third delay unit. The operation of the counter 226 can be analogized according to the operations of the counters 126 and 144. For the sake of brevity, it will not be elaborated here. In this embodiment, N2 can be a positive integer corresponding to the digital code controlled by the digital control circuit 160, and the digital control circuit 160 can control the third delay amount τ3 by controlling this digital code, thereby controlling the number of times the unit delay component 222 is reused.

[0067] In this embodiment, when the unit delay component 222 receives a rising edge, the unit delay component 222 will output a falling edge with its unit delay; and when the unit delay component 222 receives a falling edge, the unit delay component 222 will output a rising edge with its unit delay.

[0068] Figure 10 is a timing diagram of some signals (e.g., the input calibration signal CK1X, the double-frequency clock signal CK2X, the enable signal EN, the delayed signal CKOUT, and Figure 9 the output signal of the counter 126 shown in) during the stage of calibrating the first delay amount τ1, where the output signal of the counter 126 is illustrated by Figure 10 the counter output signal COUNTER in. In this embodiment, at the start of the odd cycle of the input calibration signal CK1X (more specifically, when the first rising edge of the input calibration signal CK1X is received), the enable signal EN is triggered and pulled high by the rising edge of the double-frequency clock signal CK2X, and the operation of reusing the first delay unit 122 starts. When the first delay unit 122 has been reused eight times and thus generates a rising edge of the counter output signal COUNTER as shown in the circled part in Figure 10 , the phase difference between the second rising edge of the input calibration signal CK1X and the rising edge of the counter output signal COUNTER can be detected. Figure 10It shows the case of reducing the first delay amount so that 8×τ1 is equal to one period of the input calibration signal CK1X (labeled as "Reference Period"), and the case of increasing the first delay amount τ1 for calibration can be analogized and is thus omitted here.

[0069] Figure 11 It is a timing diagram of some signals (for example, input clock signal CKIN, polarity signal PL, selected clock signal CKIN_PL, input calibration signal CK1X, enable signal EN, delay signal CKOUT, and Figure 10 the counter output signal COUNTER shown) during the stage of calibrating the second delay amount τ2. As Figure 11 shown, when the first delay unit 122 has been reused four times, the counter 126 generates a rising edge of the counter output signal COUNTER, and this rising edge is used to calibrate the duty cycle of the input calibration signal CK1X, as Figure 11 shown by the circled part in. The operations of the inverter 145 and the multiplexer 146 in the quadrupler 80 are the same as those in the doubler 10 and will not be elaborated here.

[0070] Figure 12 It is a timing diagram of some signals (for example, input clock signal CKIN, polarity signal PL, selected clock signal CKIN_PL, input calibration signal CK1X, enable signal EN, delay signal CKOUT, and Figure 10 the counter output signal COUNTER shown) during the stage of calibrating the third delay amount τ3. As Figure 12 shown, when the first delay unit 122 has been reused twice, the counter 126 can generate a rising edge of the counter output signal COUNTER, and this rising edge can be used as a reference edge for calibrating the duty cycle of the input calibration signal CK2X, as Figure 12 shown by the circled part in. Specifically, the third delay amount τ3 can be calibrated to be equal to twice the first delay amount τ1, and the third delay amount τ3 is equal to 25% of one period of the input calibration signal CK1X.

[0071] After the calibration of the first delay amount τ1, the second delay amount τ2, and the third delay amount τ3 is completed, the duty cycle of the input calibration signal CK1X can be equal to or substantially equal to 50%, the third delay amount τ3 (which corresponds to the duty cycle of the double-frequency clock signal CK2X) can be equal to or substantially equal to 25% of one period of the input clock signal CKIN (or the input calibration signal CK1X), and the first delay amount τ1 (which corresponds to the duty cycle of the quadruple-frequency clock signal CK4X) can be equal to or substantially equal to 12.5% of one period of the input clock signal CKIN (or the input calibration signal CK1X), asFigure 13 As shown. Based on this calibration result, the duty cycle of the quadrupled clock signal CK4X generated by the XOR (exclusive OR) logic circuit 100 can be equal to or substantially equal to 50%.

[0072] Figure 14 FIG. is a schematic flowchart of the working process of the delay-reused duty cycle calibration method provided by an embodiment of the present invention. Among them, the delay-reused duty cycle calibration method can be applied to frequency multipliers, such as a doubler 10, a quadrupler 80, etc. It should be noted that Figure 14 The working process shown is only for illustrative purposes and does not mean a limitation to the present invention. In Figure 14 One or more steps can be added, deleted, or modified in the working process shown. Additionally, if the same result can be obtained, these steps do not have to be executed in the Figure 14 exact order shown.

[0073] In step 1410, the frequency multiplier can couple the output terminal of the first delay unit (e.g., the first delay unit 122) to the input terminal of the first delay unit through a first calibration circuit (e.g., the delay calibration circuit 120). Among them, the first calibration circuit includes a first delay unit, the first delay unit is configured to provide a first delay amount (e.g., τ1), and the first delay unit is reused M times to delay the input calibration signal (e.g., the input calibration signal CK1X) or its derived signal (e.g., the doubled clock signal CK2X) by M times the first delay amount to generate a first delay signal.

[0074] In step 1420, the frequency multiplier can control the first delay amount according to the first delay signal by a controller (e.g., the digital control circuit 160) to find the target delay amount of the first delay unit, such that M times the target delay amount is equal to one period of the input clock signal (e.g., the input clock signal CKIN), where the input calibration signal is generated by a second calibration circuit (e.g., the input duty cycle calibration circuit 140) according to the input clock signal.

[0075] In step 1430, after finding the target delay amount, the frequency multiplier can reuse the first delay unit M / 2 times to delay the input calibration signal or its derived signal by M / 2 times the target delay amount to generate a second delay signal.

[0076] In step 1440, the frequency multiplier can control the second calibration circuit according to the second delay signal to make the input calibration signal have a target duty cycle (e.g., 50%).

[0077] It should be noted that the order of calibrating the second delay amount τ2 and the third delay amount τ3 is not a limitation to the present invention. Once the operation of calibrating the first delay amount τ1 is completed (for example, when the target delay amount of the first delay unit 122 is established / found), the order of calibrating the second delay amount τ2 and the third delay amount τ3 can be changed.

[0078] It should be noted that the value of M does not mean a limitation to the present invention. More specifically, if the value of M increases (referred to as a higher reuse / multiplexing times), the first delay amount τ1 can be reduced because τ1 is expected to be 1 / M times the period of the input clock signal CKIN, and the circuit area of the first delay unit can be reduced. However, a higher multiplexing times will result in a lower resolution for adjusting τ1 / τ2 / τ3, and the spurious-related performance of the PLL will be reduced. Therefore, there is a trade-off between the multiplexing times (which corresponds to the circuit area cost) and the resolution (which corresponds to the spurious-related performance). Under certain spurious-related requirements (such as <80dBc), the optimized M value (for example, 32) of the doubler 10 can be obtained through simulation, and under certain spurious-related requirements (such as <80dBc), the optimized M value (for example, 16) of the quadrupler 80 can be obtained through simulation.

[0079] The counters 126, 144, and 226 are preferably implemented by a binary counter, and preferably, the value of M is a power of 2 (for example, 4, 8, 16, 32, 64, 128, etc.), but the present invention is not limited thereto. Any multiple of four can be applied to the value of M in the doubler 10, and any multiple of eight can be applied to the value of M in the quadrupler 80. It should be noted that certain M values may cause the first delay amount τ1 to be repeatedly calibrated as a decimal percentage of the period of the input clock signal CKIN (for example, for the doubler 10, when M = 12, the first delay amount τ1 is calibrated to be approximately 8.3333% of the period; and for the quadrupler 80, when M = 24, the first delay amount τ1 is calibrated to be approximately 4.1667% of the period. However, as long as the resolution of adjusting τ1 / τ2 / τ3 is small enough, the error introduced by the repeated decimal percentage will not be the dominant term in the overall quantization error of the calibration.

[0080] Preferably, any one (e.g., each) of the unit delay components 142 and 222 is implemented by a fixed delay component (e.g., an inverter with a fixed propagation delay), wherein the operation of adjusting the second delay amount τ2 can be performed by adjusting the number of times of multiplexing of the unit delay component 142 (e.g., N1), and the operation of adjusting the second delay amount τ2 can be performed by adjusting the number of times of multiplexing of the unit delay component 142 (e.g., N1), but the present invention is not limited thereto. In some embodiments, any one of the second delay unit and the third delay unit can be implemented by an analog circuit, and the operation of adjusting the second delay amount τ2 and / or the third delay amount τ3 can be performed in an analog manner (e.g., adjusting the propagation load or drive strength in the second delay unit and / or the third delay unit). Similarly, the operation of adjusting the first delay amount τ1 provided by the first delay unit 122 is not limited to any specific mechanism, wherein, Figure 2 and Figure 9 the operations of adjusting the second delay amount τ2 and the third delay amount τ3 described in the embodiments of can be applied to the operation of adjusting the first delay amount τ1, but the present invention is not limited thereto. In some embodiments, the operation of adjusting the first delay amount τ1 can be performed in a similar manner as described above. Since the first delay unit 122 is reused M times to obtain an accurate time interval corresponding to 1 / M cycles of the input clock signal CKIN, and is further reused M / 2 times, M / 4 times, and M / 8 times to generate accurate time intervals corresponding to 50%, 25%, and 12.5% of the cycle of the input clock signal CKIN, adjusting the first delay amount τ1 in an analog manner is not affected by analog circuit-related problems such as device mismatch or offset, and can ensure the accuracy of the time intervals corresponding to 50%, 25%, and 12.5% of the cycle of the input clock signal CKIN.

[0081] Although the present invention has been described by way of examples and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar structures (as would be apparent to those skilled in the art), e.g., combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A frequency multiplier, characterized in that, The frequency multiplier includes a first calibration circuit, a second calibration circuit, and a controller. Among them, the first calibration circuit includes: A first delay unit for providing a first delay amount; Among them, in the calibration mode of the frequency multiplier, the output end of the first delay unit is coupled to the input end of the first delay unit through a multiplexer to feedback the signal on the output end of the first delay unit to the input end of the first delay unit. The first delay unit is reused M times to delay the input calibration signal or its derived signal by M times the first delay amount to generate a first delay signal, where M is a predetermined positive integer; The second calibration circuit is used to generate the input calibration signal according to the input clock signal; and, The controller is coupled to the first calibration circuit and the second calibration circuit. Among them, the controller controls the first delay amount according to the first delay signal to obtain a target delay amount, where M times the target delay amount is equal to one cycle of the input clock signal; after obtaining the target delay amount, the first delay unit is reused M / 2 times to delay the input calibration signal or its derived signal by M / 2 times the target delay amount to generate a second delay signal; and the controller controls the second calibration circuit according to the second delay signal to make the input calibration signal have a target duty cycle.

2. The frequency doubler according to claim 1, characterized in that, The frequency multiplier further includes: A phase detector coupled to the controller for detecting the phase difference between the delay edge of the first delay signal and the target edge of the input calibration signal; Among them, the controller controls the first delay amount to align the delay edge of the first delay signal with the target edge of the input calibration signal.

3. The frequency doubler according to claim 2, characterized in that, The delay edge of the first delay signal is generated by delaying the first edge of the input calibration signal or its derived signal, and the target edge of the input calibration signal is the second edge that is one cycle later than the first edge.

4. The frequency doubler according to claim 2, characterized in that, The first calibration circuit further includes: A counter coupled to the output end of the first delay unit, where the counter generates the delay edge of the first delay signal when the first delay unit is reused M times.

5. The frequency doubler according to claim 1, characterized in that, The second calibration circuit includes: A second delay unit for providing a second delay amount; Among them, the controller controls the second delay amount according to the second delay signal to make the input calibration signal have the target duty cycle.

6. The frequency multiplier according to claim 5, characterized in that, The second delay unit includes: A unit delay component for providing a unit delay, where the output end of the unit delay component is coupled to the input end of the unit delay component; Among them, the unit delay component is reused N times to make the second delay amount equal to N times the unit delay, and N is a positive integer corresponding to the digital code controlled by the controller.

7. The frequency doubler according to claim 5, characterized in that The second calibration circuit further includes: An inverter for generating an inverted clock signal according to the input clock signal; and, A multiplexer coupled to the second delay unit for selecting one of the input clock signal and the inverted clock signal to send to the second delay unit according to the comparison between the current duty cycle of the input clock signal and the target duty cycle.

8. The frequency multiplier according to claim 7, characterized in that: When the current duty cycle is greater than the target duty cycle, the multiplexer selects that the input clock signal will be delayed by the second delay unit for calibrating the input calibration signal; And, When the current duty cycle is less than the target duty cycle, the multiplexer selects that the inverted clock signal will be delayed by the second delay unit for calibrating the input calibration signal.

9. The frequency doubler according to claim 1, wherein The frequency multiplier further includes a third calibration circuit, and the third calibration circuit includes: A third delay unit for providing a third delay amount; Wherein, after obtaining the target delay amount, the first delay unit is reused M / 4 times to delay the input calibration signal or its derived signal by M / 4 times the target delay amount to generate a third delay signal; and, the controller controls the third calibration circuit according to the third delay signal so that the third delay amount is equal to M / 4 times the target delay amount.

10. The frequency doubler according to claim 1, characterized in that, The frequency multiplier further includes: At least one exclusive OR (XOR) logic circuit, coupled to the first calibration circuit, for performing at least one XOR operation on the input calibration signal or its derived signal and the final delay signal in the normal mode of the frequency multiplier to generate a frequency-multiplied output signal, wherein the final delay signal is generated by using the first delay unit M / 4 times to delay the input calibration signal by M / 4 times the target delay amount; or, the final delay signal is generated by using the first delay unit M / 8 times to delay the derived signal of the input calibration signal by M / 8 times the target delay amount.

11. A delay multiplexing duty cycle calibration method, wherein, The method includes: Coupling the output terminal of the first delay unit to the input terminal of the first delay unit through a multiplexer to feedback the signal on the output terminal of the first delay unit to the input terminal of the first delay unit, wherein the first delay unit is located in the first calibration circuit for providing a first delay amount, and the first delay unit is reused M times to delay the input calibration signal or its derived signal by M times the first delay amount to generate a first delay signal, where M is a predetermined positive integer; The controller controls the first delay amount according to the first delay signal to obtain the target delay amount of the first delay unit such that M times the target delay amount is equal to one period of the input clock signal, wherein the input calibration signal is generated by the second calibration circuit according to the input clock signal; After obtaining the target delay amount, the first delay unit is reused M / 2 times to delay the input calibration signal or its derived signal by M / 2 times the target delay amount to generate a second delay signal; and, Controlling the second calibration circuit according to the second delay signal so that the input calibration signal has a target duty cycle.

12. The delay multiplexing duty cycle calibration method according to claim 11, wherein The controller controls the first delay amount according to the first delay signal to obtain the target delay amount, which includes: Detecting the phase difference between the delay edge of the first delay signal and the target edge of the input calibration signal; and, Controlling the first delay amount so that the delay edge of the first delay signal is aligned with the target edge of the input calibration signal.

13. The delay multiplexing duty cycle calibration method according to claim 12, characterized in that The delayed edge of the first delay signal is generated by delaying the first edge of the input calibration signal or its derivative signal, and the target edge of the input calibration signal is a second edge that is one cycle later than the first edge.

14. The duty cycle calibration method for delay multiplexing according to claim 12, wherein The output terminal of the first delay unit is coupled to a counter, and the counter generates the delayed edge of the first delay signal when the first delay unit is reused M times.

15. The duty cycle calibration method for delay multiplexing according to claim 11, wherein The second calibration circuit includes a second delay unit for providing a second delay amount, and controlling the second calibration circuit according to the second delay signal to make the input calibration signal have the target duty cycle includes: Controlling the second delay amount according to the second delay signal to make the input calibration signal have the target duty cycle.

16. The duty cycle calibration method for delay multiplexing according to claim 15, wherein The second delay unit includes unit delay components for providing unit delays, the output terminal of the unit delay component is coupled to the input terminal of the unit delay component, and controlling the second delay amount includes: Reusing the unit delay component N times to make the second delay amount equal to N times the unit delay, where N is a positive integer corresponding to the digital code controlled by the controller.

17. The delay multiplexing duty cycle calibration method according to claim 15, characterized in that Controlling the second calibration circuit according to the second delay signal to make the input calibration signal have the target duty cycle further includes: selecting one of the input clock signal and the inverted clock signal according to the comparison between the current duty cycle of the input clock signal and the target duty cycle and sending it to the second delay unit, where the inverted clock signal is the inverted signal of the input clock signal.

18. The duty cycle calibration method for delay multiplexing according to claim 17, wherein Selecting one of the input clock signal and the inverted clock signal according to the comparison between the current duty cycle of the input clock signal and the target duty cycle and sending it to the second delay unit includes: In response to a comparison indicating that the current duty cycle is greater than the target duty cycle, selecting the input clock signal to be delayed by the second delay unit for calibrating the input calibration signal.

19. The delay multiplexing duty cycle calibration method according to claim 17, characterized in that, Selecting one of the input clock signal and the inverted clock signal according to the comparison between the current duty cycle of the input clock signal and the target duty cycle and sending it to the second delay unit includes: In response to a comparison indicating that the current duty cycle is less than the target duty cycle, selecting the inverted clock signal to be delayed by the second delay unit for calibrating the input calibration signal.

20. The duty cycle calibration method for delay multiplexing according to claim 11, wherein The method further includes: After obtaining the target delay amount, reusing the first delay unit M / 4 times to delay the input calibration signal or its derivative signal by M / 4 times the target delay amount to generate a third delay signal; And, Controlling a third calibration circuit according to the third delay signal to make the third delay amount provided by a third delay unit in the third calibration circuit equal to M / 4 times the target delay amount.

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