Adaptive Read Voltage Adjustment Using Margin Error Statistics of a Memory Whose Error Rate Varies over Time

Abstract

A processing device is configured to: identify a first range among a plurality of write-read latency ranges of a memory component; identify a first set of the plurality of write-read latency times at a first end of the first range and a second set of the plurality of write-read latency times at a second end of the first range; determine a first error rate of the memory component corresponding to the first set of the plurality of write-read latency times and a second error rate of the memory component corresponding to the second set of the plurality of write-read latency times; determine whether a correspondence relationship between the first error rate and the second error rate satisfies a first threshold criterion; and modify a read voltage level associated with the first range.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to adaptive read voltage adjustment using boundary error statistics of memories with error rates that vary over time. Background Art

[0002] A memory subsystem may be a storage system, a memory module, or a combination of a storage device and a memory module. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system may use the memory subsystem to store data at the memory components and retrieve data from the memory components. Brief Description of the Drawings

[0003] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 An example computing environment including a memory subsystem is shown in accordance with some embodiments of the present disclosure.

[0005] Figure 2 is a flowchart of an example method for adjusting a read voltage level based on cumulative boundary RBER statistics of a memory with an error rate that varies over time in accordance with some embodiments of the present disclosure.

[0006] Figure 3A is a graph showing bit error rates varying with write-to-read delay for three read voltage levels in accordance with some embodiments of the present disclosure.

[0007] Figure 3B is a graph showing cumulative boundary raw bit error rate statistics of a memory with an error rate that varies over time in accordance with some embodiments of the present disclosure.

[0008] Figure 4 is a flowchart of an example method for determining error rates of a set of write-to-read delay times at the boundary of a write-to-read delay time range in accordance with some embodiments of the present disclosure.

[0009] Figure 5 is a flowchart of an example method for performing a read operation using a dynamically adjusted read voltage level based on boundary error statistics in accordance with some embodiments of the present disclosure.

[0010] Figure 6 is a flowchart of an example method for adjusting a read voltage level based on cumulative directional RBER statistics of a memory with an error rate that varies over time in accordance with some embodiments of the present disclosure.

[0011] Figure 7 A graph showing cumulative directional raw bit error rate statistics of a memory where the error rate varies over time, according to some embodiments of the present disclosure.

[0012] Figure 8 A flowchart of an example method for determining a directional error rate for a set of write / read latency times within a write / read latency time range, according to some embodiments of the present disclosure.

[0013] Figure 9 A flowchart of an example method for performing a read operation using dynamically adjusted read voltage levels based on directional error statistics, according to some embodiments of the present disclosure.

[0014] Figure 10 A block diagram of an example computer system in which embodiments of the present disclosure may be operative. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure are directed to adaptive read voltage adjustment for memories in a memory subsystem where the error rate varies over time. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 description. Generally, a host system may use a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include multiple memory components that can store data from the host system. Depending on the implementation, each memory component may include the same or different types of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory, and flash-based memories such as single-level cell (SLC) memories, multi-level cell (MLC) memories, three-level cell (TLC) memories, or quad-level cell (QLC) memories. The characteristics of different types of media may vary. An example of a characteristic associated with a memory component is data density. Data density corresponds to the amount of data (e.g., data bits) that can be stored in each memory cell of the memory component. Using an example of a flash-based memory, a QLC memory may store four data bits, while an SLC memory may store one data bit. Accordingly, a memory component that includes QLC memory cells will have a higher data density than a memory component that includes SLC memory cells. Another example of a characteristic of a memory component is access speed. Access speed corresponds to the amount of time it takes for the memory component to access data stored at the memory component.

[0017] Other characteristics of the memory component may be associated with the durability of the memory component to store data. When data is written to and / or erased from the memory cells of the memory component, the memory cells may be damaged to some extent. As the number of write operations and / or erase operations performed on the memory cells increases, the probability that the data stored at the memory cells contains errors increases, and the memory cells are damaged more and more severely. The characteristic associated with the durability of the memory component is the number of write operations or the number of program / erase operations performed on the memory cells of the memory component. The increasing number of read and write operations may result in the data stored at the memory cells having a high error rate. This may increase the use of error recovery operations, which include but are not limited to read retry (i.e., sensing the memory component again) and RAID (Redundant Array of Independent Disks) for subsequent data operations (e.g., read and / or write) performed on the memory cells. The increased use of error recovery operations may result in a degradation in the performance of the conventional memory subsystem. Additionally, when the error rate of the memory cells or data blocks continues to increase, it may even exceed the error recovery capabilities of the memory subsystem, resulting in the lost data being irreparable. Furthermore, since the memory subsystem has more resources for performing error recovery operations, fewer resources are available for performing other read or write operations.

[0018] Accordingly, after performing a threshold number of read and / or write operations on a data block, the memory subsystem may perform a data integrity check (also referred to herein as a “scan”) to verify that the data stored at the data block remains at an appropriate reliability level. During the data integrity check, a series of read and / or write operations are invoked, and one or more reliability statistics of the data stored at the data block are determined. An example of a reliability statistic is the raw bit error rate (RBER). The RBER can be defined as the ratio of the number of error bits to the number of all data bits stored in the data block.

[0019] For a particular memory type (i.e., for a memory subsystem employing a particular type of storage media), the error rate can vary over time. Specifically, the threshold voltage (Vt) distribution of some non-volatile memories (e.g., NAND, phase change, etc.) shifts over time. At a given read level (i.e., the voltage applied to a memory cell as part of a read operation), if the Vt distribution shifts, then the RBER may also be affected. For any Vt distribution at a given moment, there may be an optimal read level (or range of read levels) that minimizes the expected RBER. Specifically, the Vt distribution and the RBER can be functions of the write-to-read (W2R) latency (i.e., the time period between when data is written to a memory component and when the data is read from the memory component). Due to this time-varying nature of the RBER and other noise mechanisms in the memory, a single read level may not be sufficient to achieve an error rate that meets a particular system reliability goal. Thus, a particular memory subsystem may have several pre-programmed read voltage levels, each corresponding to a different range of W2R latency times. For example, a first read voltage level may be used to read data with a W2R latency time in a first corresponding range, a second read voltage level may be used to read data with a W2R latency time in a second corresponding range, and so on.

[0020] In many conventional memory subsystems, the read voltage levels for each range of W2R latency times are pre-programmed and never adjusted during the use of the underlying memory components. These pre-programmed read voltage levels may not be set to optimal values during manufacturing or may not remain optimal during the lifespan of the memory components, resulting in an increase in the error rate. For example, the Vt distribution may be constantly affected by interference from itself or adjacent cells, circuit system noise, temperature, etc., which means that the optimal read voltage should also change accordingly. Due to wear on the memory cells and changes in the physical and / or electrical characteristics of the memory cells, the optimal read voltage may also gradually shift over time. Using sub-optimal read voltage levels may result in partial write effects, an increase in RBER, and a high read retry trigger rate. This can lead to a reduction in the performance of the memory subsystem, as well as an increase in the power consumption of the memory subsystem. System bandwidth and other resources may also be occupied for longer periods, preventing these resources from being used for other functions.

[0021] Aspects of the present disclosure address the above and other deficiencies by using an adaptive in - operation read voltage adjustment scheme based on cumulative boundary RBER statistics of a memory based on the variation of error rate over time. In one embodiment, the memory subsystem identifies a first range among a plurality of write - to - read latency ranges of a memory component, where the first range represents a plurality of write - to - read latency times, and the associated read voltage level is used to perform a read operation on a segment of the memory component having a write - to - read latency time within the first range. The memory subsystem further identifies a first set of a plurality of write - to - read latency times at a first end (i.e., the first boundary) of the first range and a second set of a plurality of write - to - read latency times at a second end (i.e., the second boundary) of the first range, and determines a first error rate of the memory component corresponding to the first set of write - to - read latency times and a second error rate of the memory component corresponding to the second set of write - to - read latency times. The memory subsystem determines whether a correspondence relationship (e.g., the ratio of the first error rate to the second error rate, the difference between the first error rate and the second error rate, etc.) between the first error rate and the second error rate satisfies a first threshold criterion, which may be based, for example, on the desired reliability and performance characteristics of the memory subsystem. If the correspondence relationship between the first error rate and the second error rate satisfies the first threshold criterion, then the memory subsystem may maintain the read voltage level at the current level. Alternatively, in response to the correspondence relationship between the first error rate and the second error rate not satisfying the first threshold criterion, the memory subsystem may modify the read voltage level associated with the first range as needed.

[0022] The read voltage adjustment scheme described herein allows adjustment of manufacturing trim values, which may initially be set sub - optimally or may become sub - optimal over time. Adjusting the read voltage levels for different W2R latency time ranges can minimize the harmful effects of various interferences on the memory component and reduce the read retry trigger rate, thereby improving throughput and latency in the memory subsystem. Additionally, read voltage adjustment can reduce the partial write effect and lower the risk that the memory subsystem fails to meet the host system reliability goals. Finally, reducing the RBER can improve performance, reduce the power consumption associated with error correction / recovery operations, and free system resources for other functions. The memory controller can spend less time performing error recovery operations, thus allowing the controller more time to handle other data access operations of the memory component.

[0023] Figure 1FIG. 0 illustrates an example computing environment 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 can include media, such as memory components 112A-112N. The memory components 112A-112N can be volatile memory components, non-volatile memory components, or a combination thereof. The memory subsystem 110 can be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing environment 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 FIG. 5 illustrates an example of a host system 120 coupled to a memory subsystem 110. The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, and the connection can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including, for example, electrical, optical, magnetic, etc. connections.

[0025] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., included in a vehicle, an industrial device, or an Internet-of-Things (IoT) device), or a computing device that includes a memory and a processing device. The host system 120 may include or be coupled to a memory subsystem 110 such that the host system 120 can read data from or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, and the connection can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including, for example, electrical, optical, magnetic, etc. connections. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further use a Non-Volatile Memory Express (NVMe) interface to access memory components 112A to 112N when the memory subsystem 110 is coupled to the host system 120 via a PCIe interface. The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0026] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND (Negative-And) type flash memory. Each of memory components 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., triple-level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component may include an SLC portion and an MLC portion of memory cells. Each memory cell may store one or more data bits (e.g., data blocks) for use by host system 120. Although non-volatile memory components such as NAND type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR (Not-Or) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory may perform in-situ write operations, where non-volatile memory cells may be programmed without their prior erasure. Further, the memory cells of memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to the units of the memory components for storing data. Data blocks may be further grouped into one or more planes on each of memory components 112A to 112N, where operations may be performed simultaneously on each plane. Corresponding data blocks from different planes may be associated with each other in a stripe rather than across multiple planes.

[0027] The memory system controller 115 (hereinafter referred to as "controller") can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N and other such operations. The controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling the communication between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers for storing memory metrics, acquired data, counters 118, etc. The local memory 119 can also include a read only memory (ROM) for storing microcode. Although Figure 1 the illustrated example memory subsystem 110 has been shown to include the controller 115, in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115 and instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0028] Generally, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to enable the desired access to the memory components 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 can further include host interface circuitry that communicates with the host system 120 through a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions for accessing the memory components 112A to 112N and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0029] Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive an address from controller 115 and decode the address to access memory components 112A through 112N.

[0030] Memory subsystem 110 includes a read voltage adjustment component 113 that may be used to perform a marginal RBER calculation and adjust the read voltage levels of data blocks of memory components 112A through 112N. In one embodiment, read voltage adjustment component 113 identifies a first range among a plurality of write-to-read (W2R) latency ranges of a memory component (e.g., one of memory components 112A through 112N). The first range represents a plurality of write-to-read (W2R) latency times, and the associated read voltage level is used to perform a read operation on a segment of the memory component having a W2R latency time in the first range. Read voltage adjustment component 113 may further identify a first set of a plurality of write-to-read latency times at a first end (i.e., a first boundary) of the first range and a second set of a plurality of write-to-read latency times at a second end (i.e., a second boundary) of the first range, and determine a first error rate of the memory component corresponding to the first set of a plurality of write-to-read latency times and a second error rate of the memory component corresponding to the second set of a plurality of write-to-read latency times. Read voltage adjustment component 113 may determine whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, which may be based, for example, on the desired reliability and performance characteristics of the memory subsystem. If the correspondence satisfies the first threshold criterion, then read voltage adjustment component 113 may maintain the read voltage level at the current level. However, in response to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, read voltage adjustment component 113 may modify the read voltage level associated with the first range as needed so that the correspondence (e.g., a ratio) deviates from a target ratio defined by the first threshold criterion by no more than a threshold amount. Other details regarding the operation of read voltage adjustment component 113 are described below.

[0031] Figure 2 is a flowchart of an example method for adjusting a read voltage level based on cumulative marginal RBER statistics of an error rate-versus-time memory according to some embodiments of the present disclosure. Method 200 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by Figure 1is performed by the read voltage adjustment component 113. Although shown in a particular order or sequence, the process order may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in different orders and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0032] At operation 210, the processing logic identifies a first range (e.g., the W2R range 310) of a plurality of write-read latency ranges of the memory component, where the first range represents a plurality of write-read latency times and the associated read voltage level (e.g., read level 1) is used to perform a read operation on a segment of the memory component having a write-read latency time in the first range, as Figure 3A shown. Figure 3AFIG. 300 shows a graph showing bit error rate (BER) versus write-to-read (W2R) latency for three read voltage levels, according to some embodiments of the present disclosure. As described herein, the Vt distribution may shift over time. For example, for a given read voltage level, such as a first read voltage level (labeled read level 1), the bit error rate experienced when performing a read operation using this read voltage level may change over time due to the shift in the Vt distribution. Similarly, the corresponding bit error rates for a second read voltage level (labeled read level 2) or a third read voltage level (labeled read level 3) also change over time. In these or other cases, the Vt distribution and the bit error rate may be a function of the W2R latency. Graph 300 shows each of the three read voltage levels corresponding to different W2R latency time ranges, such as W2R range 310, W2R range 320, and W2R range 330, which may be design goals of the memory subsystem specification. In other embodiments, there may be any other number of W2R latency time ranges and associated read voltage levels. In graph 300, the measured BER of read operations performed using a specified read voltage level is shown. For example, BER curve 312 represents the BER measured for read operations performed using read level 1 on segments at different W2R latency times, BER curve 322 represents the BER measured for read operations performed using read level 2 on segments at different W2R latency times, and BER curve 332 represents the BER measured for read operations performed using read level 3 on segments at different W2R latency times. From graph 300, it is evident that using read level 1 results in a lower BER for read operations performed on segments of the memory component having a W2R latency time in W2R range 310, using read level 2 results in a lower BER for read operations performed on segments of the memory component having a W2R latency time in W2R range 320, and using read level 3 results in a lower BER for read operations performed on segments of the memory component having a W2R latency time in W2R range 330. Graph 300 also shows that for a single read voltage level (e.g., read level 2), the BER increases at lower W2R latency times (i.e., W2R range 310) and at higher W2R latency times (i.e., W2R range 330). The values of read level 1, read level 2, and read level 3 may be set during the manufacture of the memory component, but may become sub-optimal at certain points in time due to the passage of time and other factors associated with the use of the memory component. Adjusting the read voltage levels based on the accumulated bound RBER statistics can bring those read voltage levels back to the point where the BER is optimized (or at least reduced) for the corresponding W2R latency time range.

[0033] Refer again to Figure 2, at operation 220, the processing logic identifies a first set 314 of a plurality of write-read latency times at a first end (i.e., boundary) of a first range (i.e., the W2R range 310) and a second set 316 of a plurality of write-read latency times at a second end (i.e., boundary) of the first range, as Figure 3B shown. Figure 3B FIG. 350 is a graph showing cumulative boundary RBER statistics of a memory in which the error rate changes over time, according to some embodiments of the present disclosure. In one implementation, the first set 314 includes the smaller set of the smallest W2R latency times in the W2R range 310, and the second set includes the smaller set of the highest W2R latency times in the W2R range 310. The W2R range 320 may similarly have a first set 324 and a second set 326, and the W2R range 330 may have a first set 334 and a second set 336. The sizes of the first set 314 and the second set 316 may be configurable parameters and may include a fixed number of W2R latency times (e.g., 5 of the smallest W2R latency times or 5 of the highest W2R latency times in the W2R range 310) or a certain percentage of all the W2R latency times in the W2R range 310 (e.g., the smallest 1% or the highest 1%). In one implementation, the boundary between the W2R range 310 and the W2R range 320 may be set according to the intersection point of the curves 312 and 322, and the boundary between the W2R range 320 and the W2R range 330 may be set according to the intersection point of the curves 322 and 332. Since the error rate may change over time due to physical changes of the associated memory cells, wear leveling, temperature, etc., these boundaries may also shift over time to optimize the BER. Additionally, changing the system design goals may also affect the positions of these boundaries.

[0034] Referring again to Figure 2, at operation 230, the processing logic determines a first error rate of the memory component corresponding to the first set 314 of multiple write-to-read latency times and a second error rate of the memory component corresponding to the second set 316 of multiple write-to-read latency times. In one embodiment, the read voltage adjustment component 113 performs a data integrity scan of the memory component to determine the error rate for each segment (e.g., data block). During the scan, the read voltage adjustment component 113 identifies one or more reliability statistics, such as the raw bit error rate (RBER) defined as the ratio of the number of error bits to the number of all data bits stored in the data block. In one example, during the scan, the read voltage adjustment component 113 writes and reads the original codewords (i.e., a fixed number of bits in a sequence) from the data block, where the controlled W2R latency is in the first set 314 or the second set 316. The read voltage adjustment component 113 can apply the original codeword to an error correction code (ECC) decoder to generate a decoded codeword and compare the decoded codeword with the original codeword. The read voltage adjustment component 113 can count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits (i.e., error bits) to the total number of bits in the codeword represents the RBER. The read voltage adjustment component 113 can repeat this process for additional codewords where the W2R latency is evenly distributed within 314 and 316 until the entire block has been scanned. In another embodiment, the read voltage adjustment component 113 can use various counters 118 to determine the error rate, as described in more detail with respect to Figure 4 more detailedly described.

[0035] At operation 240, the processing logic determines whether a correspondence between a first error rate and a second error rate meets a first threshold criterion. In one implementation, the read voltage adjustment component 113 determines a ratio of the first error rate to the second error rate and compares the ratio to a target ratio. In one implementation, the target ratio can be one, such that the first error rate is as close as possible to the second error rate. Accordingly, the read voltage adjustment component 113 can compare the first error rate to the second error rate and determine whether the difference between the first error rate and the second error rate is no more than a threshold amount. If the ratio is close enough to one (i.e., if the difference between the first error rate and the second error rate is within the threshold amount), then the read voltage adjustment component 113 can determine that the threshold criterion is met. In other implementations, the target ratio can be some other value set in view of the desired reliability and performance requirements of the memory subsystem. For example, in some cases, a particular read level may be preferred to be optimized based on the entire W2R range of the memory subsystem. In another implementation, it may be desirable for the first error rate at the first boundary of a certain W2R range to be lower than the second error rate at the second boundary, or vice versa. Accordingly, the target ratio can have some value other than one. If the ratio is close enough to the target ratio (i.e., if the difference between the ratio and the target ratio is no more than the threshold amount), then the read voltage adjustment component 113 can determine that the threshold criterion is met.

[0036] In response to the correspondence between the first error rate and the second error rate meeting the first threshold criterion, at operation 250, the processing logic maintains the read voltage level associated with the first range at the current level. In response to the correspondence between the first error rate and the second error rate not meeting the first threshold criterion, at operation 260, the processing logic modifies the read voltage level associated with the first range. In one implementation, the read voltage adjustment component 113 can adjust the read voltage level such that the ratio of the first error rate to the second error rate meets the first threshold criterion. This can include, for example, increasing or decreasing the read voltage level by a certain amount, re-measuring the error rates at each boundary, and determining whether the ratio is closer to the target ratio. The read voltage adjustment component 113 can repeat this iterative process until the threshold criterion is met. Once the appropriate modified read voltage level is determined, the read voltage adjustment component 113 can store this read voltage level for future read operations for data having a W2R latency in the corresponding range.

[0037] Figure 4is a flowchart of an example method for determining an error rate of a set of write-read latency times at the boundary of a write-read latency time range according to some embodiments of the present disclosure. Method 400 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is executed by Figure 1 the read voltage adjustment component 113. Although shown in a particular order or sequence, the process order may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0038] At operation 410, the processing logic monitors read operations being performed on a segment of a memory component having a write-read latency time that is within a first set (e.g., 314 and / or 316) of a plurality of write-read latency times. In one implementation, the read voltage adjustment component 113 may receive a request to perform a read operation from the host system 120, perform any address mapping operations to identify the physical address in the memory that the read operation is directed to, and determine the corresponding W2R latency time for the address. The W2R latency time may represent the difference between a first time when data is written to the physical address and a second time when a read request is received from the host system 120. Depending on the implementation, the W2R latency time may be calculated based on the difference between the current time and a timestamp (indicating the write time) that may be stored with the data at the physical address on the memory component or stored in some other data storage device separate from the memory component (e.g., the local memory 119), or the W2R latency time may be calculated in some other manner by the read voltage adjustment component 113. In another implementation, the actual read operation is not received from the host system 120, but rather the read voltage adjustment component 113 may intentionally issue a request to read data known to have an appropriate W2R latency time. Although the operations of method 400 are described with respect to a first set (e.g., 314) of W2R latency times of a first range (e.g., the W2R range 310), the same or similar operations may be performed for different sets (e.g., 316) or different ranges (e.g., the W2R range 320 or 330).

[0039] At operation 420, the processing logic increments a first counter in counter 118 in response to each failed bit detected in the read operation. For reads in the identified group 314, the read voltage adjustment component 113 reads the original codeword, applies the codeword to an error correction code (ECC) decoder to generate a decoded codeword, and compares the decoded codeword with the original codeword. The read voltage adjustment component 113 may increment the first counter in response to each bit flipped in the decoded codeword. At operation 430, the processing logic increments a second counter in counter 118 in response to each bit in each codeword decoded in the read operation.

[0040] At operation 440, the processing logic determines whether the value of the first counter meets a second threshold criterion related to the sample size. To ensure that the determined error rate is statistically relevant and not just an outlier, the read voltage adjustment component 113 may continue to collect data until a threshold number of failed bits have been decoded, where the threshold number of failed bits represents a sufficient sample size. Once the threshold number is reached, the read voltage adjustment component 113 may determine that the second threshold criterion is met. In response to the value of the first counter meeting the second threshold criterion, at operation 450, the processing logic determines the error rate based on the ratio of the value of the first counter to the value of the second counter.

[0041] In one embodiment, the operations of method 400 are performed twice in order to determine the first and second boundary error rates described with respect to method 200. For example, the processing logic may determine to perform the operations of method 400 once to determine the error rate corresponding to bits written at the first boundary 314 of a given write-read range 310, and again to determine the error rate corresponding to bits written at the second boundary 316 of the write-read range 310.

[0042] Figure 5 is a flow diagram of an example method of performing a read operation using dynamically adjusted read voltage levels based on boundary error statistics in accordance with some embodiments of the present disclosure. Method 500 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1 the read voltage adjustment component 113. Although shown in a particular order or sequence, the process order may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0043] At operation 510, processing logic receives a read request from the host system 120 or from some other component of the memory subsystem 110. In one embodiment, the read request identifies data stored in a segment of a memory component. The segment can be any physical or logical portion of the memory component, such as a data block.

[0044] At operation 520, the processing logic performs a read operation on the segment of the memory component using a first read voltage level, decodes the data stored at the segment, and determines the write-to-read (W2R) latency time of the segment of the memory component in which the data identified in the request is stored. In one embodiment, the read voltage adjustment component defaults to using the minimum read voltage level available in the memory subsystem (e.g., read level 1) to perform the read operation. If the data read using the first read voltage level can be successfully decoded, then the read voltage adjustment component 113 can read a timestamp stored on the memory component along with the data, which indicates the time the data was written to the segment. If the data read using the minimum read voltage level cannot be successfully decoded, then the processing logic can attempt to read the data again using another read voltage level (e.g., read level 2). The processing logic can repeat this process until the data can be successfully decoded. After the data is successfully decoded, the read voltage adjustment component 113 can determine the difference between the write time indicated by the timestamp and the current time (or the time the read request was received at operation 510), where the difference represents the W2R latency. In some cases, the W2R latency can be determined without reading the corresponding segment. For example, if the write timestamp is stored elsewhere, such as in local memory 119, or if the controller 115 issues write and read operations where there is a known intentional latency time between the write and read operations, then the read voltage adjustment component 113 can determine the W2R latency before reading the segment. In these cases, the read voltage adjustment component 113 can perform the read operation using a different read voltage level (e.g., read level 2 or read level 3) corresponding to the known W2R latency. In one embodiment, regardless of whether the first read voltage level is read level 1, read level 2, or read level 3, the read voltage level is dynamically adjusted based on the correspondence between a first error rate measured at a first boundary of a first range and a second error rate measured at a second boundary of the first range. In one embodiment, the actual value of the read voltage level can be adjusted according to the process described above with respect to Figure 2 the process described.

[0045] At operation 530, the processing logic identifies a first range among multiple write-read latency ranges of the memory component, where the first range represents multiple write-read latency times, and where the write-read latency time of the segment is within the first range. At operation 540, the processing logic determines an optimal read voltage level to be used for performing a read operation on the segment of the memory component having a write-read latency time within the first range, where the optimal read voltage level is dynamically adjusted based on a correspondence between a first error rate measured at a first boundary of the first range and a second error rate measured at a second boundary of the first range. For example, for a W2R latency time within W2R range 310, the read voltage adjustment component may determine a corresponding optimal read voltage level (i.e., read level 1) according to a data structure, a mapping table, a register, etc.

[0046] At operation 550, the processing logic optionally performs any additional read operations on the segment of the memory component using the optimal read voltage level determined at operation 540. In one embodiment, performing the read operation may include applying a signal having the determined read voltage level to one or more memory cells to be read, and determining the state of the memory cells, where this state may be decoded to provide the data stored therein.

[0047] Figure 6 is a flowchart of an example method of adjusting a read voltage level based on cumulative directional RBER statistics of a memory where the error rate varies over time, according to some embodiments of the present disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1 the read voltage adjustment component 113. Although shown in a particular order or sequence, the process order may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0048] At operation 610, the processing logic identifies a first range (e.g., W2R range 310) among multiple write-read latency ranges of the memory component, where the first range represents multiple write-read latency times, and whose associated read voltage level (e.g., read level 1) is used for performing a read operation on the segment of the memory component having a write-read latency time within the first range, as Figure 3AAs shown. The values of read level 1, read level 2, and read level 3 can be set during the manufacture of the memory component, but may become sub-optimal at certain points in time due to the passage of time and other factors associated with the use of the memory component. Adjusting the read voltage levels based on the accumulated direction RBER statistics can bring those read voltage levels back to the point where the BER is optimized (or at least reduced) for the corresponding W2R delay time range.

[0049] Referring again to Figure 6 , at operation 620, the processing logic identifies a first set 714 of a plurality of write-read delay times at the first end (i.e., boundary) of the first range (i.e., W2R range 310), as Figure 7 shown. Figure 7 FIG. 700 is a graph showing the accumulated direction RBER statistics of a memory showing the error rate changing over time according to some embodiments of the present disclosure. In one embodiment, the first set 714 includes the smaller of the sets of the smallest W2R delay times in the W2R range 710. The W2R range 320 may similarly have a first set 724, and the W2R range 330 may have a first set 734. The size of the first set 714 can be a configurable parameter and can include a fixed number of W2R delay times (e.g., the 5 smallest W2R delay times in the W2R range 310) or a certain percentage (e.g., the smallest 1%) of all the W2R delay times in the W2R range 310. In one embodiment, the boundary between the W2R range 310 and the W2R range 320 can be set according to the intersection point of the curves 312 and 322, and the boundary between the W2R range 320 and the W2R range 330 can be set according to the intersection point of the curves 322 and 332. Since the error rate can change over time due to physical changes in the associated memory cells, wear leveling, temperature, etc., these boundaries can also shift over time to optimize the BER. Additionally, changing the system design goals may also affect the positions of these boundaries.

[0050] Referring again to Figure 6, at operation 630, the processing logic determines a first direction error rate of the memory component corresponding to the first set of the plurality of write-read latency times 714 and a second direction error rate of the memory component corresponding to the first set of the plurality of write-read latency times 714. In one embodiment, the direction error rate is related to the number of bits programmed in a first state and misread as a second state. Accordingly, the first error rate may be related to, for example, the number of bits written as logic '0' and misread as logic '1' divided by the total number of logic '0' bits written in the measured segment. Similarly, the second error rate may be related to, for example, the number of bits written as logic '1' and misread as logic '0' divided by the total number of logic '1' bits written in the measured segment. In other embodiments, the first error rate and the second error rate may be reversed. In another embodiment, the processing logic determines a direction failure bit count instead of the corresponding direction error rate.

[0051] In one embodiment, the read voltage adjustment component 113 performs a data integrity scan of the memory component to determine the error rate for each segment (e.g., data block). During the scan, the read voltage adjustment component 113 identifies one or more reliability statistics, such as the direction error rate. In one example, during the scan, the read voltage adjustment component 113 writes and reads the original codewords (i.e., a fixed number of bits in a series) from the data block, where the controlled W2R latency is in the first set 714. The read voltage adjustment component 113 may apply the codewords to an error correction code (ECC) decoder to generate decoded codewords and compare the decoded codewords with the original codewords. The read voltage adjustment component 113 may count the number of flipped bits between the decoded codewords and the original codewords to further obtain the direction error rates in both directions. The read voltage adjustment component 113 may repeat this process for additional codewords until the entire block has been scanned. In another embodiment, the read voltage adjustment component 113 may use various counters 118 to determine the error rate, as described in more detail with respect to Figure 8 more detailed description.

[0052] At operation 640, the processing logic determines whether the correspondence between the first direction error rate and the second direction error rate satisfies a first threshold criterion. In one embodiment, the read voltage adjustment component 113 determines the ratio of the first direction error rate to the second direction error rate and compares the ratio to a target ratio. In one embodiment, the target ratio may be one, such that the first direction error rate is as close as possible to the second direction error rate. Accordingly, the read voltage adjustment component 113 may compare the first direction error rate to the second direction error rate and determine whether the difference between the first direction error rate and the second direction error rate is no more than a threshold amount. If the ratio is close enough to one (i.e., if the difference between the first direction error rate and the second direction error rate is within the threshold amount), then the read voltage adjustment component 113 may determine that the threshold criterion is satisfied. In other embodiments, the target ratio may be some other value set in view of the desired reliability and performance requirements of the memory subsystem. For example, in some cases, it may be desirable for the first direction error rate to be lower than the second direction error rate, or vice versa. Accordingly, the target ratio may have some value other than one. If the ratio is close enough to the target ratio (i.e., if the difference between the ratio and the target ratio is no more than the threshold amount), then the read voltage adjustment component 113 may determine that the threshold criterion is satisfied.

[0053] In response to the correspondence between the first direction error rate and the second direction error rate satisfying the first threshold criterion, at operation 650, the processing logic maintains the read voltage level associated with the first range at the current level. In response to the correspondence between the first direction error rate and the second direction error rate not satisfying the first threshold criterion, at operation 660, the processing logic modifies the read voltage level associated with the first range. In one embodiment, the read voltage adjustment component 113 may adjust the read voltage level such that the ratio of the first direction error rate to the second direction error rate satisfies the first threshold criterion. This may include, for example, increasing or decreasing the read voltage level by a certain amount, re-measuring the direction error rate, and determining whether the ratio is closer to the target ratio. The read voltage adjustment component 113 may repeat this iterative process until the threshold criterion is satisfied. Once the appropriate modified read voltage level is determined, the read voltage adjustment component 113 may store this read voltage level for future read operations for data having a W2R latency in the corresponding range.

[0054] Figure 8 is a flow chart of an example method for determining the direction error rates of a set of write-read latency times at the boundaries of a write-read latency time range according to some embodiments of the present disclosure. Method 800 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 800 is performed by Figure 1is performed by the read voltage adjustment component 113. Although shown in a particular sequence or order, the process order may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0055] At operation 810, the processing logic monitors read operations being performed on a segment of a memory component having a read-write latency time in a first set of a plurality of read-write latency times. In one implementation, the read voltage adjustment component 113 may receive a request from the host system 120 to perform a read operation, perform any address mapping operations to identify the physical address in the memory that the read operation is directed to, and determine the corresponding W2R latency time for the address. The W2R latency time may represent the difference between a first time when data is written to the physical address and a second time when the read request is received from the host system 120. Depending on the implementation, the W2R latency time may be calculated based on the difference between the current time and a timestamp (indicating the write time), which may be stored with the data at the physical address on the memory component or stored in some other data storage device separate from the memory component (e.g., local memory 119), or the W2R latency time may be calculated in other ways by the read voltage adjustment component 113. In another implementation, the actual read operation is not received from the host system 120, but rather the read voltage adjustment component 113 may intentionally issue a request to read data known to have an appropriate W2R latency time. Although the operations of method 800 are described with respect to errors occurring in a first direction for a first set (e.g., 714) of W2R latency times in a first range (e.g., W2R range 310), the same or similar operations may be performed for different sets (e.g., 724 or 734) or different ranges (e.g., W2R range 320 or 330).

[0056] At operation 820, the processing logic increments a first counter in counter 118 in response to each failed bit detected in the first direction during a read operation. For a read of the identified group 714, the read voltage adjustment component 113 reads the original codeword, applies the codeword to an error correction code (ECC) decoder to generate a decoded codeword, and compares the decoded codeword with the original codeword. The read voltage adjustment component 113 may increment the first counter in response to each bit that flips in a particular direction in the decoded codeword. For example, the read voltage adjustment component 113 may increment the first counter for each bit written as a logic '0' and misread as a logic '1'. In another implementation, the read voltage adjustment component 113 may actually increment the first counter for each bit written as a logic '1' and misread as a logic '0'. At operation 830, the processing logic increments a second counter in counter 118 in response to each bit of a certain state (i.e., the direction state determined at operation 820) in the decoded codeword. For example, in one implementation where the first counter corresponds to a data direction error where a logic '0' is written and misread as a logic '1', at operation 830, the second counter will accumulate in response to each bit having a logic '0' state in the decoded codeword.

[0057] At operation 840, the processing logic determines whether the value of the first counter meets a second threshold criterion related to the sample size. To ensure that the determined error rate is statistically relevant and not just an outlier, the read voltage adjustment component 113 may continue to collect data until a threshold number of direction failed bits have been decoded, where the threshold number of direction failed bit counts represents a sufficient sample size. Once the threshold number is reached, the read voltage adjustment component 113 may determine that the second threshold criterion is met. In response to the value of the first counter meeting the second threshold criterion, at operation 850, the processing logic determines the direction error rate based on the ratio of the value of the first counter to the value of the second counter.

[0058] In one embodiment, the operations of method 800 are performed twice to determine the first and second direction error rates described with respect to method 600. For example, the processing logic may determine to perform the operations of method 800 once to determine the direction error rate corresponding to bits written as logic '0' and misread as logic '1', and perform again to determine the direction error rate corresponding to bits written as logic '1' and misread as logic '0'. In one embodiment, in response to there being a sufficient sample size related to the first and second direction error rates, as determined at operation 840, the ratio of the first and second direction error rates is determined at 640 of operation method 600. Since the number of decoded codewords for direction failure bit accumulation increases, the balance between the number of logic '0' and logic '1' bits improves. Accordingly, the first threshold criterion for operation 640 of method 600 may be determined based on the number of failure bits in each direction as described above with respect to operation 820 of method 800.

[0059] Figure 9 is a flowchart of an example method of performing a read operation using dynamically adjusted read voltage levels based on direction error statistics in accordance with some embodiments of the present disclosure. Method 900 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 900 is performed by Figure 1 the read voltage adjustment component 113. Although shown in a particular order or sequence, the process order may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 910, the processing logic receives a read request from the host system 120 or from some other component of the memory subsystem 110. In one embodiment, the read request identifies data stored in a segment of the memory component. The segment may be any physical or logical portion of the memory component, such as a data block.

[0061] At operation 920, the processing logic performs a read operation on a segment of the memory component using a first read voltage level (e.g., read level 1), decodes the data stored at the segment, and determines the write-to-read (W2R) latency time of the segment of the memory component that stores the data identified in the read request. In one embodiment, the read voltage adjustment component defaults to using the minimum read voltage level available in the memory subsystem (e.g., read level 1) to perform the read operation. If the data read using the first read voltage level can be successfully decoded, then the read voltage adjustment component 113 can read the timestamp stored on the memory component along with the data, which indicates the time the data was written to the segment. If the data read using the minimum read voltage level cannot be successfully decoded, then the processing logic can attempt to read the data again using another read voltage level (e.g., read level 2). The processing logic can repeat this process until the data can be successfully decoded. After the data is successfully decoded, the read voltage adjustment component 113 can determine the difference between the write time indicated by the timestamp and the current time (or the time the read request was received at operation 910), where the difference represents the W2R latency. In some cases, the W2R latency can be determined without reading the corresponding segment. For example, if the write timestamp is stored elsewhere, such as in local memory 119, or if the controller 115 issues write and read operations where there is a known intentional latency time between the write and read operations, then the read voltage adjustment component 113 can determine the W2R latency before reading the segment. In these cases, the read voltage adjustment component 113 can perform the read operation using a different read voltage level (e.g., read level 2 or read level 3) corresponding to the known W2R latency. In one embodiment, regardless of whether the first read voltage level is read level 1, read level 2, or read level 3, the read voltage level is dynamically adjusted based on the correspondence between the first direction error rate measured at the first boundary of the first range and the second direction error rate measured at the first boundary of the first range. In one embodiment, the actual value of the read voltage level can be adjusted according to the process described above with respect to Figure 6 the process described.

[0062] At operation 930, processing logic identifies a first range among a plurality of write-read latency ranges of a memory component, where the first range represents a plurality of write-read latency times and where the write-read latency time of a segment is within the first range. At operation 940, the processing logic determines an optimal read voltage level to be used to perform a read operation on a segment of the memory component having a write-read latency time within the first range, where the optimal read voltage level is dynamically adjusted based on a correspondence between a first direction error rate measured at a first boundary of the first range and a second direction error rate measured at the first boundary of the first range. For example, for a W2R latency time in W2R range 320, the read voltage adjustment component may determine a corresponding optimal read voltage level (i.e., read level 2) according to a data structure, a mapping table, a register, etc.

[0063] At operation 950, the processing logic optionally performs any additional read operations on the segment of the memory component using the optimal read voltage level determined at operation 940. In one embodiment, performing the read operation may include applying a signal having the determined read voltage level to one or more memory cells to be read and determining the state of the memory cells, where the state may be decoded to provide the data stored therein.

[0064] Figure 10 An example machine of a computer system 1000 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 1000 may correspond to a host system (e.g., Figure 1 host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or may be used to perform the operations of a controller (e.g., executing an operating system to perform the operations corresponding to Figure 1 read voltage adjustment component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment as a peer (or distributed) machine in a peer-to-peer network environment or as a server or a client machine in a cloud computing infrastructure or environment.

[0065] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0066] Example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030.

[0067] The processing device 1002 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1002 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. The computer system 1000 can further include a network interface device 1008 to communicate via a network 1020.

[0068] The data storage system 1018 can include a machine-readable storage medium 1024 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 1026 or software embodying any one or more of the methods or functions described herein. The instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution by the computer system 1000, which main memory 1004 and processing device 1002 also constitute machine-readable storage media. The machine-readable storage medium 1024, the data storage system 1018, and / or the main memory 1004 may correspond to Figure 1 the memory subsystem 110.

[0069] In one embodiment, the instructions 1026 include implementing corresponding to Figure 1instructions for the functionality of the read voltage adjustment component 113. Although the machine-readable storage medium 1024 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be understood to include (but not be limited to) solid-state memories, optical media, and magnetic media.

[0070] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has, at times, proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0071] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0072] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0073] The algorithms and displays presented herein are not inherently related to any particular computer or other device. A variety of general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods. The structure of many of these systems will be presented as will be set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that a variety of programming languages may be used to implement the teachings of the present disclosure described herein.

[0074] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that may be used to program a computer system (or other electronic device) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0075] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory system, comprising: A memory component; And A processing device operatively coupled to the memory component and performing the following operations: Identifying a first range among a plurality of write-read latency ranges of the memory component, wherein the first range represents a plurality of write-read latency times, and an associated read voltage level is used to perform a read operation on a segment of the memory component having a write-read latency time within the first range; Identifying a first set of the plurality of write-read latency times at a first end of the first range and a second set of the plurality of write-read latency times at a second end of the first range; Determining a first error rate of the memory component corresponding to the first set of the plurality of write-read latency times and a second error rate of the memory component corresponding to the second set of the plurality of write-read latency times; Determining whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion; And In response to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifying the read voltage level associated with the first range.

2. The memory system according to claim 1, wherein to determine the first error rate, the processing device performs the following operations: Monitoring read operations performed on a segment of the memory component having a write-read latency time within the first set of the plurality of write-read latency times; Incrementing a first counter in response to each failed bit detected in the read operation; Incrementing a second counter in response to each bit in each codeword decoded in the read operation; Determining that a value of the first counter satisfies a second threshold criterion related to a sample size; and Determining a ratio of the value of the first counter to the value of the second counter.

3. The memory system according to claim 1, wherein to determine whether the correspondence between the first error rate and the second error rate satisfies the first threshold criterion, the processing device determines whether the first error rate and the second error rate differ by no more than a threshold amount.

4. The memory system according to claim 1, wherein to determine whether the correspondence between the first error rate and the second error rate satisfies the first threshold criterion, the processing device determines whether a ratio of the first error rate to the second error rate and a target ratio differ by no more than a threshold amount.

5. The memory system according to claim 4, wherein the target ratio is based on required reliability and performance requirements of the system.

6. The memory system according to claim 1, wherein to modify the read voltage level associated with the first range, the processing device adjusts the read voltage level such that the correspondence between the first error rate and the second error rate satisfies the first threshold criterion.

7. The memory system according to claim 1, wherein the processing device further performs the following operations: In response to the correspondence between the first error rate and the second error rate satisfying the first threshold criterion, maintain the read voltage level associated with the first range at the current level.

8. A method of operating a memory subsystem, comprising: Receiving a read request from a host system, the read request identifying data stored in a segment of a memory component; Performing a read operation on the segment of the memory component using a first read voltage level; Based on the read operation, determining a write-read latency time of the segment of the memory component, wherein the data identified in the request is stored in the segment of the memory component; Identifying a first range among a plurality of write-read latency ranges of the memory component, wherein the first range represents a plurality of write-read latency times, and wherein the write-read latency time of the segment is within the first range; And Determining a second read voltage level for performing a read operation on the segment of the memory component, wherein the second read voltage level is dynamically adjusted based on a correspondence between a first error rate measured at a first boundary of the first range and a second error rate measured at a second boundary of the first range.

9. The method of claim 8, wherein the write-read latency time represents a difference between a first time when the data is written to the segment and a second time when the read request identifying the data is received from the host system.

10. The method of claim 8, wherein determining the second read voltage level comprises: Identifying a first set of the plurality of write-read latency times at the first boundary of the first range and a second set of the plurality of write-read latency times at the second boundary of the first range; Determining a first error rate of the memory component corresponding to the first set of the plurality of write-read latency times and a second error rate of the memory component corresponding to the second set of the plurality of write-read latency times; And Determining the correspondence between the first error rate and the second error rate.

11. The method of claim 10, further comprising: In response to the correspondence between the first error rate and the second error rate not satisfying a first threshold criterion, dynamically adjusting the second read voltage level.

12. The method of claim 11, wherein the correspondence between the first error rate and the second error rate satisfies the first threshold criterion when the difference between the first error rate and the second error rate does not exceed a threshold amount.

13. The method of claim 11, wherein the correspondence between the first error rate and the second error rate satisfies the first threshold criterion when the ratio of the first error rate to the second error rate and a target ratio differ by no more than a threshold amount, and wherein the target ratio is based on required reliability and performance requirements of the memory subsystem.

14. A non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform the following operations: Identify a first range among multiple write-read latency ranges of a memory component in a memory subsystem, where the first range represents multiple write-read latency times, and an associated read voltage level is used to perform a read operation on a segment of the memory component having a write-read latency time within the first range; Identify a first set of the multiple write-read latency times at a first end of the first range and a second set of the multiple write-read latency times at a second end of the first range; Determine a first error rate of the memory component corresponding to the first set of the multiple write-read latency times and a second error rate of the memory component corresponding to the second set of the multiple write-read latency times; Determine whether a correspondence relationship between the first error rate and the second error rate satisfies a first threshold criterion; And In response to the correspondence relationship between the first error rate and the second error rate not satisfying the first threshold criterion, modify the read voltage level associated with the first range.

15. The non-transitory computer-readable storage medium according to claim 14, wherein to determine the first error rate, the instructions further cause the processing device to perform the following operations: Monitor read operations performed on a segment of the memory component having a write-read latency time within the first set of the multiple write-read latency times; Increment a first counter in response to each failed bit detected in the read operation; Increment a second counter in response to each bit in each codeword decoded in the read operation; Determine that a value of the first counter satisfies a second threshold criterion related to a sample size; and Determine a ratio of the value of the first counter to the value of the second counter.

16. The non-transitory computer-readable storage medium according to claim 14, wherein to determine whether the correspondence relationship between the first error rate and the second error rate satisfies the first threshold criterion, the instructions further cause the processing device to determine whether the first error rate and the second error rate differ by no more than a threshold amount.

17. The non-transitory computer-readable storage medium according to claim 14, wherein to determine whether the correspondence relationship between the first error rate and the second error rate satisfies the first threshold criterion, the instructions further cause the processing device to determine whether a ratio of the first error rate to the second error rate and a target ratio differ by no more than a threshold amount.

18. The non-transitory computer-readable storage medium according to claim 17, wherein the target ratio is based on required reliability and performance requirements of the memory subsystem.

19. The non-transitory computer-readable storage medium according to claim 14, wherein to modify the read voltage level associated with the first range, the instructions further cause the processing device to adjust the read voltage level such that the correspondence relationship between the first error rate and the second error rate satisfies the first threshold criterion.

20. The non-transitory computer-readable storage medium according to claim 14, wherein the instructions further cause the processing device to perform the following operations: In response to the correspondence between the first error rate and the second error rate satisfying the first threshold criterion, maintaining the read voltage level associated with the first range at the current level.

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