Serial shift two's complement multiplier-accumulator

Abstract

The present invention provides a serial shift complement multiplier and adder, which comprises: a shift register, a first two-choose-one data selector, an inverter, a second two-choose-one data selector, a D flip-flop and a one-bit full adder. The present invention implements a power-of-two multiplication operation through a shift register, implements original code conversion to a complement code through an inverter and the first two-choose-one data selector, obtains sign bit data and output carry data through the second two-choose-one data selector and the D flip-flop, implements addition operation through a full adder, and can implement positive and negative power-of-two multiplication and accumulation operations, thereby reducing hardware resource overhead and improving operation efficiency.

Description

Technical Field

[0001] The invention relates to the technical field of digital circuit design, and in particular to a serial shift complement multiplier-adder. Background Art

[0002] In recent years, the design of special digital integrated circuits to realize digital signal processing has become a hot research topic. In digital signal processing, multiplication and addition operations account for a large proportion.

[0003] For some special multiplication and addition operations, such as a multiplication and addition operation where the multiplier is a power of two, directly calling the multiplier and adder will often result in a waste of resources. In addition, the multiplication results may be positive or negative, and additional processing is required to accumulate these positive and negative multiplication results. Summary of the invention

[0004] The invention provides a serial shift complement multiplier-adder, which is used to solve the problems in the prior art of realizing power-of-two multiplication and addition operations, such as huge consumption of hardware resources, slow operation speed and the existence of positive and negative numbers in the operation process.

[0005] The present invention provides a serial shift complement multiplier adder, comprising: a shift register, a first two-to-one data selector, an inverter, a second two-to-one data selector, a D flip-flop and a one-bit full adder;

[0006] The output end of the shift register is divided into two paths, one of which is connected to the input end of the inverter, and the other is connected to the first input end of the first two-to-one data selector; the shift register is used to perform shift processing on the input data to be multiplied;

[0007] The output end of the inverter is connected to the second input end of the first two-to-one data selector; the inverter is used to convert the original code of the shifted data to be multiplied into an inverse code;

[0008] The output end of the first two-to-one data selector is connected to the first input end of the one-bit full adder; the first two-to-one data selector is used to select one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied and output them;

[0009] The input end of the second two-to-one data selector is connected to the output carry end of the one-bit full adder; the output end of the second two-to-one data selector is connected to the input end of the D flip-flop; the second two-to-one data selector is used to select one of the output carry data of the one-bit full adder and the sign bit of the data to be multiplied and output them;

[0010] The output end of the D flip-flop is connected to the second input end of the one-bit full adder; the D flip-flop is used to delay the output carry data or the sign bit of the data to be multiplied by one cycle and then input it to the input carry end of the one-bit full adder;

[0011] The one-bit full adder is used to perform addition processing on the input carry data, the shifted data to be multiplied and the data to be added, and output the operation result data.

[0012] Optionally, the shift register comprises: a third two-to-one data selector, a second D flip-flop and a data selector;

[0013] The output end of the third two-to-one data selector is connected to the input end of the second D flip-flop; the third two-to-one data selector is used for synchronous reset;

[0014] The output end of the second D flip-flop is connected to the input end of the data selector; the second D flip-flop is used to delay the input data to be multiplied;

[0015] The data selector is used to select one of the output data of the second D flip-flop and output it.

[0016] Optionally, the data to be multiplied, the sign bit of the data to be multiplied, the data to be added and the calculation result data are all input or output in the form of a serial pulse waveform.

[0017] Optionally, the first two-to-one data selector is used to select and output one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied, including:

[0018] When the enable terminal signal of the first two-to-one data selector is logic 1, the output terminal of the first two-to-one data selector outputs the inverse code of the shifted data to be multiplied;

[0019] When the enable terminal signal of the first two-to-one data selector is logic 0, the output terminal of the first two-to-one data selector outputs the original code of the shifted data to be multiplied.

[0020] Optionally, the second two-to-one data selector is used to select one of the output carry data of the one-bit full adder and the sign bit of the data to be multiplied and output them, including:

[0021] When the enable terminal signal of the second two-to-one data selector is logic 1, the output terminal of the second two-to-one data selector outputs the output carry data of the one-bit full adder;

[0022] When the enable terminal signal of the second two-to-one data selector is logic 0, the output terminal of the second two-to-one data selector outputs the sign bit of the data to be multiplied.

[0023] Optionally, when the enable signal of the shift register is logic 1, the data to be multiplied is valid data.

[0024] Optionally, when the enable terminal signal of the second two-to-one data selector is logic 1, the data to be added and the operation result data are valid data.

[0025] Optionally, the data to be multiplied are input into the input end of the shift register in order from low bits to high bits.

[0026] Optionally, the D flip-flop is a pulse edge D flip-flop.

[0027] The serial shift complement multiplier and adder provided by the present invention realizes multiplication operation of powers of two through a shift register, realizes conversion of original code into complement code through an inverter and a first two-to-one data selector, obtains sign bit data and output carry data through a second two-to-one data selector and a D flip-flop, realizes addition operation through a full adder, and can realize positive and negative power of two multiplication and accumulation operation, thereby reducing hardware resource overhead and improving operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 1 is a schematic diagram of the internal structure of a serial shift complement multiplier-adder provided by an embodiment of the present invention;

[0030] Figure 2 1 is a schematic diagram of the external structure of a serial shift complement multiplier-adder provided by an embodiment of the present invention;

[0031] Figure 3 1 is a schematic diagram of the internal structure of a shift register of a serial shift complement multiplier-adder provided by an embodiment of the present invention;

[0032] Figure 4 It is a timing diagram of a serial shift complement multiplier and adder provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Figure 1 is a schematic diagram of the internal structure of a serial shift complement multiplier and adder provided by an embodiment of the present invention, such as Figure 1 As shown, the present invention provides a serial shift complement multiplier adder, comprising: a shift register, a first two-to-one data selector, an inverter, a second two-to-one data selector, a first D flip-flop and a one-bit full adder;

[0035] The output end of the shift register is divided into two paths, one of which is connected to the input end of the inverter, and the other is connected to the first input end of the first two-to-one data selector; the shift register is used to perform shift processing on the input data to be multiplied;

[0036] The output end of the inverter is connected to the second input end of the first two-to-one data selector; the inverter is used to convert the original code of the shifted data to be multiplied into an inverse code;

[0037] The output end of the first two-choose-one data selector is connected to the first input end of the one-bit full adder; the first two-choose-one data selector is used to select one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied and output them;

[0038] The input end of the second two-to-one data selector is connected to the output carry end of the one-bit full adder; the output end of the second two-to-one data selector is connected to the input end of the first D flip-flop; the second two-to-one data selector is used to select one of the output carry data of the one-bit full adder and the sign bit of the data to be multiplied and output them;

[0039] The output end of the first D flip-flop is connected to the second input end of the one-bit full adder; the first D flip-flop is used to delay the output carry data or the sign bit of the data to be multiplied by one cycle and then input it to the input carry end of the one-bit full adder;

[0040] The one-bit full adder is used to perform addition processing on the input carry data, the shifted data to be multiplied and the data to be added, and output the operation result data.

[0041] Specifically, Figure 2 is a schematic diagram of the external structure of the serial shift complement multiplier and adder provided by an embodiment of the present invention, such as Figure 2As shown, the external input ports of the multiplier-adder include the shift input (ShiftIn) port, the shift input enable (ShiftlnEn) port, the shift input control (ShiftInCtrl[2:0]) port, the sign bit (SignBit) port, the sign control bit (SignBitCtrl) port, the addend (Addend) port and the clock (Clk) port, and the output ports include the sum (Sum) port.

[0042] The ShiftIn port of the multiplier-adder is connected to the ShiftIn input terminal of the internal shift register, and the ShiftIn port of the multiplier-adder is used to input data to be multiplied.

[0043] Optionally, the data to be multiplied are input into the input end of the shift register in order from low to high bits.

[0044] Specifically, the data to be multiplied are input into the ShiftIn input terminal of the shift register, that is, the ShiftIn port of the multiplier-accumulator, in the order of low bits first and high bits last. The highest bit of the data to be multiplied is the sign bit, and logic 0 indicates that the sign bit is positive, and logic 1 indicates that the sign is negative.

[0045] For example, the binary representation of the data to be multiplied is 01101, and the data to be multiplied is input into the shift register in the form of serial pulses 1, 0, 1, 1, 0 in sequence.

[0046] By inputting the data to be multiplied in order from low to high, a one-bit full adder can perform addition from low to high.

[0047] Optionally, the data to be multiplied, the sign bit of the data to be multiplied, the data to be added and the result data are all input or output in the form of serial pulse waveforms.

[0048] Specifically, the calculation data in the embodiments of the present application are all input or output in the form of serial pulse waveforms, and the data to be multiplied, the sign bits of the data to be multiplied, the data to be added, and the calculation result data are all input or output in the form of serial high and low levels, the high level is logic 1, and the low level is logic 0.

[0049] The input or output is performed in the form of a serial pulse waveform, which further facilitates the one-bit full adder to perform addition from low bits to high bits.

[0050] The ShiftInCtrl[2:0] port of the multiplier-adder is connected to the ShiftInCtrl[2:0] port of the internal shift register. The input data of the ShiftInCtrl[2:0] port of the multiplier-adder indicates the number of bits to be shifted for the data to be multiplied. Since the shift register is a timing-controlled delay device, shifting the data to be multiplied is to multiply the data to be multiplied by a positive power of two. ShiftInCtrl[2:0] indicates a three-digit value, and each value is 0 or 1, that is, the data to be multiplied can be shifted left by up to 7 bits.

[0051] The ShiftInEn port of the multiplier-accumulator is connected to the ShiftInEn port of the internal shift register.

[0052] Optionally, when the enable signal of the shift register is logic 1, the data to be multiplied is valid data.

[0053] Specifically, when the enable signal of the ShiftlnEn port is at a high level, that is, logic 1, the shift register starts to work, which also indicates that the data to be multiplied input to the shift register is valid data.

[0054] For example, when the enable signal of the ShiftlnEn port is logic 1, the serial pulse of the data to be multiplied input into the shift register is 1, and this serial pulse 1 is valid data.

[0055] For example, when the enable signal of the ShiftlnEn port is logic 0, the serial pulse of the data to be multiplied input to the shift register is 1, then this serial pulse 1 is invalid data, and the result of the operation involving this serial pulse 1 is an invalid result.

[0056] The validity of the data to be multiplied is controlled by using an enable signal, thereby further improving the reliability of the output result of the multiplier-accumulator.

[0057] The clock Clk port of the multiplier-adder is divided into two paths, one connected to the Clk port of the shift register, and the other connected to the Clk port of the first D flip-flop. The embodiment of the present invention uses the rising edge of the Clk signal as a valid signal to control the data to enter the device in a rhythmic manner.

[0058] Optionally, the shift register includes: a third two-to-one data selector, a second D flip-flop and a data selector;

[0059] The output end of the third two-to-one data selector is connected to the input end of the second D flip-flop; the third two-to-one data selector is used for synchronous reset;

[0060] The output end of the second D flip-flop is connected to the input end of the data selector; the second D flip-flop is used to delay the input data to be multiplied;

[0061] The data selector is used to select one of the output data of the second D flip-flop and output it.

[0062] Specifically, Figure 3 FIG. 1 is a schematic diagram of the internal structure of a shift register of a serial shift complement multiplier and adder provided by an embodiment of the present invention. Figure 3 As shown, the ShiftlnEn port of the shift register is connected to the enable end of the third two-to-one data selector MUX3, the Shiftln port of the shift register is connected to the first input end of the third two-to-one data selector, and the second input end of the third two-to-one data selector is grounded.

[0063] When the enable signal of the ShiftlnEn port of the shift register is at a high level, that is, the enable terminal signal of the third two-to-one data selector is at a high level, the third two-to-one data selector outputs the data of the first input terminal, that is, the data to be multiplied.

[0064] When the enable signal of the ShiftlnEn port of the shift register is at a low level, that is, the enable terminal signal of the third two-to-one data selector is at a low level, the third two-to-one data selector outputs the data of the second input terminal, that is, logic 0.

[0065] When the second D flip-flop connected to the third two-to-one data selector does not start working, it stores 0 in advance in the second D flip-flop to achieve synchronous resetting of the second D flip-flop.

[0066] The number of D flip-flops represented by the second D flip-flop is greater than 1. The specific number of D flip-flops depends on the shift requirement, such as Figure 4 As shown, the second D flip-flop is 8 D flip-flops connected in series, and the 8 D flip-flops connected in series can achieve a maximum left shift of 7 bits.

[0067] The data selector corresponds to the second D flip-flop, the eight-to-one data selector MUX4 corresponds to the eight D flip-flops, the data selector is an eight-to-one data selector, the ShiftInCtrl[2:0] port of the shift register is connected to the enable end of the eight-to-one data selection, and controls the eight-to-one data selector to select one from the eight data input by the eight D flip-flops for output.

[0068] Assume execution 2 3 ×100, the binary representation of 100 is 01100100, the highest bit 0 represents the sign bit, 100 and 2 3Multiplication means shifting 00100110 to the left by 3 bits and then outputting it. The eight-to-one data selector selects the input value of the fourth D flip-flop for output, that is, the data to be multiplied is delayed for three cycles before being output. The ShiftOut output terminal of the eight-to-one data selector outputs 01100100000, and the decimal value of 01100100000 is 800.

[0069] The shift register is reset through a two-to-one data selector, delayed output is achieved through a plurality of D flip-flops, and delayed data is selected for output through a data selector, thereby reducing hardware resource overhead and improving operation efficiency.

[0070] The output terminal ShiftOut of the shift register is connected to the input terminal A of the one-bit full adder. After the shift register performs shift processing on the input data to be multiplied, the shifted data to be multiplied is input into the one-bit full adder for addition operation.

[0071] The Addend port of the multiplier-adder is connected to the B input terminal of the internal one-bit full adder. The Addend port of the multiplier-adder is used to input the data to be added. The data to be added is the complement pulse of the previous accumulated result, that is, the data to be added is input into the B input terminal of the one-bit full adder in the form of a serial complement pulse waveform to participate in the addition operation.

[0072] The SignBitCtrl port of the multiplier-adder is connected to the enable terminal of the second two-to-one data selector MUX2, and is used to control the output of the second two-to-one data selector.

[0073] Optionally, when the enable terminal signal of the second two-to-one data selector is logic 1, the data to be added and the operation result data are valid data.

[0074] Specifically, when the SignBitCtrl port of the second two-to-one data selector is logic 1, the one-bit full adder starts to work. At this time, the data to be added input to the one-bit full adder and the operation result data output from the one-bit full adder are valid data.

[0075] When the SignBitCtrl port of the second two-choose-one data selector is logic 0, the one-bit full adder has not started working. At this time, the data to be added input to the one-bit full adder is invalid data. Since the one-bit full adder has not started working, the one-bit full adder has no output data, that is, no operation result data.

[0076] The validity of the data to be added and the operation result data is controlled by the enable terminal signal of the second two-to-one data selector, thereby further improving the reliability of the output result of the multiplier-adder.

[0077] The SignBit port of the multiplier-adder is connected to the first input terminal of the second two-to-one data selector, and the second input terminal of the second two-to-one data selector is connected to the carry output terminal Co of the one-bit full adder.

[0078] The input signal of the SignBitCtrl port of the multiplier-adder controls whether the second two-to-one data selector outputs the sign bit of the data to be multiplied or outputs the output carry data of the one-bit full adder.

[0079] Optionally, the second two-to-one data selector is used to select and output one of the output carry data of the one-bit full adder and the sign bit of the data to be multiplied, including:

[0080] When the enable terminal signal of the second two-to-one data selector is logic 1, the output terminal of the second two-to-one data selector outputs a one-bit full adder output carry data;

[0081] When the enable terminal signal of the second two-to-one data selector is logic 0, the output terminal of the second two-to-one data selector outputs the sign bit of the data to be multiplied.

[0082] Specifically, for example, when the enable terminal signal of the second two-to-one data selector is logic 1, the output terminal of the second two-to-one data selector outputs the output carry data of the one-bit full adder in the previous cycle.

[0083] For example, when the enable terminal signal of the second two-to-one data selector is logic 0, the output terminal of the second two-to-one data selector outputs the sign bit of the data to be multiplied.

[0084] The high level of the input signal of the SignBitCtrl port, that is, logic 1, is a valid signal. The second two-to-one data selector outputs the carry data of the one-bit full adder output in the previous cycle to the input carry of the one-bit full adder, so that the one-bit full adder can add the carry of the previous bit, further improving the reliability of the output result of the multiplier.

[0085] The output port of the second two-to-one data selector is connected to the D input terminal of the D flip-flop, and the Q output terminal of the D flip-flop is connected to the carry input terminal Ci of the one-bit full adder.

[0086] The SignBit port of the multiplier-adder inputs the sign bit of the data to be multiplied. When the sign bit is positive, the input signal of the SignBit port is logic 0, and when the sign bit is negative, the input signal of the SignBit port is logic 1. The SignBit port is connected to the first port of the second two-to-one data selector.

[0087] Optionally, the D flip-flop is a pulse edge D flip-flop.

[0088] Specifically, the pulse edge D flip-flop is triggered by the clock edge pulse, which can be either the upper edge triggered or the lower edge triggered. In the embodiment of the present application, the rising edge of the Clk signal is used as the valid signal, so the D flip-flop also uses the pulse edge D flip-flop triggered by the upper edge.

[0089] The pulse edge D flip-flop is used to delay the output carry data or the sign bit of the data to be multiplied by one cycle and then input it into the input carry terminal of a one-bit full adder.

[0090] Assume that the specific expression for executing a power-of-two multiplication and addition operation is as follows:

[0091] y=x·2 n +d

[0092] Among them, y is the output result of the multiplication and addition operation, x is a fixed-point positive integer, 2 n is the nth power multiplier of 2 that is multiplied by x, where n is a positive integer with a range, and x is equal to 2 n After multiplication, add the integer d.

[0093] Execute x 2 n +d, {0,x} is input to the ShiftIn port of the multiplier-adder. The 0 in {0,x} indicates that the highest bit sign is positive. n is converted into a binary number and input to the ShiftInCtrl[2:0] port of the multiplier-adder. Since x is a fixed-point positive integer, the input signal of the SignBit port is 0, d is input to the Addend port of the multiplier-adder, and the multiplication-addition operation result y is output from the Sum port of the multiplier-adder.

[0094] When the enable signal of the SignBitCtrl port is 0, the second 2-to-1 data selector outputs the SignBit port input signal, i.e. 0, to the D flip-flop. The D flip-flop delays the SignBit port input signal by one cycle and inputs it into the input carry terminal of the one-bit full adder. At this time, the one-bit full adder has not started working yet, and the D flip-flop has been storing the SignBit port input signal.

[0095] When the enable signal of the SignBitCtrl port is 1, in the first clock cycle, the D flip-flop inputs the input signal of the SignBit port that has been stored to the input carry terminal of the one-bit full adder, that is, the first input value of the Ci port is 0, which is equivalent to the addition of the first clock cycle only counting the first input value A1 of the A port and the first input value B1 of the B port, and the output port S outputs the sum S1 of A1 and B1, and the carry output port C o The port outputs the first carry value C of A1 and B1 o1 In the second clock cycle, the second selector outputs C o1, the D flip-flop outputs the carry value C of the previous cycle o1 Input the Ci port of the one-bit full adder. The second clock cycle is to calculate the input value C of the Ci port. o1 , the addition of the value A2 input at port A and the value B2 input at port B. After that, the D flip-flop outputs the carry output value of the one-bit full adder in the previous cycle in each clock cycle, that is, the carry output value of the one-bit full adder Ci port has been input in the previous clock cycle.

[0096] Multiplication and addition operations do not always involve positive integers; negative integers also exist.

[0097] An inverter and a first-to-two-choice data selector MUX1 are added between the shift register and the one-bit full adder. The inverter is used to convert the shifted data to be multiplied from the original code to the inverse code, and then the first-to-two-choice data selector is used to select one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied and output them.

[0098] The enable signal terminal of the first two-to-one data selector is connected to the SignBit port of the external multiplier-adder.

[0099] Optionally, the first two-to-one data selector is used to select one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied and output them, including:

[0100] When the enable terminal signal of the first two-to-one data selector is logic 1, the output terminal of the first two-to-one data selector outputs the inverse code of the shifted data to be multiplied;

[0101] When the enable terminal signal of the first two-to-one data selector is logic 0, the output terminal of the first two-to-one data selector outputs the original code of the data to be multiplied after the shift.

[0102] Specifically, for example, when the binary value of the data to be multiplied is a positive integer of 01101, the highest bit is the sign bit 0, the input signal of the SignBit port is 0, and after shifting one bit to the left, the shifted data to be multiplied is 011010, that is, the enable signal of the first two-to-one data selector is logic 0, and the output end of the first two-to-one data selector outputs the original code of the shifted data to be multiplied, that is, 11010.

[0103] For example, when the binary data to be multiplied is a negative integer of 11101, the highest bit is the sign bit 1, the input signal of the SignBit port is 1, and after shifting one bit to the left, the shifted data to be multiplied is 111010, that is, the enable signal of the first two-to-one data selector is logic 1, and the output end of the first two-to-one data selector outputs the inverse of the shifted data to be multiplied, that is, 00101.

[0104] By controlling the first two-to-one data selector to output the original code of the data to be multiplied or the inverse code of the shifted data to be multiplied, it is beneficial to allow negative numbers to participate in the operation in the form of complement code during the operation process.

[0105] The ShiftOut output end of the shift register is divided into two paths, one is connected to the input end of the inverter, and the other is connected to the first input end of the first two-to-one data selector. The output end of the inverter is connected to the second input end of the first two-to-one data selector, and the output end of the first two-to-one data selector is connected to the first input end A of the one-bit full adder.

[0106] Assume that the specific expression for executing a power-of-two multiplication and addition operation is as follows:

[0107] y′=-x·2 n +d

[0108] Among them, y′ is the output result of the multiplication and addition operation, x is a fixed-point positive integer, 2 n is the nth power multiplier of 2 that is multiplied by -x, where n is a positive integer with a range, and -x and 2 n After multiplication, add the integer d.

[0109] Execute -x 2 n When performing the +d operation, {0,x} is input into the ShiftIn port of the multiplier-adder. The 0 in {0,x} indicates that the highest sign bit is complemented to positive through transformation. n is converted into a binary number and input into the ShiftInCtrl[2:0] port of the multiplier-adder. Since -x is a negative integer, the SignBit sign bit is 1. d is input into the Addend port of the multiplier-adder, and the multiplication-addition operation result y′ is output from the Sum port of the multiplier-adder.

[0110] When the enable signal of the SignBitCtrl port is 0, the second 2-to-1 data selector outputs the input signal of the SignBit port, which is 1, to the D flip-flop. The D flip-flop delays the input signal of the SignBit port by one cycle and inputs it into the input carry terminal of the one-bit full adder. At this time, the one-bit full adder has not started working yet, and the D flip-flop has been storing the input signal of the SignBit port.

[0111] When the enable signal of the SignBitCtrl port is 1, the D flip-flop in the first clock cycle inputs the input signal of the SignBit port that has been stored to the input carry terminal of the one-bit full adder, that is, the first input value of the Ci port is 1. The input signal of the SignBit port is 1, and the first two-to-one register outputs the inverse code of x. In the first clock cycle, the first value of the inverse code of x, the first complement pulse of the data d to be added, and the carry input value 1 of the Ci port are added. Among them, the first value of the inverse code of x is added to the carry input value 1 of the Ci port, which is equivalent to adding 1 to the inverse code to realize the conversion of the original code of the negative number into the complement code.

[0112] In the second clock cycle, the second two-to-one data selector outputs the carry output value C of the previous cycle. o1 , the D flip-flop outputs the carry value C of the previous cycle o1 Input the Ci port of the one-bit full adder. The second clock cycle is to convert the input value C of the Ci port into o1 , the second value of the inverse code of x and the second complement pulse of the data to be added d are added. After that, the D flip-flop outputs the carry output value of the one-bit full adder in the previous cycle in each clock cycle, that is, the one-bit full adder Ci port always inputs the carry output value of the previous clock cycle, and finally realizes the effect of pulse complement multiplication and addition.

[0113] Figure 4 is a timing diagram of a serial shift complement multiplier and adder provided by an embodiment of the present invention, such as Figure 4 As shown, execute -(2 3×100)+2, the binary code of 100 01100100 is input into the ShiftIn port of the multiplier-adder in the order of low-order first and high-order last. The Least Significant Bit (LSB) to the Most Significant Bit (MSB) are 0, 0, 1, 0, 0, 1, 1, 0. The input signal of the ShiftInCtrl[2:0] port of the multiplier-adder is 011. The ShiftInCtrl[2:0] port controls the delay of 01100100 for three clock cycles before output. The LSB to MSB of the output signal of the ShiftOut port are 0, 0, 0, 0, 1, 0, 0, 1, 1, 0. The LSB to MSB of the input signal of the Addend port of the multiplier-adder are 0, 1. The A port of the one-bit full adder inputs the inverse code of the output signal of the ShiftOut port. The LSB to MSB of the input signal of the A port are 1, 1, 1, 1, 1, 0, 1, 0, 0, 1. The first clock cycle input of the Ci port of the one-bit full adder is the input signal 1 of the SignBit port. The input signals of the Ci port, the A port, and the Addend port are added to obtain the output signal of the Sum port. The output signal of the Sum port is the serial complement of -798, and the LSB to MSB of the output signal of the Sum port are 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1.

[0114] The serial shift complement multiplier and adder provided by the present invention realizes multiplication operation of powers of two through a shift register, realizes conversion of original code into complement code through an inverter and a first two-to-one data selector, obtains sign bit data and output carry data through a second two-to-one data selector and a D flip-flop, realizes addition operation through a full adder, and can realize positive and negative power of two multiplication and accumulation operation, thereby reducing hardware resource overhead and improving operation efficiency.

[0115] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A serial shift complement multiplier-adder, characterized in that: include: A shift register, a first two-to-one data selector, an inverter, a second two-to-one data selector, a first D flip-flop and a one-bit full adder; The output end of the shift register is divided into two paths, one of which is connected to the input end of the inverter, and the other is connected to the first input end of the first two-to-one data selector; the shift register is used to perform shift processing on the input data to be multiplied; The output end of the inverter is connected to the second input end of the first two-to-one data selector; The inverter is used to convert the original code of the shifted data to be multiplied into an inverse code; The output end of the first two-to-one data selector is connected to the first input end of the one-bit full adder; the first two-to-one data selector is used to select one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied and output them; The input end of the second two-to-one data selector is connected to the output carry end of the one-bit full adder; the output end of the second two-to-one data selector is connected to the input end of the first D flip-flop; the second two-to-one data selector is used to select one of the output carry data of the one-bit full adder and the sign bit of the data to be multiplied and output them; The output end of the first D flip-flop is connected to the second input end of the one-bit full adder; the first D flip-flop is used to delay the output carry data or the sign bit of the data to be multiplied by one cycle and then input it to the input carry end of the one-bit full adder; The one-bit full adder is used to perform addition processing on the input carry data, the shifted data to be multiplied and the data to be added, and output the operation result data.

2. The serial shift complement multiplier-adder according to claim 1, characterized in that: The shift register comprises: a third two-to-one data selector, a second D flip-flop and a data selector; The output end of the third two-to-one data selector is connected to the input end of the second D flip-flop; the third two-to-one data selector is used for synchronous reset; The output end of the second D flip-flop is connected to the input end of the data selector; the second D flip-flop is used to delay the input data to be multiplied; The data selector is used to select one of the output data of the second D flip-flop and output it.

3. The serial shift complement multiplier and adder according to claim 1, characterized in that: The data to be multiplied, the sign bit of the data to be multiplied, the data to be added and the operation result data are all input or output in the form of serial pulse waveforms.

4. The serial shift complement multiplier-adder according to claim 1, characterized in that: The first two-to-one data selector is used to select one of the original code of the shifted data to be multiplied and the inverse code of the shifted data to be multiplied and output them, including: When the enable terminal signal of the first two-to-one data selector is logic 1, the output terminal of the first two-to-one data selector outputs the inverse code of the shifted data to be multiplied; When the enable terminal signal of the first two-to-one data selector is logic 0, the output terminal of the first two-to-one data selector outputs the original code of the shifted data to be multiplied.

5. The serial shift complement multiplier adder according to claim 1, characterized in that: The second two-to-one data selector is used to select one of the output carry data of the one-bit full adder and the sign bit of the data to be multiplied and output them, including: When the enable terminal signal of the second two-to-one data selector is logic 1, the output terminal of the second two-to-one data selector outputs the output carry data of the one-bit full adder; When the enable terminal signal of the second two-to-one data selector is logic 0, the output terminal of the second two-to-one data selector outputs the sign bit of the data to be multiplied.

6. The serial shift complement multiplier adder according to claim 1, characterized in that: When the enable signal of the shift register is logic 1, the data to be multiplied is valid data.

7. The serial shift complement multiplier and adder according to claim 1, characterized in that: When the enable terminal signal of the second two-to-one data selector is logic 1, the data to be added and the operation result data are valid data.

8. The serial shift complement multiplier and adder according to claim 1, characterized in that: The data to be multiplied are input into the input end of the shift register in order from low to high bits.

9. The serial shift complement multiplier and adder according to claim 1, characterized in that: The first D flip-flop is a pulse edge D flip-flop.

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