Sense amplifier circuit

Abstract

The present invention discloses a sense amplifier circuit, which comprises a reference unit circuit, a storage unit circuit and an output circuit; the reference unit circuit is connected to a power supply voltage and provides a reference current for the storage unit circuit and the output unit; the storage unit circuit is connected to the power supply voltage and receives an external control signal, and under the control of the external control signal, operates on a storage tube in the storage unit circuit by using the reference current, including reading, writing and programming; the output circuit amplifies and outputs the data read out by the storage unit, and a comparison circuit is included in the output circuit, the bias current of the comparison circuit is provided by the reference unit circuit, and after comparing the storage current provided by the storage unit circuit with the bias current, the comparison circuit outputs a storage signal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit design and manufacturing, and particularly to a sense amplifier circuit. Background Art

[0002] Flash memory stores data information through the mechanism of storing charges on the floating gate. The SA reads the memory cell information by sensing the current of the memory cell under clearly defined conditions. Under the read reference condition, a programmed memory cell has a high threshold voltage and thus draws a small current; while an erased memory cell has a low threshold voltage and thus draws a large current. The SA usually detects the memory cell information by comparing the memory cell current with a reference current. The reference current can be obtained by mirroring the reference cell current through a current mirror, or can be generated by other reference current source circuits. According to whether a reference cell is used for comparison in the read circuit, the SA can be divided into a single-ended structure and a differential structure. The sense amplifier is an important part of the memory. The sense amplifier senses the small signal on the bit line (BL, BitLine) and reads the data stored in the memory cell by amplifying the small signal. In order to read the data stored in the memory cell, it is necessary to pre-charge the bit line of the memory cell.

[0003] The existing sense amplifier includes a pre-charge circuit. In the pre-charge circuit, a PMOS transistor is used as a switching transistor. The source of the PMOS transistor is connected to the power supply, the gate is connected to the pre-charge control signal, and the drain is connected to the bit line of the memory cell. When the pre-charge control signal changes from a high level to a low level, the PMOS transistor conducts, and the voltage of the bit line of the memory cell increases.

[0004] As Figure 1 shown, it is a schematic structural diagram of an existing sense amplifier. The figure includes a reference cell branch on the left and a memory cell branch on the right. The comparator included in the sense amplifier has two schemes for generating the bias current Ib of the comparator. As Figure 1 shown in the lower right corner of , one is from the bandgap reference circuit BGR, but this will consume standby current. The other scheme is to directly use the power supply VDD to generate it. However, the large variation range of the power supply VDD will make the bias current unstable and fluctuate greatly. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a sense amplifier circuit with low power consumption and fast response.

[0006] To solve the above problems, a sense amplifier circuit according to the present invention includes a reference cell circuit, a memory cell circuit, and an output circuit;

[0007] The reference unit circuit is connected to the power supply voltage to provide a reference current for the storage unit circuit and the output unit;

[0008] The storage unit circuit is connected to the power supply voltage and receives an external control signal. Under the control of the external control signal, the storage tube in the storage unit circuit is operated by the reference current, including reading, writing, and programming;

[0009] The output circuit amplifies and outputs the data read from the storage unit. The output circuit includes a comparison circuit. The bias current of the comparison circuit is provided by the reference unit circuit. After comparing the storage current provided by the storage unit circuit with the bias current, the comparison circuit outputs a storage signal.

[0010] A further improvement is that the sense amplifier circuit is composed of multiple MOS transistors and inverters.

[0011] In the reference unit circuit, the source of the first PMOS is connected to the power supply VDD, the gate and drain of the first PMOS are shorted, the drain of the first PMOS is connected to the drain of the first NMOS, the source of the first NMOS is serially connected to the third NMOS and the fourth NMOS in sequence, the source of the fourth NMOS is connected to the reference storage tube, the source of the reference storage tube is grounded, and the gate of the reference storage tube is connected to the reference word line voltage.

[0012] The source of the first NMOS is also connected to the gate of the first NMOS through a first inverter.

[0013] In the storage unit circuit, the source of the second PMOS is connected to the power supply VDD, the gate of the second PMOS is connected to the gate of the first PMOS, the drain of the second PMOS is connected to the drain of the second NMOS, the source of the second NMOS is serially connected to the fifth NMOS and the sixth NMOS in sequence, the source of the sixth NMOS is connected to the storage tube, and the gate of the storage tube is connected to the word line voltage; the gates of the fifth NMOS and the sixth NMOS are respectively connected to the external control signal.

[0014] The source of the second NMOS is also connected to the gate of the second NMOS through a second inverter.

[0015] In the output circuit, the source of the third PMOS is connected to the power supply VDD, the gate of the third PMOS is connected to the gates of the first PMOS and the second PMOS, the drain of the third PMOS is connected to the drain of the ninth NMOS, the source of the ninth NMOS is grounded, and the gate and drain of the ninth NMOS are shorted.

[0016] The gates of the fourth PMOS and the fifth PMOS are short - circuited, and the gate of the fourth PMOS is short - circuited with its drain. The sources of the fourth PMOS and the fifth PMOS are both connected to the power supply voltage VDD. The drain of the fourth PMOS is connected to the drain of the seventh NMOS, and the gate of the seventh NMOS is connected to the drain of the second NMOS.

[0017] The eighth NMOS is connected to the drain of the fifth PMOS; after the sources of the seventh NMOS and the eighth NMOS are connected, they are sequentially connected in series with the tenth NMOS and the eleventh NMOS, and the source of the eleventh NMOS is grounded; the gate of the eleventh NMOS is connected to the gate of the ninth NMOS; the gate of the tenth NMOS is connected to an external enable signal; the drain of the fifth PMOS is connected to a third inverter, and the output terminal of the third inverter is the output terminal of the sense amplifier circuit; the gate voltage of the eighth NMOS is the difference between the reference voltage and the gate voltage of the seventh NMOS.

[0018] A further improvement is that the first NMOS and the first inverter form a clamping circuit in the reference unit circuit; the second NMOS and the second inverter form a clamping circuit in the memory cell circuit.

[0019] A further improvement is that the third PMOS and the first PMOS form a current mirror, mirroring the current flowing through the first PMOS to the third PMOS, and the third PMOS transmits the mirrored current to the gate of the eleventh NMOS.

[0020] A further improvement is that the mirrored current in the third PMOS is equal to the bias current provided by the reference unit circuit, providing a stable bias current for the comparator in the output circuit.

[0021] The sense amplifier current of the present invention mirrors the reference current provided by the reference unit circuit to the output circuit, providing a more stable bias current for the comparator circuit, making the entire amplifier current work more stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic structural diagram of an existing sense amplifier circuit.

[0023] Figure 2 is a schematic circuit diagram of a sense amplifier circuit provided by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] The specific embodiments of the present invention will be given below in conjunction with the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. According to the following description and the claims, the advantages and features of the present invention will be more clear. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0025] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals throughout the drawings denote the same elements. It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0026] In order to make the technical means, creative features, achieved purposes and effects of the present invention easy to understand, the present invention will be further described below in conjunction with specific illustrations.

[0027] A sense amplifier circuit according to the present invention, the overall structure of which includes a reference unit circuit, a storage unit circuit and an output circuit.

[0028] The reference unit circuit is connected to the power supply voltage and provides a reference current for the storage unit circuit and the output unit.

[0029] The storage unit circuit is connected to the power supply voltage and receives an external control signal, and under the control of the external control signal, the storage tube in the storage unit circuit is operated by the reference current, including reading, writing and programming.

[0030] The output circuit amplifies and outputs the data read out by the storage unit. The output circuit includes a comparison circuit, and the bias current of the comparison circuit is provided by a reference unit circuit. After comparing the storage current provided by the storage unit circuit with the bias current, the comparison circuit outputs a storage signal.

[0031] For the specific structure, refer to Figure 2 As shown in the figure, the sense amplifier circuit is composed of multiple MOS transistors and inverters. P1 to P5 in the figure respectively correspond to the first PMOS to the fifth PMOS, N1 to N11 respectively correspond to the first NMOS to the eleventh NMOS, and IV1 to IV3 respectively correspond to the first to the third inverters.

[0032] In the reference unit circuit, the source of the first PMOS is connected to the power supply VDD, the gate and the drain of the first PMOS are short - circuited, the drain of the first PMOS is connected to the drain of the first NMOS, the source of the first NMOS is connected in series with the third NMOS and the fourth NMOS in sequence, the source of the fourth NMOS is connected to a reference storage tube, the source of the reference storage tube is grounded, and the gate of the reference storage tube is connected to the reference word - line voltage VRWL.

[0033] The reference storage tube in the figure further includes a capacitor CBL. One end of the CBL is connected to the source of the fourth NMOS, and the other end is grounded. The capacitor CBL is the bit - line equivalent capacitor.

[0034] The source of the first NMOS is also connected to the gate of the first NMOS through the first inverter. The first NMOS transistor and the first inverter form a clamping circuit in the reference unit circuit.

[0035] In the storage unit circuit, the source of the second PMOS is connected to the power supply VDD, the gate of the second PMOS is connected to the gate of the first PMOS, the drain of the second PMOS is connected to the drain of the second NMOS, the source of the second NMOS is connected in series with the fifth NMOS and the sixth NMOS in sequence, the source of the sixth NMOS is connected to a storage tube, and the gate of the storage tube is connected to the word - line voltage; the gates of the fifth NMOS and the sixth NMOS are respectively connected to external control signals YA and YB.

[0036] The source of the second NMOS is also connected to the gate of the second NMOS through the second inverter. The second NMOS transistor and the second inverter form a clamping circuit in the storage unit circuit.

[0037] For the output circuit described above, the source of the third PMOS is connected to the power supply VDD, the gate of the third PMOS is connected to the gates of the first PMOS and the second PMOS, the drain of the third PMOS is connected to the drain of the ninth NMOS, the source of the ninth NMOS is grounded, and the gate of the ninth NMOS is shorted to its drain.

[0038] The gate of the fourth PMOS is shorted to the gate of the fifth PMOS, and the gate of the fourth PMOS is shorted to its drain. The sources of the fourth PMOS and the fifth PMOS are both connected to the power supply voltage VDD. The drain of the fourth PMOS is connected to the drain of the seventh NMOS. The gate of the seventh NMOS is connected to the drain of the second NMOS, and the gate of the seventh NMOS is denoted as the node voltage E.

[0039] The eighth NMOS is connected to the drain of the fifth PMOS. After the sources of the seventh NMOS and the eighth NMOS are connected, the tenth NMOS and the eleventh NMOS are connected in series in sequence. The source of the eleventh NMOS is grounded. The gate of the eleventh NMOS is connected to the gate of the ninth NMOS. The gate of the tenth NMOS is connected to the external enable signal EN. The drain of the fifth PMOS is connected to the third inverter, and the output terminal of the third inverter is the output terminal of the sense amplifier circuit. The gate voltage of the eighth NMOS is the difference VREF - E between the reference voltage and the gate voltage of the seventh NMOS.

[0040] The function of the third PMOS is to form a current mirror with the first PMOS, mirror the current flowing through the first PMOS to the third PMOS, and the third PMOS transmits the mirrored current Ib to the gate of the eleventh NMOS. The mirrored current in the third PMOS is equivalent to the bias current provided by the reference unit circuit, providing a stable bias current Ib for the comparator in the output circuit. That is, it is equivalent to introducing the reference current of the reference unit circuit into the comparator of the output circuit through the third PMOS tube as the bias current of the comparator. Since the reference current of the reference unit circuit has strong stability, the bias current of the comparator also has higher stability, which helps to improve the performance of the comparator, such as increasing speed and reducing standby power consumption.

[0041] For the sense amplifier current of the present invention, by mirroring the reference current provided by the reference unit circuit to the output circuit, a more stable bias current is provided for the comparator circuit, making the entire amplifier current work more stably.

[0042] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A sensitive amplifier circuit, characterized in that: The described sense amplifier circuit includes a reference cell circuit, a storage cell circuit, and an output circuit; The reference cell circuit is connected to the power supply voltage and provides a reference current for the storage cell circuit and the output unit; The storage cell circuit is connected to the power supply voltage and receives an external control signal. Under the control of the external control signal, the storage tube in the storage cell circuit is operated by the reference current, including reading, writing, and programming; The output circuit amplifies and outputs the data read from the storage cell. The output circuit includes a comparison circuit. The bias current of the comparison circuit is provided by the reference cell circuit. By mirroring the reference current provided by the reference cell circuit to the output circuit, a bias current is provided for the comparator circuit; The comparison circuit outputs a storage signal after comparing the storage current provided by the storage cell circuit with the bias current.

2. The sense amplifier circuit according to claim 1, wherein: The described sense amplifier circuit is composed of multiple MOS transistors and inverters; For the reference cell circuit, the source of the first PMOS is connected to the power supply VDD, the gate and drain of the first PMOS are shorted, the drain of the first PMOS is connected to the drain of the first NMOS, the source of the first NMOS is serially connected to the third NMOS and the fourth NMOS in sequence, the source of the fourth NMOS is connected to the reference storage tube, the source of the reference storage tube is grounded, and the gate of the reference storage tube is connected to the reference word line voltage; The source of the first NMOS is also connected to the gate of the first NMOS through a first inverter; For the storage cell circuit, the source of the second PMOS is connected to the power supply VDD, the gate of the second PMOS is connected to the gate of the first PMOS, the drain of the second PMOS is connected to the drain of the second NMOS, the source of the second NMOS is serially connected to the fifth NMOS and the sixth NMOS in sequence, the source of the sixth NMOS is connected to the storage tube, and the gate of the storage tube is connected to the word line voltage; the gates of the fifth NMOS and the sixth NMOS are respectively connected to the external control signal; The source of the second NMOS is also connected to the gate of the second NMOS through a second inverter; For the output circuit, the source of the third PMOS is connected to the power supply VDD, the gate of the third PMOS is connected to the gates of the first PMOS and the second PMOS, the drain of the third PMOS is connected to the drain of the ninth NMOS, the source of the ninth NMOS is grounded, and the gate and drain of the ninth NMOS are shorted; The gates of the fourth PMOS and the fifth PMOS are shorted, and the gate and drain of the fourth PMOS are shorted. The sources of the fourth PMOS and the fifth PMOS are both connected to the power supply voltage VDD. The drain of the fourth PMOS is connected to the drain of the seventh NMOS, and the gate of the seventh NMOS is connected to the drain of the second NMOS; The eighth NMOS is connected to the drain of the fifth PMOS; the sources of the seventh NMOS and the eighth NMOS are connected and then serially connected to the tenth NMOS and the eleventh NMOS in sequence, and the source of the eleventh NMOS is grounded; the gate of the eleventh NMOS is connected to the gate of the ninth NMOS; the gate of the tenth NMOS is connected to an external enable signal; the drain of the fifth PMOS is connected to a third inverter, and the output terminal of the third inverter is the output terminal of the sense amplifier circuit; the gate voltage of the eighth NMOS is the difference between the reference voltage and the gate voltage of the seventh NMOS.

3. The sense amplifier circuit according to claim 2, wherein: The first NMOS and the first inverter form a clamping circuit in the reference cell circuit; the second NMOS and the second inverter form a clamping circuit in the storage cell circuit.

4. The sense amplifier circuit according to claim 3, wherein: The third PMOS and the first PMOS form a current mirror to mirror the current flowing through the first PMOS to the third PMOS, and the third PMOS transmits the mirrored current to the gate of the eleventh NMOS.

5. The sense amplifier circuit according to claim 4, wherein: The mirrored current in the third PMOS is equivalent to the bias current provided by the reference cell circuit and provides a stable bias current for the comparator in the output circuit.

6. The sense amplifier circuit according to claim 2, wherein: There is also a bit-line equivalent capacitance between the source and drain terminals of the reference storage transistor.

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