Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and an operating method thereof can be provided herein. The semiconductor memory device can include a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on the memory cells. The control logic controls the read operation of the peripheral circuit. During the read operation, the control logic controls the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the memory cells, a first pass voltage is applied to an unselected word line disposed adjacent to the selected word line, and a second pass voltage is applied to an unselected word line not disposed adjacent to the selected word line. The peripheral circuit adjusts a magnitude of the first pass voltage or a magnitude of the second pass voltage based on a temperature of the semiconductor memory device.

Description

TECHNICAL FIELD

[0001] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a semiconductor memory device. BACKGROUND

[0002] A memory device can have a two-dimensional (2D) structure in which strings are horizontally arranged on a semiconductor substrate. Alternatively, the memory device can have a three-dimensional (3D) structure in which strings are vertically stacked on a semiconductor substrate. Since a memory device having a 2D structure is about to reach its physical scaling limit (i.e., integration limit), a 3D memory device including a plurality of memory cells vertically stacked on a semiconductor substrate has been produced. SUMMARY

[0003] Various embodiments of the present disclosure relate to a semiconductor memory device having improved read performance depending on temperature change.

[0004] Embodiments of the present disclosure can provide a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and a control logic. The memory cell array can include a plurality of memory cells. The peripheral circuit can be configured to perform a read operation on the plurality of memory cells. The control logic can be configured to control the read operation of the peripheral circuit. During the read operation, the control logic can control the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the plurality of memory cells, a first pass voltage is applied to an unselected word line among the plurality of word lines that is adjacently disposed with the selected word line, and a second pass voltage is applied to an unselected word line among the plurality of word lines that is not adjacently disposed with the selected word line. The peripheral circuit can be further configured to adjust a magnitude of the first pass voltage or a magnitude of the second pass voltage based on a temperature of the semiconductor memory device.

[0005] In an embodiment, the peripheral circuit can include a voltage generator, an address decoder, a read-write circuit, and a temperature sensor. The voltage generator can be configured to generate the read voltage, the first pass voltage, and the second pass voltage. The address decoder can be configured to transfer the read voltage, the first pass voltage, and the second pass voltage to the selected word line, the unselected word line adjacently disposed with the selected word line, and the unselected word line not adjacently disposed with the selected word line, respectively. The read-write circuit can be configured to sense a threshold voltage of a memory cell coupled to the selected word line. The temperature sensor can be configured to sense a temperature and generate a temperature code based on the temperature. The voltage generator can be further configured to adjust the magnitude of the first pass voltage or the magnitude of the second pass voltage based on the temperature code.

[0006] In an embodiment, the peripheral circuit can decrease the magnitude of the second pass voltage as the temperature increases.

[0007] In an embodiment, the peripheral circuit can increase the magnitude of the first pass voltage as the temperature increases.

[0008] In an embodiment, the peripheral circuit can keep the first pass voltage constant regardless of the temperature.

[0009] In an embodiment, the peripheral circuit can decrease the magnitude of the first pass voltage as the temperature increases.

[0010] In an embodiment, the peripheral circuit can adjust the magnitude of the first pass voltage and the second pass voltage such that the absolute value of the slope of the second pass voltage as a function of an increase in the temperature is greater than the absolute value of the slope of the first pass voltage as a function of the increase.

[0011] Embodiments of the present disclosure can provide a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and a control logic. The memory cell array can include a plurality of memory cells. The peripheral circuit can be configured to perform a read operation on the plurality of memory cells. The control logic can be configured to control the read operation of the peripheral circuit. During the read operation, the control logic can control the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the plurality of memory cells, and such that a first pass voltage is applied to an unselected word line among the plurality of word lines disposed adjacent to the selected word line in a direction of a drain select line, a second pass voltage is applied to an unselected word line among the plurality of word lines disposed adjacent to the selected word line in a direction of a source select line, and a third pass voltage is applied to an unselected word line among the plurality of word lines not disposed adjacent to the selected word line. The peripheral circuit can be further configured to adjust a magnitude of at least one of the first pass voltage, the second pass voltage, and the third pass voltage based on a temperature of the semiconductor memory device.

[0012] In an embodiment, the peripheral circuit can include a voltage generator, an address decoder, a read-write circuit, and a temperature sensor. The voltage generator can be configured to generate the read voltage, the first pass voltage, the second pass voltage, and the third pass voltage. The address decoder can be configured to transfer the read voltage, the first pass voltage, the second pass voltage, and the third pass voltage to the selected word line, the unselected word line disposed adjacent to the selected word line in the direction of the drain select line, the unselected word line disposed adjacent to the selected word line in the direction of the source select line, and the unselected word line not disposed adjacent to the selected word line, respectively. The read-write circuit can be configured to sense a threshold voltage of a memory cell coupled to the selected word line. The temperature sensor can be configured to sense a temperature and generate a temperature code based on the temperature. The voltage generator can be further configured to adjust the magnitude of at least one of the first pass voltage to the third pass voltage based on the temperature code.

[0013] In an embodiment, the peripheral circuit can decrease the amplitude of the third pass voltage as the temperature increases.

[0014] In an embodiment, the peripheral circuit can increase the amplitudes of the first pass voltage and the second pass voltage as the temperature increases.

[0015] In an embodiment, the peripheral circuit can adjust the amplitudes of the first pass voltage and the second pass voltage such that a slope of the first pass voltage as a function of an increase in temperature is greater than a slope of the second pass voltage as a function of the increase.

[0016] In an embodiment, the peripheral circuit can adjust the amplitudes of the first pass voltage and the second pass voltage such that a slope of the second pass voltage as a function of an increase in temperature is greater than a slope of the first pass voltage as a function of the increase.

[0017] In an embodiment, the peripheral circuit can increase the amplitude of the first pass voltage as the temperature increases. The peripheral circuit can keep the second pass voltage constant independent of temperature.

[0018] In an embodiment, the peripheral circuit can increase the amplitude of the second pass voltage as the temperature increases. The peripheral circuit can keep the first pass voltage constant independent of temperature.

[0019] In an embodiment, the peripheral circuit can increase the amplitude of the first pass voltage and decrease the amplitude of the second pass voltage as the temperature increases.

[0020] In an embodiment, the peripheral circuit can adjust the amplitudes of the second pass voltage and the third pass voltage such that an absolute value of a slope of the third pass voltage as a function of an increase in temperature is greater than an absolute value of a slope of the second pass voltage as a function of the increase.

[0021] In an embodiment, the peripheral circuit can decrease the amplitude of the first pass voltage and increase the amplitude of the second pass voltage as the temperature increases.

[0022] In an embodiment, the peripheral circuit can adjust the amplitudes of the first pass voltage and the third pass voltage such that an absolute value of a slope of the third pass voltage as a function of an increase in temperature is greater than an absolute value of a slope of the first pass voltage as a function of the increase.

[0023] Embodiments of the present disclosure can provide a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and a control logic. The memory cell array can include a plurality of memory cells. The peripheral circuit can be configured to perform a read operation on the plurality of memory cells. The control logic can be configured to control the read operation of the peripheral circuit. During the read operation, the control logic can control the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the plurality of memory cells, and such that an adjacent pass voltage is applied to an unselected word line among the plurality of word lines that is adjacently disposed from the selected word line, and a plurality of different non-adjacent pass voltages are applied to unselected word lines among the plurality of word lines that are not adjacently disposed from the selected word line. The peripheral circuit can be further configured to adjust a magnitude of the adjacent pass voltage or a magnitude of the non-adjacent pass voltage based on a temperature of the semiconductor memory device.

[0024] Embodiments of the present disclosure can provide an operating method of a semiconductor memory device including a memory cell string of memory cells. The operating method can include grouping non-target word lines into a proximal group and a distal group each including one or more word lines, applying an operation voltage to a target word line, applying one or more proximal voltages to the proximal group, respectively, and applying one or more distal voltages to the distal group, respectively. The proximal group can be disposed closer to the target word line than the distal group, and the target word line and the non-target word lines can be coupled to the memory cells, respectively. The step of applying the distal voltages can include changing the distal voltages in inverse proportion to a temperature. The step of applying the proximal voltages can include changing at least one of the proximal voltages in direct proportion to the temperature.

[0025] In embodiments, the step of applying the proximal voltages can further include changing another one of the proximal voltages in a different direct proportion to the temperature.

[0026] In embodiments, the step of applying the proximal voltages can further include keeping another one of the proximal voltages constant with respect to the temperature.

[0027] In embodiments, the step of applying the proximal voltages can further include changing another one of the proximal voltages in inverse proportion to the temperature. A gradient of the distal voltages during the changing of the distal voltages can be greater than a gradient of the other proximal voltage during the changing of the other proximal voltage.

[0028] Embodiments of this disclosure may provide a method of operating a semiconductor memory device, the semiconductor memory device including a string of memory cells respectively connected to word lines. The method of operation may include: grouping the remaining word lines into a near-end group and a far-end group, each comprising one or more word lines; applying an operating voltage to a target word line; applying one or more near-end voltages to the near-end group respectively; and applying one or more far-end voltages to the far-end group respectively. The near-end group may be configured to be closer to the target word line than the far-end group. The step of applying the far-end voltage may include changing the far-end voltage in a negatively proportional manner with temperature. The step of applying the near-end voltage may include keeping at least one of the near-end voltages constant relative to temperature.

[0029] In an implementation, the step of applying a proximal voltage may further include changing another proximal voltage in a manner proportional to temperature.

[0030] Embodiments of this disclosure provide a method of operating a semiconductor memory device, the semiconductor memory device including a string of memory cells respectively connected to word lines. The method of operation may include: grouping remaining word lines into a near-end group and a far-end group, each comprising one or more word lines; applying an operating voltage to a target word line; applying one or more near-end voltages to the near-end group respectively; and applying one or more far-end voltages to the far-end group respectively. The near-end group may be configured to be closer to the target word line than the far-end group. The step of applying the far-end voltage may include changing the far-end voltage in a negatively proportional manner with temperature. The step of applying the near-end voltage may include changing at least one of the near-end voltages in a negatively proportional manner with temperature. The gradient of the far-end voltage during the change of the far-end voltage may be greater than the gradient of the near-end voltage during the change of the near-end voltage.

[0031] In an implementation, the step of applying the proximal voltage may further include changing one of the proximal voltages in proportion to the temperature. Attached Figure Description

[0032] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0033] Figure 2 This is an example Figure 1 A block diagram of an embodiment of the memory cell array 110.

[0034] Figure 3 This is an example Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0035] Figure 4 This is an example Figure 2 A circuit diagram of an example of storage block BLKb in storage blocks BLK1 to BLKz.

[0036] Figure 5 is a circuit diagram illustrating an example of a memory block BLKc among a plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 of Figure 1 .

[0037] Figure 6 is a graph describing a read operation of a semiconductor memory device.

[0038] Figure 7A is a graph illustrating a relationship between a pass voltage and a temperature used in a typical read operation.

[0039] Figure 7B is a graph illustrating temperature-dependent operation characteristics of a memory cell when a pass voltage of Figure 7A is used.

[0040] Figure 8A is a graph illustrating a relationship between a pass voltage and a temperature used in a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0041] Figure 8B is a graph illustrating temperature-dependent operation characteristics of a memory cell when a pass voltage of Figure 8A is used.

[0042] Figure 9 is a graph describing a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0043] Figure 10A is a graph illustrating a relationship between a pass voltage and a temperature used in a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0044] Figure 10B is a graph illustrating temperature-dependent operation characteristics of a memory cell when a pass voltage of Figure 10A is used.

[0045] Figure 11A and Figure 11B is a graph illustrating a relationship between a pass voltage and a temperature used in a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0046] Figure 12 is a graph describing a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0047] Figures 13A to 13C is a graph illustrating a relationship between a pass voltage and a temperature used in a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0048] Figure 14 is a graph describing a read operation of a semiconductor memory device according to an embodiment of the disclosure.

[0049] Figure 15 is a graph illustrating a temperature-dependent operating characteristic of a memory cell when a pass voltage of Figure 14 is used.

[0050] Figure 16 is a block diagram illustrating a memory system 1000 including a semiconductor memory device 100 described with reference to Figure 1 .

[0051] Figure 17 is a block diagram illustrating an application example of a memory system. Figure 16

[0052] Figure 18 is a block diagram illustrating a computing system including a memory system described with reference to Figure 17 . DETAILED DESCRIPTION

[0053] The specific structure or function descriptions in the embodiments of the disclosure introduced in the present specification or application are exemplified for describing various embodiments of the disclosure. Various embodiments of the disclosure can be practiced in various forms, and should not be interpreted as being limited to the embodiments described in the specification or application.

[0054] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0055] Referring to Figure 1 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read-write circuit 130, a control logic 140, a voltage generator 150, and a temperature sensor 160.

[0056] ​The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz are coupled to the address decoder 120 through the word lines WL. The memory blocks BLK1 to BLKz are coupled to the read / write circuit 130 through the bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells can be non-volatile memory cells, and can be implemented as non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be implemented as a memory cell array having a two-dimensional (2D) structure. In an embodiment, the memory cell array 110 can be implemented as a memory cell array having a three-dimensional (3D) structure. Each memory cell included in the memory cell array can store at least one bit of data. In an embodiment, each memory cell included in the memory cell array 110 can be a single-level cell (SLC) storing 1 bit of data. In an embodiment, each memory cell included in the memory cell array 110 can be a multi-level cell (MLC) storing 2 bits of data. In an embodiment, each memory cell included in the memory cell array 110 can be a triple-level cell (TLC) storing 3 bits of data. In an embodiment, each memory cell included in the memory cell array 110 can be a quad-level cell (QLC) storing 4 bits of data. According to an embodiment, the memory cell array 110 can include a plurality of memory cells each of which stores 5 bits or more of data.

[0057] The address decoder 120, the read / write circuit 130, the control logic 140, the voltage generator 150, and the temperature sensor 160 operate as peripheral circuits for driving the memory cell array 110. The address decoder 120 is coupled to the memory cell array 110 through the word lines WL. The address decoder 120 can operate under the control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) provided in the semiconductor memory device 100.

[0058] The address decoder 120 can decode a block address among the received address. The address decoder 120 selects at least one memory block based on the decoded block address. Further, when a read voltage application operation is performed during a read operation, the address decoder 120 can apply a read voltage Vread generated by the voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining word lines (i.e., unselected word lines). Further, during a program verify operation, the address decoder 120 can apply a verify voltage generated by the voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining word lines (i.e., unselected word lines).

[0059] The address decoder 120 can decode a column address among the received addresses. The address decoder 120 can transmit the decoded column address to the read / write circuit 130.

[0060] The read operation and the program operation of the semiconductor memory device 100 are each performed in units of pages. Addresses received in response to requests for the read operation and the program operation can include a block address, a row address, and a column address. The address decoder 120 can select one memory block and one word line according to the block address and the row address. The column address can be decoded by the address decoder 120 and then can be provided to the read / write circuit 130.

[0061] The address decoder 120 can include a block decoder, a row decoder, a column decoder, an address buffer, etc.

[0062] The read / write circuit 130 includes a plurality of page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110 and as a "write circuit" during a write operation thereof. The plurality of page buffers PB1 to PBm are coupled to the memory cell array 110 through bit lines BL1 to BLm. To sense a threshold voltage of a memory cell during a read operation and a program verify operation, each of the page buffers PB1 to PBm can sense a change in an amount of current flowing according to a program state of a corresponding memory cell through a sense node while continuously providing a sense current to a bit line coupled to the memory cell and latch the sensed change as sense data. The read / write circuit 130 can output data DATA in response to a page buffer control signal CTR PB and operations output from the control logic 140.

[0063] During a read operation, the read / write circuit 130 can sense data stored in the memory cell and temporarily store the read data, and then can output the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In an embodiment, the read / write circuit 130 can include a column selection circuit, etc., as well as a page buffer (or a page register).

[0064] The control logic 140 is coupled to the address decoder 120, the read / write circuit 130, and the voltage generator 150. The control logic 140 can receive a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 can control overall operations of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 can output a control signal CTR PB for controlling a plurality of page buffers PB1 to PBm included in the read / write circuit 130. The control logic 140 can control the read / write circuit 130 to perform a read operation of the memory cell array 110.

[0065] The voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass required for a read operation in response to a control signal output from the control logic 140. In addition, the voltage generator 150 can generate voltages required for generating various control signals for controlling operations of the semiconductor memory device.

[0066] The temperature sensor 160 can sense a temperature of the semiconductor memory device 100, can generate a temperature code T CODE based on a result of the sensing, and transmit the temperature code to the voltage generator 150. The temperature code T CODE may be a digital code indicating a temperature of the semiconductor memory device. The voltage generator 150 can control at least some voltages required for an operation of the semiconductor memory device 100 based on the temperature code T CODE . For example, the voltage generator 150 can control a read voltage Vread or a pass voltage Vpass used for a read operation based on the temperature code T CODE .

[0067] In general, an operating characteristic of a memory cell included in the memory cell array 110 can vary with a change in a temperature of the semiconductor memory device 100. In this case, when a read voltage Vread or a pass voltage Vpass determined without considering a temperature of the semiconductor memory device 100 is used, a reliability of a read operation can be deteriorated. In the semiconductor memory device 100 according to an embodiment of the disclosure, a voltage level of the pass voltage Vpass to be used for a read operation is controlled in accordance with a temperature change, whereby a problem that a reliability of a read operation is deteriorated in accordance with a temperature change can be prevented.

[0068] Figure 2 is a block diagram illustrating an embodiment of the memory cell array 110 of Figure 1 .

[0069] Referring to Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block has a three-dimensional (3D) structure. Each memory block can include a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged in +X, +Y, and +Z directions. The structure of each memory block will be described in greater detail below with reference to Figure 3 and Figure 4 .

[0070] Figure 3 is a circuit diagram illustrating a memory block BLKa among the memory blocks BLK1 to BLKz of Figure 2 .

[0071] Referring to Figure 3The storage block BLKa can include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the storage block BLKa, m cell strings can be arranged in a row direction (i.e., a positive (+) X direction). In Figure 3 In an embodiment, two cell strings are illustrated as being arranged in a column direction (i.e., a positive (+) Y direction). However, this illustration is made for ease of description, and it will be understood that three or more cell strings can be arranged in the column direction.

[0072] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0073] The select transistors SST and DST and the memory cells MC1 to MCn can have similar structures. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing the channel layer can be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating layer, the charge storage layer, and the blocking insulating layer can be provided in each cell string.

[0074] The source select transistors SST of each cell string are coupled between a common source line CSL and the memory cells MC1 to MCp.

[0075] In an embodiment, the source select transistors of the cell strings arranged in the same row are coupled to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are coupled to different source select lines. In Figure 3 In an embodiment, the source select transistors of the cell strings CS11 to CS1m in the first row are coupled to a first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second source select line SSL2.

[0076] In an embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m can be commonly coupled to one source select line.

[0077] The first to nth memory cells MC1 to MCn in each cell string are coupled between the source select transistor SST and the drain select transistor DST.

[0078] The first memory cell MC1 to the n-th memory cell MCn can be divided into the first memory cell MC1 to the p-th memory cell MCp and the (p+1)-th memory cell MCp+1 to the n-th memory cell MCn. The first memory cell MC1 to the p-th memory cell MCp are arranged in order in a direction opposite to the positive (+Z) direction and are connected in series between the source select transistor SST and the tub transistor PT. The (p+1)-th memory cell MCp+1 to the n-th memory cell MCn are arranged in order in the +Z direction and are connected in series between the tub transistor PT and the drain select transistor DST. The first memory cell MC1 to the p-th memory cell MCp and the (p+1)-th memory cell MCp+1 to the n-th memory cell MCn are connected to each other through the tub transistor PT. The gates of the first memory cell MC1 to the n-th memory cell MCn of each cell string are connected to the first word line WL1 to the n-th word line WLn, respectively.

[0079] The gate of the tub transistor PT of each cell string is connected to the pipe line PL.

[0080] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cell MCp+1 to MCn. The drain select transistors DST of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0081] The cell strings arranged in the column direction can be connected to the bit line extending in the column direction. In the embodiment, the cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm. Figure 3

[0082] The memory cells connected to the same word line among the cell strings arranged in the row direction form a single page. For example, the memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m in the first row form a single page. The memory cells connected to the first word line WL1 among the cell strings CS21 to CS2m in the second row form another single page. The cell strings arranged in a single row direction can be selected by selecting one of the drain select lines DSL1 and DSL2. A page can be selected from the selected cell strings by selecting one of the word lines WL1 to WLn.

[0083] ​In an embodiment, instead of the first to mth bit lines BL1 to BLm, even and odd bit lines can be provided. Even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be coupled to respective even bit lines. Odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be coupled to respective odd bit lines.

[0084] In an embodiment, one or more of the first to n-th memory cells MC1 to MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As the number of dummy memory cells provided increases, the operation reliability of the memory block BLKa can improve, while the size of the memory block BLKa increases. As the number of dummy memory cells provided decreases, the size of the memory block BLKa can decrease, while the operation reliability of the memory block BLKa can deteriorate.

[0085] To efficiently control the one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. All or some of the dummy memory cells can be subjected to a program operation before or after an erase operation on the memory block BLKa is performed. When the erase operation is performed after the program operation has been performed, each dummy memory cell can have the desired threshold voltage by controlling a voltage applied to a dummy word line coupled to each dummy memory cell.

[0086] Figure 4 is a circuit diagram illustrating an example of a memory block BLKb among the memory blocks BLK1 to BLKz of Figure 2 .

[0087] Referring to Figure 4 , the memory block BLKb can include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends in a positive Z (+Z) direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' can include at least one source select transistor SST, first to n-th memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0088] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In an embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly connected to a single source select line.

[0089] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0090] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0091] As a result, besides Figure 4 The text excludes tubular transistors (PTs) from each unit string. Figure 4 The storage block BLKb has the same characteristics as Figure 3 The circuitry is similar to that of the storage block BLKa.

[0092] In this implementation, instead of the first bit line BL1 to the m-th bit line BLm, even bit lines and odd bit lines can be provided. Furthermore, the even-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the odd bit lines.

[0093] In an embodiment, one or more of the first memory cell MC1 to the n-th memory cell MCn can function as a dummy memory cell. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKb improves, but the size of the memory block BLKb increases. As fewer dummy memory cells are provided, the size of the memory block BLKb decreases, but the operation reliability of the memory block BLKb can deteriorate.

[0094] To efficiently control the one or more dummy memory cells, each of the dummy memory cells can have a desired threshold voltage. All or some of the dummy memory cells can be subjected to a program operation before or after an erase operation on the memory block BLKb is performed. When the erase operation is performed after the program operation has been performed, the dummy memory cells can have the desired threshold voltage by controlling a voltage to be applied to a dummy word line coupled to each of the dummy memory cells.

[0095] Figure 5 is a circuit diagram illustrating an example of a memory block BLKc included in the memory blocks BLK1 to BLKz of the memory cell array 110. Figure 1

[0096] Referring to Figure 5 The memory block BLKc can include a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm can be respectively coupled to a plurality of bit lines BL1 to BLm. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to n-th memory cells MC1 to MCn, and at least one drain select transistor DST.

[0097] The select transistors SST and DST and the memory cells MC1 to MCn can have similar structures. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing the channel layer can be disposed in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating layer, the charge storage layer, and the blocking insulating layer can be disposed in each cell string.

[0098] The source select transistor SST of each cell string is coupled between a common source line CSL and the memory cells MC1 to MCn.

[0099] ​The first memory cell MC1 to the nth memory cell MCn in each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0100] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0101] Memory cells connected to the same word line can form a single page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page can be selected from the selected cell string by choosing one of the word lines WL1 to WLn.

[0102] In other embodiments, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Among the unit strings CS1 to CSm, even-numbered unit strings can be connected to even-numbered bit lines respectively, and odd-numbered unit strings can be connected to odd-numbered bit lines respectively.

[0103] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array with a 3D structure. Further, as... Figure 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array with a 2D structure.

[0104] Figure 6 This is a diagram illustrating the read operation of a semiconductor memory device. (Refer to...) Figure 6 This illustrates a cell string CS included in a memory cell array of a semiconductor memory device. Figure 6 The unit string CS can be Figure 3 The shown unit strings are CS11 to CS1m and CS21 to CS2m. Alternatively, Figure 6 The unit string CS can be Figure 4 The shown unit strings are one of the unit strings CS11′ to CS1m′ and CS21′ to CS2m′. Alternatively, Figure 6 The unit string CS can be Figure 5 The unit string shown is one of the unit strings CS1 to CSm. Figure 6 The diagram illustrates the source select line SSL, multiple word lines WL1 to WLn, and drain select line DSL connected to the cell string CS, while the illustrations of the common source line and bit lines are omitted.

[0105] During a read operation of the semiconductor memory device, among the word lines WL1 to WLn coupled to the cell string CS, a read voltage Vread can be applied to a selected word line WLs, and a pass voltage Vpass can be applied to unselected word lines WL1 to WLs-1 and WLs+1 to WLn. During the read operation, information on whether or not the threshold voltage of each memory cell coupled to the selected word line WLs is greater than the read voltage Vread is read out based on the read voltage Vread applied to the selected word line WLs. The pass voltage Vpass applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn during the read operation can be greater than the threshold voltage of all the memory cells coupled to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. A source select line voltage VSSL applied to the source select line SSL during the read operation can be a voltage for turning on a source select transistor. Further, a drain select line voltage VDSL applied to the drain select line DSL during the read operation can be a voltage for turning on a drain select transistor.

[0106] Figure 7A is a graph illustrating a relationship between a pass voltage used in a typical read operation and temperature. Figure 7B is a graph illustrating a temperature-dependent operation characteristic of a memory cell when a pass voltage of Figure 7A is used.

[0107] Referring to Figure 7A , a constant value can be used as the amplitude of the pass voltage Vpass applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn in a typical read operation regardless of a temperature change of the semiconductor memory device 100.

[0108] Referring to Figure 7B , a relationship between a gate voltage Vg and a cell current I CELL during a read operation or a program verify operation performed on a selected memory cell in accordance with the temperature of the semiconductor memory device is illustrated.

[0109] As shown in Figure 7B , the higher the temperature of the semiconductor memory device is, the higher the cell current I CELL flowing through a memory cell to which a gate voltage Vg is supplied is, and the lower the temperature of the semiconductor memory device is, the smaller the cell current I CELL flowing through a memory cell to which the same gate voltage Vg is supplied is. That is, in a comparison between a case where the semiconductor memory device is operated in a relatively high temperature state and a case where the semiconductor memory device is operated in a relatively low temperature state, the cell current I CELLmay vary with temperature. Due to a difference between the cell current I CELL at a high temperature of the semiconductor memory device and the cell current I CELL at a low temperature of the semiconductor memory device, it is difficult to accurately determine the threshold voltage of the selected memory cell during a read operation.

[0110] Figure 8A is a graph illustrating a relationship between a pass voltage and a temperature used in a read operation of a semiconductor memory device according to an embodiment of the present disclosure. Figure 8B is a graph illustrating an operating characteristic of a memory cell depending on a temperature of a semiconductor memory device 100 when a pass voltage of Figure 8A is used.

[0111] Referring to Figure 8A , the amplitude of the pass voltage Vpass applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn depending on the temperature of the semiconductor memory device 100 during a read operation of the semiconductor memory device according to an embodiment of the present disclosure is illustrated. More specifically, when the temperature of the semiconductor memory device 100 is relatively high, a voltage having a relatively low value can be used as the pass voltage Vpass to be applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. In contrast, when the temperature of the semiconductor memory device 100 is relatively low, a voltage having a relatively high value can be used as the pass voltage Vpass to be applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn.

[0112] Accordingly, as shown in Figure 8B , compared to the embodiment of Figure 7B , a difference between the cell current I CELL at a high temperature of the semiconductor memory device and the cell current I CELL at a low temperature of the semiconductor memory device can be reduced. Specifically, at a gate voltage equal to or greater than a certain voltage level, there is almost no difference between the cell current I CELL at a high temperature of the semiconductor memory device and the cell current I CELL at a low temperature of the semiconductor memory device. However, even in this case, at a gate voltage less than the certain voltage level, a difference between the cell current I CELL at a high temperature of the semiconductor memory device and the cell current I CELL at a low temperature of the semiconductor memory device still exists. Specifically, there is a difference between the slope of the gate voltage Vg and the cell current I CELL , which results in a difference between the cell currents corresponding to the read voltage applied to the gate of the selected memory cell during a read operation. Accordingly, due to the difference between the cell current I CELLthe difference between the threshold voltages of the selected memory cell and the unselected memory cell, which causes it to be difficult to accurately determine the threshold voltage of the selected memory cell during a read operation.

[0113] Figure 9 is a diagram describing a read operation of a semiconductor memory device according to an embodiment of the disclosure. Referring to Figure 9 , a cell string CS included in an array of memory cells of a semiconductor memory device is exemplified. Figure 9 The cell string CS can be any one of the cell strings CS11 to CS1m and CS21 to CS2m illustrated in FIG. 1A. Figure 3 The cell string CS can be any one of the cell strings CS11 to CS1m and CS21 to CS2m illustrated in FIG. 1A. Figure 9 The cell string CS can be any one of the cell strings CS11 to CS1m and CS21 to CS2m illustrated in FIG. 1A. Figure 4 The cell string CS can be any one of the cell strings CS11 to CS1m and CS21 to CS2m illustrated in FIG. 1A. Figure 9 The cell string CS can be any one of the cell strings CS11 to CS1m and CS21 to CS2m illustrated in FIG. 1A. Figure 5 In FIG. 1B, a source select line SSL, a plurality of word lines WL1 to WLn, and a drain select line DSL coupled to the cell string CS are exemplified, and the illustration of a common source line and a bit line is omitted. Figure 9 During a read operation of a semiconductor memory device, a read voltage Vread is applied to a selected word line WLs among the word lines WL1 to WLn coupled to the cell string CS. At the same time, a first pass voltage Vpass1 can be applied to word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. A second pass voltage Vpass2 can be applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn except for the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs.

[0114] In this specification, the first pass voltage Vpass1 applied to the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs can be referred to as an "adjacent pass voltage", and the second pass voltage Vpass2 applied to the unselected word lines WL1 to WLs-2 and WLs+2 to WLn not disposed adjacent to the selected word line WLs can be referred to as a "non-adjacent pass voltage".

[0115]

[0116] ​During a read operation, information about whether the threshold voltage of each memory cell coupled to the selected word line WLs is greater than the read voltage Vread is read based on the read voltage Vread applied to the selected word line WLs. During the read operation, the first pass voltage Vpassl and the second pass voltage Vpass2 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn can be a voltage greater than the threshold voltage of all memory cells coupled to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. The source select line voltage VSSL applied to the source select line SSL during the read operation can be a voltage for turning on the source select transistor. Further, the drain select line voltage VDSL applied to the drain select line DSL during the read operation can be a voltage for turning on the drain select transistor. Although not shown, whenever the word line WLs is selected for each read operation, the control logic 140 can group the unselected word lines WL1 to WLs-1 and WLs+1 to WLn into a group to which the adjacent pass voltage Vpassl is to be applied and a group to which the non-adjacent pass voltage Vpass2 is to be applied.

[0117] In the semiconductor memory device 100 according to the embodiment of the present disclosure, the first pass voltage Vpassl applied to the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn and the second pass voltage Vpass2 applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn can be used separately. Hereinafter, the relationship between the pass voltages used in the read operation of the semiconductor memory device and the temperature will be described with reference to FIGS. 10A and 10B. Figure 10B A method of controlling the first pass voltage Vpassl and the second pass voltage Vpass2 depending on the temperature of the semiconductor memory device 100 according to the embodiment of the present disclosure will be described.

[0118] Figure 10A is a graph illustrating the relationship between the pass voltage used in the read operation of the semiconductor memory device and the temperature according to the embodiment of the present disclosure. Figure 10B is a graph illustrating the temperature-dependent operation characteristics of the memory cell when the pass voltage of Figure 10A is used.

[0119] Referring to Figure 10A , the amplitude of the first pass voltage Vpassl and the second pass voltage Vpass2 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn depending on the temperature of the semiconductor memory device 100 during the read operation of the semiconductor memory device according to the embodiment of the present disclosure will be described with reference to FIGS. 11A and 11B. As described above with reference to FIGS. 10A and 10B, the first pass voltage Vpassl and the second pass voltage Vpass2 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn during the read operation of the semiconductor memory device can be controlled depending on the temperature of the semiconductor memory device 100. Figure 9As described, a first pass voltage Vpass1 can be applied to word lines WLs-1 and WLs+1, which are adjacent to the selected word line WLs, among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. A second pass voltage Vpass2 can be applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn. According to embodiments of this disclosure, as the temperature of the semiconductor memory device 100 increases, the amplitude of the first pass voltage Vpass1 increases and the amplitude of the second pass voltage Vpass2 decreases. Conversely, as the temperature decreases, the amplitude of the first pass voltage Vpass1 decreases and the amplitude of the second pass voltage Vpass2 increases. The cell current I flowing through the memory cells selected as the object of a read operation in the memory cell array 110 included in the semiconductor memory device 100... CELL Of the components, the linear current component is highly sensitive to the first pass voltage Vpass1 applied to the unselected word lines WLs-1 and WLs+1, which are adjacent to the selected memory cell. Therefore, the first pass voltage Vpass1 can increase with increasing temperature. Meanwhile, the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn, excluding the unselected word lines WLs-1 and WLs+1, can act as the cell current I flowing through the selected memory cell. CELL The resistance factor is [value missing]. Therefore, as the temperature increases, the second through voltage Vpass2 can decrease.

[0120] Therefore, as Figure 10B As shown, with Figure 8B Compared to the previous implementation, the cell current I in the case of high temperature in the semiconductor memory device 100 can be further reduced. CELL Cell current I under low temperature conditions of semiconductor memory device 100 CELL The difference lies between them. Specifically, the cell current I in semiconductor memory devices at high temperatures occurs not only at gate voltages equal to or greater than a specific voltage level, but also at gate voltages less than a specific voltage level. CELL Cell current I under low temperature conditions of semiconductor memory devices CELL The differences between them can be minimized.

[0121] Figure 11A and Figure 11B This is a graph illustrating the relationship between voltage and temperature used in a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0122] Reference Figure 11A, illustrates magnitudes of the first pass voltage Vpass1 and the second pass voltage Vpass2 applied to unselected word lines WL1 to WLs-1 and WLs+1 to WLn in dependence on a temperature of the semiconductor memory device 100 during a read operation of the semiconductor memory device according to an embodiment of the present disclosure. As described above with reference to Figure 9 , the first pass voltage Vpass1 is applied to the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, and the second pass voltage Vpass2 is applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. According to an embodiment of the present disclosure, the first pass voltage Vpass1 having a constant voltage level regardless of a change in the temperature of the semiconductor memory device 100 can be applied to the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs. In the case of the second pass voltage Vpass2, the magnitude of the second pass voltage Vpass2 can decrease as the temperature increases, and the magnitude of the second pass voltage Vpass2 can increase as the temperature decreases, similarly to the embodiment of Figure 10A .

[0123] Referring to Figure 11B , illustrates magnitudes of the first pass voltage Vpass1 and the second pass voltage Vpass2 applied to unselected word lines WL1 to WLs-1 and WLs+1 to WLn in dependence on a temperature of the semiconductor memory device 100 during a read operation of the semiconductor memory device according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the magnitudes of both the first pass voltage Vpass1 and the second pass voltage Vpass2 decrease as the temperature increases, and the magnitudes of both the first pass voltage Vpass1 and the second pass voltage Vpass2 increase as the temperature decreases. However, the slopes of the first pass voltage Vpass1 and the second pass voltage Vpass2 in dependence on the change in the temperature can be different from each other. For example, as shown in Figure 11B , the absolute value of the slope of the second pass voltage Vpass2 in dependence on the change in the temperature can be greater than the absolute value of the slope of the first pass voltage Vpass1 in dependence on the change in the temperature. Figure 11B

[0124] Figure 12 is a graph describing a read operation of a semiconductor memory device according to an embodiment of the present disclosure. Referring to Figure 12 , illustrates a cell string CS included in a memory cell array of the semiconductor memory device. Figure 12 The cell string CS can be one of cell strings CS11 to CS1m and CS21 to CS2m shown in Figure 3 . Alternatively,​Figure 12 The unit string CS can be Figure 4 The shown unit strings are one of the unit strings CS11′ to CS1m′ and CS21′ to CS2m′. Alternatively, Figure 12 The unit string CS can be Figure 5 The shown unit string is one of the unit strings CS1 to CSm. Figure 12 The diagram illustrates the source select line SSL, multiple word lines WL1 to WLn, and drain select line DSL connected to the cell string CS, while the illustrations of the common source line and bit lines are omitted.

[0125] During a read operation of the semiconductor memory device, a read voltage Vread is applied to the selected word line WLs among the word lines WL1 to WLn connected to the cell string CS. Simultaneously, a third pass voltage Vpass3 can be applied to the word line WLs+1 among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, which is adjacent to the selected word line WLs in the direction of the drain select line DSL. Furthermore, a fourth pass voltage Vpass4 can be applied to the word line WLs-1 among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, which is adjacent to the selected word line WLs in the direction of the source select line SSL. A second pass voltage Vpass2 can be applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, excluding the word lines WLs-1 and WLs+1 which are adjacent to the selected word line WLs. During a read operation, information is read regarding whether the threshold voltage of each memory cell connected to the selected word line WLs is greater than the read voltage Vread, based on the read voltage Vread applied to the selected word line WLs. During a read operation, the second pass voltage Vpass2 to the fourth pass voltage Vpass4 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn can be voltages greater than the threshold voltage of all memory cells connected to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. The source select line voltage VSSL applied to the source select line SSL during a read operation can be the voltage used to turn on the source select transistor. Furthermore, the drain select line voltage VDSL applied to the drain select line DSL during a read operation can be a voltage used to turn on the drain select transistor. Although not shown, whenever a word line WLs is selected for each read operation, control logic 140 can group the unselected word lines WL1 to WLs-1 and WLs+1 to WLn into a group to be applied with adjacent pass voltages Vpass3 and Vpass4, and a group to be applied with non-adjacent pass voltage Vpass2.

[0126] In the semiconductor memory device 100 according to the embodiment of the present disclosure, the third pass voltage Vpass3 applied to the word line WLs+1 among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, the fourth pass voltage Vpass4 applied to the word line WLs-1 among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, and the second pass voltage Vpass2 applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn can be used separately. According to the embodiment of the present disclosure, the relationship between the pass voltages used in the read operation of the semiconductor memory device and the temperature will be described below with reference to Figures 13A to 13C A method of controlling the second pass voltage Vpass2 to the fourth pass voltage Vpass4 depending on the temperature of the semiconductor memory device 100 is described.

[0127] Figures 13A to 13C is a graph illustrating the relationship between the pass voltage used in the read operation of the semiconductor memory device and the temperature according to the embodiment of the present disclosure.

[0128] Referring to Figure 13A , the amplitude of the second pass voltage Vpass2 to the fourth pass voltage Vpass4 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn depending on the temperature of the semiconductor memory device 100 during the read operation of the semiconductor memory device according to the embodiment of the present disclosure is illustrated. As described above with reference to Figure 12 , the third pass voltage Vpass3 can be applied to the word line WLs+1 among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn disposed adjacent to the selected word line WLs in the direction of the drain select line DSL, and the fourth pass voltage Vpass4 can be applied to the word line WLs-1 among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn disposed adjacent to the selected word line WLs in the direction of the source select line SSL. Meanwhile, the second pass voltage Vpass2 can be applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. According to the embodiment of the present disclosure, as the temperature of the semiconductor memory device 100 increases, the amplitude of the third pass voltage Vpass3 and the fourth pass voltage Vpass4 increases, and the amplitude of the second pass voltage Vpass2 decreases. Conversely, as the temperature decreases, the amplitude of the third pass voltage Vpass3 and the fourth pass voltage Vpass4 decreases, and the amplitude of the second pass voltage Vpass2 increases. However, the slopes of the third pass voltage Vpass3 and the fourth pass voltage Vpass4, which increase depending on the temperature of the semiconductor memory device 100, can be different from each other. In Figure 13AIn the embodiment of the present disclosure, the slope of the third pass voltage Vpass3 that increases in accordance with the temperature is greater than the slope of the fourth pass voltage Vpass4. However, this is merely an example, and an embodiment configured such that the slope of the third pass voltage Vpass3 that increases in accordance with the temperature is less than the slope of the fourth pass voltage Vpass4 can also be implemented.

[0129] Referring to Figure 13B , the magnitude of the second to fourth pass voltages Vpass2 to Vpass4 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn in accordance with the temperature of the semiconductor memory device 100 during a read operation of the semiconductor memory device according to the embodiment of the present disclosure is exemplified. Similar to the embodiment of Figure 13A , as the temperature of the semiconductor memory device 100 increases, the magnitude of the third pass voltage Vpass3 increases and the magnitude of the second pass voltage Vpass2 decreases. Conversely, as the temperature decreases, the magnitude of the third pass voltage Vpass3 decreases and the magnitude of the second pass voltage Vpass2 increases. However, unlike the embodiment of Figure 13A , the fourth pass voltage Vpass4 can have a constant voltage level regardless of temperature changes.

[0130] In the embodiment of the present disclosure, Figure 13B , although an embodiment configured such that the magnitude of the third pass voltage Vpass3 increases as the temperature increases and the fourth pass voltage Vpass4 has a constant voltage level regardless of temperature changes is exemplified, the present disclosure is not limited thereto. For example, an embodiment configured such that the magnitude of the fourth pass voltage Vpass4 increases as the temperature increases and the third pass voltage Vpass3 has a constant voltage level regardless of temperature changes can also be implemented.

[0131] Referring to Figure 13C , the magnitude of the second to fourth pass voltages Vpass2 to Vpass4 applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn in accordance with the temperature of the semiconductor memory device 100 during a read operation of the semiconductor memory device according to the embodiment of the present disclosure is exemplified. Similar to the embodiment of Figure 13A , as the temperature of the semiconductor memory device 100 increases, the magnitude of the third pass voltage Vpass3 increases and the magnitude of the second pass voltage Vpass2 decreases. Conversely, as the temperature decreases, the magnitude of the third pass voltage Vpass3 decreases and the magnitude of the second pass voltage Vpass2 increases. However, unlike the embodiment of Figure 13AThe magnitude of the fourth pass voltage Vpass4 can decrease as the temperature increases, depending on the embodiment. That is, the magnitude of both the second pass voltage Vpass2 and the fourth pass voltage Vpass4 decreases as the temperature increases, and the magnitude of both the second pass voltage Vpass2 and the fourth pass voltage Vpass4 increases as the temperature decreases. However, the slope of the voltage change depending on the temperature change can be different from each other between the second pass voltage Vpass2 and the fourth pass voltage Vpass4. The slope of the second pass voltage Vpass2 depending on the temperature change can be greater than the slope of the fourth pass voltage Vpass4 depending on the temperature change.

[0132] Referring to Figures 9 to 13C , an example is illustrated in which the same second pass voltage Vpass2 is applied to unselected word lines WL1 to WLs-2 and WLs+2 to WLn that are not adjacent to the selected word line WLs. However, the present disclosure is not limited thereto, and different pass voltages can be applied to unselected word lines WL1 to WLs-2 and WLs+2 to WLn that are not adjacent to the selected word line WLs.

[0133] Figure 14 is a diagram describing a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0134] Referring to Figure 14 , an example is illustrated in which a cell string CS included in a memory cell array of a semiconductor memory device. Figure 14 The cell string CS of Figure 3 may be one of cell strings CS11 to CS1m and CS21 to CS2m illustrated in Figure 14 . Alternatively, Figure 4 The cell string CS of Figure 14 may be one of cell strings CS1 to CSm illustrated in Figure 5 . In Figure 14 , a source select line SSL, a plurality of word lines WL1 to WLn, and a drain select line DSL coupled to the cell string CS are illustrated, and the illustration of a common source line and a bit line is omitted.

[0135] During a read operation of the semiconductor memory device, a read voltage Vread is applied to a selected word line WLs among the word lines WL1 to WLn coupled to the cell string CS. At the same time, a first pass voltage Vpass1 can be applied to word lines WLs-1 and WLs+1 among the unselected word lines WL1 to WLs-1 and WLs+1 disposed adjacent to the selected word line WLs.

[0136] The unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn that are not adjacent to the selected word line WLs can be divided into a plurality of groups WLGa, WLGb, WLGc, and WLGd. The 2a pass voltage Vpass2a can be applied to the unselected word lines WL1 to WLk belonging to a first group WLGa among the plurality of groups WLGa, WLGb, WLGc, and WLGd, and the 2b pass voltage Vpass2b can be applied to the unselected word lines WLk+1 to WLs-2 belonging to a second group WLGb among the plurality of groups WLGa, WLGb, WLGc, and WLGd. Further, the 2c pass voltage Vpass2c can be applied to the unselected word lines WLs+2 to WLp-1 belonging to a third group WLGc among the plurality of groups WLGa, WLGb, WLGc, and WLGd, and the 2d pass voltage Vpass2d can be applied to the unselected word lines WLp to WLn belonging to a fourth group WLGd among the plurality of groups WLGa, WLGb, WLGc, and WLGd. In Figure 14 In the embodiment in which the unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn that are not adjacent to the selected word line WLs are divided into the four groups WLGa, WLGb, WLGc, and WLGd, the present disclosure is not limited thereto, and the number of groups and the number of word lines included in each group can be selected in various ways depending on the situation.

[0137] In the present disclosure, the first pass voltage Vpass1 applied to the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs can be referred to as an "adjacent pass voltage", and the 2a pass voltage Vpass2a to the 2d pass voltage Vpass2d applied to the unselected word lines WL1 to WLs-2 and WLs+2 to WLn not disposed adjacent to the selected word line WLs can be referred to as a "non-adjacent pass voltage". Although not shown, every time the word line WLs is selected for each read operation, the control logic 140 can group the unselected word lines WL1 to WLs-1 and WLs+1 to WLn into a group to which the adjacent pass voltage Vpass1 is to be applied and groups WLGa to WLGd to which the non-adjacent pass voltages Vpass2a to Vpass2d are to be applied, respectively.

[0138] Figure 15 is a graph illustrating the operating characteristics of a memory cell depending on the temperature of the semiconductor memory device 100 when the pass voltage using Figure 14 is used.

[0139] Referring to Figure 15, it is illustrated that the amplitudes of the first pass voltage Vpass1 and the 2a-th pass voltage Vpass2a to the 2d-th pass voltage Vpass2d applied to the unselected word lines WL1 to WLs-1 and WLs+1 to WLn depend on the temperature of the semiconductor memory device 100 during a read operation of the semiconductor memory device according to the embodiment of the present disclosure. As described above with reference to Figure 14 , the first pass voltage Vpass1 can be applied to the word lines WLs-1 and WLs+1 disposed adjacent to the selected word line WLs among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn, and the 2a-th pass voltage Vpass2a to the 2d-th pass voltage Vpass2d can be applied to the remaining unselected word lines WL1 to WLs-2 and WLs+2 to WLn among the unselected word lines WL1 to WLs-1 and WLs+1 to WLn. According to the embodiment of the present disclosure, as the temperature of the semiconductor memory device 100 increases, the amplitude of the first pass voltage Vpass1 increases and the amplitudes of the 2a-th pass voltage Vpass2a to the 2d-th pass voltage Vpass2d decrease. Conversely, as the temperature decreases, the amplitude of the first pass voltage Vpass1 decreases and the amplitudes of the 2a-th pass voltage Vpass2a to the 2d-th pass voltage Vpass2d increase. In Figure 15 , although it is illustrated that the 2a-th pass voltage Vpass2a has the largest amplitude and the 2d-th pass voltage Vpass2d has the smallest amplitude among the 2a-th pass voltage Vpass2a to the 2d-th pass voltage Vpass2d, this is merely an example, and the present disclosure is not limited thereto. For example, unlike the embodiment shown in Figure 15 , the amplitude of the 2d-th pass voltage Vpass2d can be the largest and the amplitude of the 2a-th pass voltage Vpass2a can be the smallest. The respective relative amplitudes of the 2a-th pass voltage Vpass2a to the 2d-th pass voltage Vpass2d can be changed in various ways as needed.

[0140] Figure 16 is a block diagram of a memory system 1000 including the semiconductor memory device 100. Figure 1

[0141] Referring to Figure 16 , the memory system 1000 can include the semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 can be the semiconductor memory device described with reference to Figure 1 . Hereinafter, repetitive descriptions will be omitted.

[0142] ​The memory controller 1100 is coupled to the host Host and the semiconductor memory device 100. The memory controller 1100 can access the semiconductor memory device 100 in response to a request from the host Host. For example, the memory controller 1100 can control a read operation, a write operation, an erase operation, and a background operation of the semiconductor memory device 100. The memory controller 1100 can provide an interface between the semiconductor memory device 100 and the host Host. The memory controller 1100 can execute a firmware for controlling the semiconductor memory device 100.

[0143] The memory controller 1100 includes a random access memory (RAM) 1110, a processor 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 is used as at least one of a working memory of the processor 1120, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host. The processor 1120 can control the overall operation of the memory controller 1100. In addition, the memory controller 1100 can temporarily store program data provided from the host Host during a write operation.

[0144] The host interface 1130 includes a protocol for performing data exchange between the host Host and the memory controller 1100. In an embodiment, the memory controller 1100 can communicate with the host Host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol.

[0145] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface can include a NAND interface or a NOR interface.

[0146] The error correction block 1150 can detect and correct errors in data received from the semiconductor memory device 100 using an error correction code (ECC). In an example embodiment, the error correction block can be provided as an element of the memory controller 1100.

[0147] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In an embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a CompactFlash (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, or micro-SD), an SD card (SD, mini-SD, micro-SD, or SDHC), or a Universal Flash Storage (UFS).

[0148] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid state drive (SSD). The SSD includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as the SSD, the operation speed of a host Host coupled to the memory system 1000 can be significantly improved.

[0149] In an embodiment, the memory system 1000 can be provided as one of various elements of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting / receiving information in a wireless environment, one of various electronic devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, a radio frequency identification device (RFID), or one of various elements for forming a computing system.

[0150] In implementations, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in types such as: package stack (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), wafer-in-package, wafer-in-wafer, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stack-up package (WSP).

[0151] Figure 17 This is an example Figure 16 A block diagram illustrating an application example of a memory system.

[0152] Reference Figure 17 The memory system 2000 may include a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 may include a plurality of semiconductor memory chips. The semiconductor memory chips are divided into multiple groups.

[0153] exist Figure 17 The diagram illustrates multiple groups communicating with the memory controller 2200 via channels CH1 to CHk. Each semiconductor memory chip can communicate with a reference... Figure 1 The semiconductor memory device 100 described is configured and operated in the same manner.

[0154] Each group can communicate with the memory controller 2200 through a common channel. The memory controller 2200 may have a reference... Figure 16 The memory controller 1100 described has the same configuration and can control multiple memory chips of the semiconductor memory device 2100 through multiple channels CH1 to CHk.

[0155] Figure 18 This illustrates the example including references. Figure 17 A block diagram of the computing system describing the memory system.

[0156] The computing system 3000 includes a central processing unit (CPU) 3100, RAM 3200, user interface 3300, power supply 3400, system bus 3500 and memory system 2000.

[0157] The memory system 2000 is electrically coupled to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 can be stored in the memory system 2000.

[0158] In Figure 18 , the semiconductor memory device 2100 is illustrated as being coupled to the system bus 3500 through the memory controller 2200. However, the semiconductor memory device 2100 can be directly coupled to the system bus 3500. Here, the functions of the memory controller 2200 can be performed by the CPU 3100 and the RAM 3200.

[0159] In Figure 18 , the memory system 2000 described with reference to Figure 17 is illustrated. However, the memory system 1000 described with reference to Figure 16 may be used instead of the memory system 2000. In an embodiment, the computing system 3000 can include the memory systems 1000 and 2000 described with reference to Figure 16 and Figure 17 .

[0160] The present disclosure can provide a semiconductor memory device having improved read performance depending on temperature variation.

[0161] Example embodiments have been disclosed herein and, although a particular terminology is employed, such terminology is used in a generic and descriptive sense only and not for purposes of limitation. In some instances, it will be apparent that features, characteristics, and / or elements described with respect to a particular embodiment can be used, alone or in combination with one another, with or without the incorporation of additional embodiments, unless specifically stated to the contrary. As such, one of ordinary skill in the art will recognize that the disclosure is not limited to the specific embodiments described and illustrated herein-will include any modifications of the described and illustrated embodiments that come within the scope of the following claims and their equivalents.

[0162] Cross Reference to Related Applications

[0163] This application claims priority to Korean Patent Application No. 10-2020-0113413, filed on September 4, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: an array of memory cells, the array of memory cells comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells; a peripheral circuit, the peripheral circuit performing a read operation on the plurality of memory cells; and control logic, the control logic controlling the read operation of the peripheral circuit, wherein, during the read operation, the control logic controls the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the plurality of memory cells of a selected memory block, a first pass voltage is applied to an unselected word line among the plurality of word lines that is disposed adjacent to the selected word line, and a second pass voltage is applied to an unselected word line among the plurality of word lines that is not disposed adjacent to the selected word line, and wherein the peripheral circuit further adjusts a magnitude of the first pass voltage or a magnitude of the second pass voltage based on a temperature of the semiconductor memory device, wherein the peripheral circuit comprises: a voltage generator, the voltage generator generating the read voltage, the first pass voltage, and the second pass voltage; an address decoder, the address decoder selecting at least one memory block based on a decoded block address, the read voltage, the first pass voltage, and the second pass voltage being communicated to the selected word line of the selected memory block, the unselected word line of the selected memory block that is disposed adjacent to the selected word line, and the unselected word line of the selected memory block that is not disposed adjacent to the selected word line, respectively; a read-write circuit, the read-write circuit sensing a threshold voltage of a memory cell coupled to the selected word line; and a temperature sensor, the temperature sensor sensing the temperature and generating a temperature code based on the temperature, wherein the voltage generator further adjusts the magnitude of the first pass voltage or the magnitude of the second pass voltage based on the temperature code.

2. A semiconductor memory device, the semiconductor memory device comprising: an array of memory cells, the array of memory cells comprising a plurality of memory cells; a peripheral circuit, the peripheral circuit performing a read operation on the plurality of memory cells; and control logic, the control logic controlling the read operation of the peripheral circuit, wherein, during the read operation, the control logic controls the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the plurality of memory cells, a first pass voltage is applied to an unselected word line among the plurality of word lines that is disposed adjacent to the selected word line, and a second pass voltage is applied to an unselected word line among the plurality of word lines that is not disposed adjacent to the selected word line, wherein the peripheral circuit further adjusts a magnitude of the first pass voltage or a magnitude of the second pass voltage based on a temperature of the semiconductor memory device, and wherein, as the temperature increases, the peripheral circuit decreases the magnitude of the second pass voltage. As the temperature increases, the peripheral circuit increases the magnitude of the first pass voltage. The peripheral circuit keeps the first pass voltage constant regardless of the temperature.

3. The semiconductor memory device of claim 2, wherein, The peripheral circuit keeps the second pass voltage constant regardless of the temperature.

4. The semiconductor memory device according to claim 2, wherein, ​ 5. The semiconductor memory device of claim 2, wherein, As the temperature increases, the peripheral circuit decreases the magnitude of the first pass voltage.

6. The semiconductor memory device of claim 5, wherein, The peripheral circuit adjusts the magnitude of the first pass voltage and the magnitude of the second pass voltage such that the absolute value of the slope of the second pass voltage as a function of the increase in the temperature is greater than the absolute value of the slope of the first pass voltage as a function of the increase.

7. A semiconductor memory device, comprising: an array of memory cells including a plurality of memory cells; a peripheral circuit that performs a read operation on the plurality of memory cells; and control logic that controls the read operation of the peripheral circuit, wherein, during the read operation, the control logic controls the peripheral circuit such that a read voltage is applied to a selected word line among a plurality of word lines coupled to the plurality of memory cells, and such that a first pass voltage is applied to an unselected word line among the plurality of word lines that is disposed adjacent to the selected word line in a direction of a drain select line, a second pass voltage is applied to an unselected word line among the plurality of word lines that is disposed adjacent to the selected word line in a direction of a source select line, and a third pass voltage is applied to an unselected word line among the plurality of word lines that is not disposed adjacent to the selected word line, and wherein the peripheral circuit further adjusts a magnitude of at least one of the first pass voltage, the second pass voltage, and the third pass voltage based on a temperature of the semiconductor memory device.

8. The semiconductor memory device of claim 7, wherein, The peripheral circuit comprises: a voltage generator that generates the read voltage, the first pass voltage, the second pass voltage, and the third pass voltage; an address decoder that transfers the read voltage and the first pass voltage, the second pass voltage, and the third pass voltage to the selected word line, the unselected word line disposed adjacent to the selected word line in the direction of the drain select line, the unselected word line disposed adjacent to the selected word line in the direction of the source select line, and the unselected word line that is not disposed adjacent to the selected word line, respectively; a read / write circuit that senses a threshold voltage of a memory cell coupled to the selected word line; and a temperature sensor that senses the temperature and generates a temperature code based on the temperature, wherein the voltage generator further adjusts the magnitude of at least one of the first pass voltage to the third pass voltage based on the temperature code.

9. The semiconductor memory device of claim 7, wherein, As the temperature increases, the peripheral circuit decreases the magnitude of the third pass voltage.

10. The semiconductor memory device of claim 9, wherein, As the temperature increases, the peripheral circuit increases the magnitude of the first pass voltage and the second pass voltage.

11. The semiconductor memory device of claim 10, wherein, The peripheral circuit adjusts the magnitude of the first pass voltage and the magnitude of the second pass voltage such that the slope of the first pass voltage as a function of the increase in the temperature is greater than the slope of the second pass voltage as a function of the increase.

12. The semiconductor memory device of claim 10, wherein, The peripheral circuit adjusts the magnitude of the first pass voltage and the magnitude of the second pass voltage such that a slope of the second pass voltage as a function of an increase in the temperature is greater than a slope of the first pass voltage as a function of the increase.

13. The semiconductor memory device of claim 9, wherein As the temperature increases, the peripheral circuit increases the magnitude of the first pass voltage, and wherein the peripheral circuit keeps the second pass voltage constant regardless of the temperature.

14. The semiconductor memory device of claim 9, wherein As the temperature increases, the peripheral circuit increases the magnitude of the second pass voltage, and wherein the peripheral circuit keeps the first pass voltage constant regardless of the temperature.

15. The semiconductor memory device of claim 9, wherein, As the temperature increases, the peripheral circuit increases the magnitude of the first pass voltage and decreases the magnitude of the second pass voltage.

16. The semiconductor memory device of claim 15, wherein, The peripheral circuit adjusts the magnitude of the second pass voltage and the magnitude of the third pass voltage such that an absolute value of a slope of the third pass voltage as a function of an increase in the temperature is greater than an absolute value of a slope of the second pass voltage as a function of the increase.

17. The semiconductor memory device of claim 9, wherein, As the temperature increases, the peripheral circuit decreases the magnitude of the first pass voltage and increases the magnitude of the second pass voltage.

18. The semiconductor memory device of claim 17, wherein, The peripheral circuit adjusts the magnitude of the first pass voltage and the magnitude of the third pass voltage such that an absolute value of a slope of the third pass voltage as a function of an increase in the temperature is greater than an absolute value of a slope of the first pass voltage as a function of the increase.

19. An operating method of a semiconductor memory device including a memory cell string of memory cells, the operating method comprising the steps of: grouping non-target word lines into a near-end group and a far-end group each including one or more word lines, the near-end group being disposed closer to a target word line than the far-end group, and the target word line and the non-target word lines being respectively coupled to the memory cells; applying an operating voltage to the target word line; applying one or more near-end voltages to the near-end group, respectively; and applying one or more far-end voltages to the far-end group, respectively, wherein the step of applying the far-end voltages includes changing the far-end voltages in inverse proportion to a temperature of the semiconductor memory device, and wherein the step of applying the near-end voltages includes changing at least one of the near-end voltages in direct proportion to the temperature.

20. The method of operating according to claim 19, wherein, The step of applying the near-end voltages further includes changing another one of the near-end voltages in a different direct proportion to the temperature.

21. The method of operating of claim 19, wherein, The step of applying the near-end voltages further includes keeping another one of the near-end voltages constant with respect to the temperature.

22. The operating method of claim 19, wherein, The step of applying the near-end voltages further includes changing another one of the near-end voltages in inverse proportion to the temperature, and wherein a gradient of the far-end voltages during the changing of the far-end voltages is greater than a gradient of the other near-end voltage during the changing of the other near-end voltage.

23. A method of operating a semiconductor memory device including strings of memory cells respectively coupled to memory cells of word lines, the method comprising the steps of: grouping remaining word lines other than a target word line into a near group and a far group each including one or more word lines, the near group being disposed closer to the target word line than the far group; applying an operating voltage to the target word line; applying one or more near voltages to the near group, respectively; and applying one or more far voltages to the far group, respectively, wherein the step of applying the far voltages includes varying the far voltages in inverse proportion to a temperature of the semiconductor memory device, and wherein the step of applying the near voltages includes holding at least one of the near voltages constant with respect to the temperature.

24. The method of operating of claim 23, wherein, The step of applying the near voltages further includes varying another of the near voltages in direct proportion to the temperature.

25. A method of operating a semiconductor memory device including strings of memory cells respectively coupled to memory cells of word lines, the method comprising the steps of: grouping remaining word lines other than a target word line into a near group and a far group each including one or more word lines, the near group being disposed closer to the target word line than the far group; applying an operating voltage to the target word line; applying one or more near voltages to the near group, respectively; and applying one or more far voltages to the far group, respectively, wherein the step of applying the far voltages includes varying the far voltages in inverse proportion to a temperature of the semiconductor memory device, wherein the step of applying the near voltages includes varying at least one of the near voltages in inverse proportion to the temperature, and wherein a gradient of the far voltages during variation of the far voltages is greater than a gradient of the near voltages during variation of the near voltages.

26. The method of operating of claim 25, wherein, The step of applying the near voltages further includes varying another of the near voltages in direct proportion to the temperature.

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