Memory, memory control method and system

Abstract

Disclosed are a memory, a memory control method, and a memory control system. The memory includes: a first circuit set, including a memory cell array, and a first control logic circuit that operates the memory cell array based on a received external instruction; and a second circuit set, including a second control logic circuit and a power manager. In response to a low-power state instruction, the power manager disables the first circuit set, and the memory enters a low-power state; in response to receiving a first predetermined combination signal of a chip selection signal and an input signal of a first predetermined interface, the second control logic circuit causes the power manager to power the first circuit set, causing the memory to enter a standby state from the low-power state. By using an additional logic control circuit, a low-power state that can power off all irrelevant circuits can be exited under the control of the circuit through, for example, a combination signal of the CS and CLK interfaces, thereby further reducing the power consumption of the memory chip while ensuring that the low-power state is correctly exited.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to a memory, a memory control method, and a corresponding system. Background Art

[0002] Flash memory, with its high storage density, high reliability, and low power consumption, is increasingly being used today. Flash memory includes NAND flash memory and NOR flash memory. NOR flash memory, also known as code-based memory, is typically used with microcontrollers and supports in-chip execution (XIP, eXecute In Place). It has a wide range of applications in automotive electronics, wearable devices, smart home appliances, home medical devices, and other areas. NAND flash memory is widely used in various large-capacity devices such as memory cards, USB flash drives, SSDs, and eMMCs. With the improvement of device performance and integration, as well as the characteristics of distributed applications, battery replacement or frequent charging can bring many inconveniences. Therefore, how to extend battery life and reduce device power consumption is a major challenge currently facing flash memory applications. Summary of the Invention

[0003] The present disclosure addresses a technical problem by providing a memory, memory control method, and memory control system. The memory of the present invention includes an additional logic control circuit that, under the control of this circuit, can exit a low-power state that powers off all unrelated circuits by, for example, combining signals from the CS and CLK interfaces. This further reduces the power consumption of the memory chip while ensuring that the low-power state is correctly exited.

[0004] According to the first aspect of the present disclosure, a memory is provided, comprising: a first circuit set, including a memory cell array, and a first control logic circuit for operating the memory cell array based on a received external instruction; and a second circuit set, including a second control logic circuit and a power manager, wherein, in response to an instruction to enter a low power state, the power manager disables the first circuit set, and the memory enters a low power state, and in response to receiving a first predetermined combination signal of a chip selection signal and an input signal of a first predetermined interface, the second control logic circuit causes the power manager to power the first circuit set, so that the memory enters a standby state from the low power state.

[0005] Optionally, the first predetermined interface is a clock interface, and in response to receiving the first predetermined combination signal of a chip selection signal and a clock signal with a predetermined number of triggers, the second control logic circuit enables the power manager to power the first circuit set.

[0006] Optionally, the first predetermined interface includes at least one of the following: a hold interface; a write protection interface; a clock interface; a data input interface; and a data output interface.

[0007] Optionally, the memory includes a power port, the power port is connected to an external power source, and the second circuit set is powered by the external power source.

[0008] Optionally, the second circuit set includes a chip selection signal buffer and a first predetermined interface signal buffer.

[0009] Optionally, the first circuit set includes an instruction decoder, and in response to the instruction decoder receiving an instruction to enter a low power consumption state, the power manager disables the first circuit set, and the memory enters a low power consumption state from a standby state.

[0010] Optionally, the second circuit set further includes a status register, wherein the status register is in an enabled state in a standby state and a low power consumption state.

[0011] Optionally, the memory also includes a third circuit set, which includes an instruction decoder, and the second circuit set also includes a status register and an ID register. In response to a combination signal of a chip selection signal and an input signal of a second predetermined interface, the second control logic circuit enables the power manager to power the third circuit set while keeping the first circuit set disabled, so that the memory enters a second low power state from the low power state.

[0012] According to a second aspect of the present disclosure, a memory control method is provided, wherein the memory includes a first circuit set and a second circuit set, the first circuit set including a memory cell array, and a first control logic circuit for operating the memory cell array based on a received external instruction, the second circuit set including a second control logic circuit and a power manager, the method comprising: in response to an instruction to enter a low power state, the power manager disabling the first circuit set so that the memory enters a low power state; and in response to a first predetermined combination signal of a chip selection signal and a predetermined interface input signal, the second control logic circuit causing the power manager to power the first circuit set so that the memory enters a standby state from the low power state.

[0013] According to a third aspect of the present disclosure, a system is provided, comprising: a host; an interface bus; and the memory as described in the first aspect, which is coupled to the host via connection between the input / output interface and the interface bus.

[0014] The present invention uses a low-power exit mechanism of the interface combination signal and a dedicated low-power logic control circuit to shut down more circuits in a low-power state and safely exit the low-power state, thereby further reducing memory power consumption and improving robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0016] Figure 1 A simplified schematic diagram of a system incorporating a memory according to one embodiment of the present invention is shown.

[0017] Figure 2 An example of a top view of an 8-pin memory chip is shown.

[0018] Figure 3 A schematic diagram showing the composition of a memory according to an embodiment of the present invention is shown.

[0019] Figure 4 FIG. 4 shows a schematic diagram of memory state switching according to an embodiment of the present invention.

[0020] Figure 5 FIG. 4 shows a timing diagram of entering a low power consumption state according to an embodiment of the present invention.

[0021] Figure 6 FIG. 4 shows a timing diagram of leaving a low power consumption state according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0023] Various embodiments will be described in more detail with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals represent like parts throughout the various figures and embodiments of the present invention.

[0024] Note that the drawings are simplified schematic diagrams and are not necessarily drawn to scale. In some cases, parts of the drawings may have been exaggerated to more clearly illustrate certain features of the illustrated embodiments.

[0025] It is further noted that in the following description, specific details are set forth to facilitate understanding of the present invention, however, the present invention may be practiced without some of these specific details. In addition, it is noted that well-known structures and / or processes may be described only briefly or not at all to avoid obscuring the present disclosure with unnecessary well-known details.

[0026] It should also be noted that in some cases, it is obvious to those skilled in the relevant art that, unless otherwise specifically stated, elements (also referred to as features) described in connection with one embodiment can be used alone or in combination with other elements of another embodiment. In addition, the use of "first," "second," and even "third" below is intended to distinguish different objects of the same category for ease of description, and does not imply importance or order of precedence.

[0027] The various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 Describe the application environment of the present invention.

[0028] Figure 1 FIG2 is a simplified diagram of a system including a nonvolatile memory according to an embodiment of the present invention. The system 10 may be implemented as an electronic device, and the device 10 may include a host 200 and a memory 300 as shown in the figure, and communicate via a bus 100 .

[0029] Here, the host 200 refers to the part that realizes the key functions of the device 10, that is, the main part of the device 10, and the host 200 (or the device 10) can be any appropriate electronic device. In one embodiment, the device 10 can be an electronic device, including but not limited to portable electronic devices such as mobile phones, tablets, wearable devices (such as TWS headphones) and laptop computers, or non-portable electronic devices such as desktop computers, game consoles, televisions, set-top boxes and projectors, and even industrial Internet of Things devices such as independently set sensors. In this case, the memory 300 can be a device that provides storage services for independent electronic devices.

[0030] In other embodiments, the device 10 may also be an electronic device with relatively independent functions (these electronic devices are usually key components of electronic devices), such as independently sold smart screens, main control chips, camera components, etc. These electronic devices usually need to be assembled, for example, a smart screen must be assembled into a mobile phone before it can provide services to consumers (e.g., users who purchase mobile phones). In this case, the memory 300 can be a device that provides the necessary storage services for the electronic device.

[0031] Here, the host 200 may be implemented as or include a microcontroller, a microprocessor, an application-specific integrated circuit (ASIC), or an application-specific standard product (ASSP), and is coupled to a memory 300 as a slave device via a bus 100 as shown. Here, the bus 100 is shown as a bidirectional arrow connected between the host 200 and the memory 300 to indicate bidirectional information transmission between the host 200 and the memory 300 via the main line.

[0032] In one embodiment, the bus 100 can be implemented as an interface bus, such as a serial peripheral interface (SPI) bus, and can actually include multiple connection lines to implement the transmission of instructions, addresses, and data, so that the code stored in the memory 300 can be read and executed, and erased and written when necessary, such as for firmware over-the-air upgrades.

[0033] The bus 100 includes a plurality of connection lines that can be connected to interfaces provided by both the host 200 and the memory 300 , and the host 200 and the memory 300 can each include pins for performing the above connection.

[0034] In a preferred embodiment, the memory 300 can be implemented as a flash memory device with an SPI interface, particularly NOR flash memory and NAND flash memory, enabling sequential data access via a serial interface (pins) and suitable for a variety of applications such as voice, image, program code, and data storage. Specifically, the memory 300 can be enabled by a chip strobe signal received on a chip strobe (CS) pin (e.g., a specified valid "asserted" signal), and data access can be achieved via a data input (SI) pin, a data output (SO) pin, and a clock (CLK) pin. Accordingly, the bus 100 may include at least a data input line, a data output line, a clock line, and a chip strobe line. The data input line transmits data signals generated by the host 200 and received by the memory 300, such as instructions and address sequences. The data output line transmits signals generated by the memory 300 and received by the host 200, such as data read from the memory 300, such as code executable on the host 200. The clock line is used to send the clock signal generated by the host 200 to the memory 300, thereby achieving synchronous data transmission between the two parties. When data transmission is required between the host 200 and the memory 300, the chip strobe signal on the chip strobe line is set to an active level, such as a low level. After the data transmission is completed, the chip strobe signal on the chip strobe line is set to an inactive level, such as a high level. It should be understood that the bus 100 can also realize the connection between the host 200 and other slave or peripheral devices, in which case other chip strobe lines will be provided for these devices.

[0035] In addition to the chip select (CS) pin, data input (SI) pin, data output (SO) pin, and clock (CLK) pin described above, in actual operation, the memory 300 usually also needs to set other pins to implement basic (or enhanced) memory functions.

[0036] Figure 2 An example of a top view of an 8-pin memory chip is shown. As shown in the figure, the memory chip is a SOP package chip and has 8 pins. Among them, pin 1, pin 5, pin 2 and pin 6 correspond to the chip enable (CS) pin, data input (SI) pin, data output (SO) pin and clock (CLK) pin as described above, respectively. Pin 1 is shown as "CS#", where "#" is used to indicate that the signal is valid at a low level. Further, pin 6 is shown as "SCLK", where the "S" before "CLK" is used to indicate that the signal is a system clock from an outside, so as to distinguish it from the "internal clock" inside the memory.

[0037] In order to operate normally, the memory 300 may include a power interface for receiving an external power source, such as Figure 2 Pin 8 shown is a pin for receiving an external voltage VCC (e.g., a first voltage). The pin obtains power supply from a power supply device of a system (e.g., electronic device 10). Furthermore, the memory 300 may also include a pin connected to the system ground, such as pin 4 for grounding and providing a ground voltage VSS.

[0038] The various pins of memory 300 can typically operate directly at the external voltage VCC, while the internal circuitry of memory 300, such as the memory array and its logic control circuitry, can operate at the memory's operating voltage VDD. In various embodiments, the external voltage VCC can be the same as or different from the memory's operating voltage VDD. When VCC and VDD are the same, the power manager in the memory can simply be used to power various components based on different states. However, when VDD and VCC are different (typically, VDD is lower than VCC), the power manager is required to perform voltage conversion to provide the operating voltage VDD for the components in the memory.

[0039] Furthermore, the memory chip may also include pin 3, i.e., a write-protect pin WP. Similar to the chip select signal, the "#" in "WP#" shown here also indicates that this signal is active low. When the WP# signal goes low, the memory 300 may enter a hardware-protected state, for example, and prevent rewriting of the status register.

[0040] Furthermore, the memory chip may also include pin 7, or hold pin HOLD. Similar to the chip select signal, the "#" in "HOLD#" is also used to indicate that the signal is active low. When the HOLD# signal goes low, the memory 300 halts any serial communication, but does not stop ongoing programming or erasing operations, or operations targeting write-state memory.

[0041] Among the above 8 pins, the 6 pins except VCC and VSS, namely SI pin, SO pin, CLK pin, CS pin, WP pin and HOLD pin, can be regarded as input and output interfaces connected to the outside, and correspond to data input interface, data output interface, clock interface, chip strobe interface, write protection interface and hold interface respectively. These interfaces can be used separately. Figure 1 The bus 100 shown, in particular the SPI bus, includes data input lines, data output lines, clock lines, chip select lines, write protection lines and hold lines to implement memory operations under host control, such as data reading, erasing or writing operations involving a memory cell array.

[0042] It is understood that although the SI pin, SO pin, CLK pin, CS pin, WP pin, and HOLD pin are collectively referred to as input and output interfaces, in actual operation, the SI pin, CLK pin, CS pin, WP pin, and HOLD pin can be designated to obtain external signals; the SO pin is designated to output data to the outside, such as program code read from the memory 300, or status signals stored in the internal registers of the memory 300. Furthermore, the SI pin, CLK pin, CS pin, WP pin, and HOLD pin are each used to obtain signals of different properties from the outside. Specifically, the instruction sent by the host 200 to the memory 300 can be an operator, which includes multiple bits (for example, 8 bits), and the SI pin sequentially obtains the operator. The instructions obtained by the SI pin cannot usually be used directly to control the memory, but need to be decoded by a decoding device (for example, by an instruction decoder) to be converted into recognizable control instructions within the memory. The CLK pin is used to receive the host's clock signal (e.g., a clock pulse of a specific frequency) to facilitate synchronous data transmission. For example, on the rising edge of the clock signal, host 200 sends data and memory 300 receives data. The CS pin receives the chip select signal from host 200. The chip select signal can be a select pulse or an active level that lasts for a predetermined period of time (e.g., when the chip select signal is low, memory 300 can receive clock and data from host 200; when the chip select signal is high, memory 300 ignores the clock and data on the clock and data input lines). The chip select signal can often be used to modify the internal operation of the memory directly. For example, it is often necessary to have the CS signal active and accompanied by an external clock signal received on the CLK pin in order to receive instructions transmitted on the SI pin.

[0043] Furthermore, in different data transmission modes, some or all of the SI pin, SO pin, CLK pin, CS pin, WP pin and HOLD pin can be reused as IO pins. The SI pin, SO pin, WP pin and HOLD pin can be used as IO pins in the "QuadSPI" mode of the memory chip. Figure 2 The IO0 to IO3 pins shown in brackets thereby enable the memory chip to transmit and receive data at four times the rate of the normal mode.

[0044] In addition, although Figure 2The memory chip shown is an SOP package chip with 8 pins, but it should be understood that the principles of the present invention are equally applicable to memory chips of other package types, such as SON and FBGA packaged chips, and the host 200 can also be connected to the corresponding pad terminals or solder microballs of these chips through the bus 100. The interfaces of these chips (e.g., pad terminals or solder microballs) can also be regarded as pins of the memory chip. In other words, the present invention does not limit the interface form of the memory chip.

[0045] With the further miniaturization of portable devices and wearable devices, as well as the prevalence of distributed devices such as those used in IoT applications, it is expected that memory can further reduce power consumption. Since memory, such as NOR flash memory, typically stores program code for execution by the host, and this program code is read externally, such as the built-in RAM of the host 200 or the independent RAM of the system 10, the memory does not need to be continuously accessed. To this end, the memory can be set to a lower power consumption state, and in these low power consumption states, power to various components in the memory can be disabled.

[0046] The present invention thus provides a memory device including an additional logic control circuit (described below as a "second logic control circuit"). Under the control of this second logic control circuit, a low-power state, which powers down all unrelated circuits, can be exited through a combination of interface signals, such as a combination of signals from the CS and CLK pins. This further reduces the power consumption of the memory chip while ensuring that the low-power state is exited correctly.

[0047] Figure 3 Schematic diagram of the composition of a memory according to one embodiment of the present invention. Memory 300 includes an upper region (framed by a sparse dashed line) for implementing conventional memory functions. The components included in the upper region may be referred to as a "first circuit set" below, and may particularly include a memory cell array and a first control logic circuit that operates the memory cell array based on received external instructions.

[0048] Furthermore, the memory 300 of the present invention may further include a "second circuit set" (enclosed by a tight dashed box) for implementing specific functions of the present invention, and may particularly include a second control logic circuit 322 and a power manager 321. In the illustrated example, since the second control logic circuit 322 can be specifically used for logic control in a low-power state, for example, for exiting a low-power state according to a combination signal, the second control logic circuit 322 may also be referred to as a low-power control logic 322.

[0049] In response to the instruction to enter a low power state, the power manager 321 may disable the first circuit set described above, causing the memory to enter a low power (PWD) mode. The instruction may be issued when the SI pin can continue to receive input data and the instruction decoder is functioning normally. The power manager 321 may disable the first circuit set described above under the control of the decoding result of the instruction decoder, causing the memory to enter a low power mode.

[0050] In contrast, the memory can exit the low-power state directly by a signal from a pin. In the present invention, this is achieved using a combination of the CS signal and other pin signals (e.g., one or more of the SI, SO, CLK, WP, and HOLD pins). To this end, in response to receiving a first predetermined combination of a chip select signal and an input signal from a first predetermined interface (illustrated as an external clock interface), the second control logic circuit 322 causes the power manager 321 to power the first circuit set, causing the memory to enter the standby state from the low-power state.

[0051] Since each circuit in the "first circuit set" is powered off in the low-power state of the present invention, it can be classified as the "VDD_PWD voltage domain." Since each circuit in the "second circuit set" remains enabled in the low-power state of the present invention, it can be classified as the "VDD voltage domain."

[0052] Furthermore, due to the need for complete record of chip status, Figure 3 The state register 323 shown in the upper portion generally also needs to remain enabled in the low power state of the present invention, so the second circuit set also includes the state register, and it can also be attributed to the "VDD voltage domain", such as Figure 3 Shown in the upper tight dashed box.

[0053] Therefore, in the low-power state of the present invention, only the low-power control logic 322, power manager 321, and status register 322 in the VDD voltage domain within the tightly bounded dashed box remain powered. Modules in the VDD_PWD domain within the sparsely bounded box, which are involved in normal memory operations, can be powered off in the low-power state. That is, VDD_PWD is disconnected from VDD and remains floating. Compared to the prior art, the present invention only needs to maintain power to the CS# and SCLK interfaces in the low-power state. A small amount of logic circuitry (i.e., the dedicated low-power control logic 322) ensures the correct response to the combined input signals of CS# and SCLK. All other interfaces can be powered off, thereby reducing power consumption.

[0054] As mentioned above, the "first circuit set" may include a memory cell array and a first control logic circuit that operates the memory cell array based on a received external instruction. Here, the memory cell array may correspond to Figure 3 The memory array 341 shown in FIG. Memory array 341 includes a plurality of memory cells arranged in an array and addressable via word lines and bit lines. The memory cells may be transistors having a floating gate or an insulating layer capable of trapping charge. A row decoder 343 is used to select a word line according to an address. A column decoder 342 is used to select a bit line according to an address. Figure 3 In the example shown in FIG, for layout convenience, the row decoder 343 can be combined with the write protection logic to serve as both the write protection logic and the row decoder 343. The column decoder 342 can be combined with the page buffer to serve as both the column decoder and the page buffer 342. In addition, although not shown in the figure, the memory module may further include sense amplifiers required for performing read and verify operations on the memory array 341.

[0055] As shown in the figure, the first control logic circuit in the first circuit set for operating the memory cell array based on the received external command may include an SPI command & control logic circuit 331.

[0056] Here, the SPI instruction & control logic circuit 331 can be regarded as a combination of an instruction decoder and a controller. Data obtained from the input and output interfaces (i.e., the SI, SO, CLK, and HOLD pins shown in the figure) can be temporarily stored in an input and output buffer (not shown in the figure) and further transmitted to the instruction decoder or controller. The data input line and data output line support a serial protocol. Data received through the data input line (via the SI pin) is first stored in the shift register of the input and output buffer, and then the data is moved from the shift register to the static random access memory so that it can be provided in parallel to the controller (corresponding to the controller portion of the logic circuit 331 in this example). Instructions received through the data input line are first stored in the shift register of the input and output buffer and then provided to the instruction decoder (corresponding to the instruction decoder portion of the logic circuit 331 in this example). Here, the controller can refer to the component that controls the operation of various components within the memory 300, and can include multiple sub-control components, such as the control logic circuit for voltage enable control and parameter setting required for reading, erasing, and programming operations on the storage array 341.

[0057] Accordingly, the first circuit assembly may also include a high-voltage generator 333 (also referred to as a charge pump 333) that provides specific voltages for reading, erasing, and writing to the memory array 341 (for example, providing a negative voltage for unselected word lines during a NOR flash memory read operation). In one embodiment, the charge pump 333 itself needs to operate at VDD, so the power manager 321 is also configured to provide voltage to the charge pump 333 when needed. The charge pump 333 may include multiple charge pump circuits, each configured to generate the voltage Vread required for a read operation, the voltage Vpgm required for a write operation, and the voltage Verase required for an erase operation.

[0058] When the SPI instruction & control logic circuit 331 receives an operation instruction for the memory array 341, it can notify the page address latch / counter 334 and the byte address latch / counter 335 to respectively instruct the column decoder 343 and the row decoder 342 to select the corresponding word line or bit line. At the same time, the charge pump 333 generates the voltage required for the operation under the control of the controller, thereby realizing the operation for the memory array 341.

[0059] Furthermore, the first circuit set may also include a write protection logic circuit 332 required for performing a write protection operation. The circuit receives a signal from the WP pin and, in combination with status information in the status register 323 , utilizes a logic circuit 343 to perform a write protection operation on the storage array 341 .

[0060] As before combined Figure 2 As shown, the memory may include a power port (pin 8 VCC), which is connected to an external power supply. The second circuit set of the present invention can be connected to the power interface to realize power supply from the external power supply. Specifically, the power manager 321 in the second circuit set can obtain external power and, under the control of the low-power control logic 322, supply power to the first circuit set including the SPI instruction & control logic circuit 331, the write protection logic circuit 332, the high-voltage generator 333, the page address latch / counter 334 and the byte address latch / counter 335, the memory array 341, the column decoder and the page buffer 342, and the write protection logic and the row decoder 343. In addition, it should be understood that the low-power control circuit 322 and the status register 323 in the second circuit set can also be powered by the power manager 321.

[0061] As previously described, the input / output interface may further include input / output buffers (not shown) between the SPI instruction and control logic circuit 331. In certain embodiments, signals received from the SI pin, CLK pin, CS pin, WP pin, and HOLD pin may be cached in the data input buffer, clock buffer, chip strobe signal buffer, write-protect buffer, and hold buffer, respectively, within the input / output buffers. Accordingly, the input / output buffers may further include a data output buffer for caching data to be output via the SO pin.

[0062] In an embodiment of the present invention, in a low-power state, only the chip enable signal cache and the first predetermined interface cache can be enabled, while other caches can be disabled, thereby further reducing power consumption. In other words, the chip enable signal cache and the first predetermined interface cache can be considered to belong to the second circuit set, and the other caches can be considered to belong to the first circuit set.

[0063] In a preferred embodiment, the memory of the present invention may include a sub-low power (SPWD) state in addition to the low power state and the standby state. In this state, a small number of operations can be performed, such as operations that do not involve the storage array 341, so fewer circuits need to be enabled than in the standby state. To this end, a portion of the original first circuit set can be divided into a third circuit set. The third circuit set includes an instruction decoder, and the second circuit set also includes a status register and an ID register. In response to a second predetermined combination signal of a chip selection signal and an input signal of a second predetermined interface, the second control logic circuit 322 can enable the power manager 321 to power the third circuit set while keeping the first circuit set disabled, so that the memory enters the sub-low power state from the low power state.

[0064] For example, in the secondary low power consumption state, the memory can also perform at least some read instruction operations, such as reading the corresponding contents of one or more registers in the memory. Specifically, the memory 300 may also include an ID register for memory-related ID information. When the memory is powered on, the memory can read the ID information of the memory (for example, the memory ID, the manufacturer ID of the memory, etc.) from the storage array (for example, a storage area specifically used for the memory ID information) and store it in the ID register. The ID register can remain enabled during the entire power-on period of the memory 300, thereby ensuring that the stored information is not lost. Therefore, when the memory 300 in the secondary low power consumption state is Figure 5As shown in the figure, when the READID (read ID) instruction is received, the instruction decoder can decode the above instruction, read the corresponding ID information from the ID register and output the ID information through the SO pin. At this time, in order to implement the above-mentioned read ID function, the clock cache, data input cache, data output cache and chip strobe cache in the input and output cache need to be enabled. Correspondingly, IO control also needs to be enabled to execute the read ID instruction. In the sub-low power state, the internal clock is disabled and the READID operation is performed under the control of the external clock on the clock line.

[0065] Figure 4 FIG. 3 is a schematic diagram showing a state switching of a memory according to an embodiment of the present invention. As shown in the figure, the operating states of the memory 300 may include a standby state, a low power consumption state (PWD), and a second low power consumption state (SPWD).

[0066] The following table lists the enable and disable conditions of various components in the memory 300 corresponding to various states.

[0067]

[0068]

[0069] Table 1

[0070] "Enable" means that a component is in a state where it can be used. "Disable" means that a component is in a state where it cannot be used. For example, you can enable a component by supplying power, and disable it by stopping the supply.

[0071] The standby state may indicate a state in which the memory 300 is able to perform corresponding operations in response to any instruction from the host 200. In the standby state, if there is no data transmission between the host 200 and the memory 300, the chip selection signal is maintained at a non-valid level. The standby state may further include an active state (active). When the memory 300 is in the standby state, when the host 200 needs to send instructions or data to the memory 300, the host 200 sets the chip selection signal to a valid level, and the memory 300 enters the active state. The memory 300 receives instructions or data through the data input line and sets the busy signal to valid. The above-mentioned standby state in which the chip selection signal is at a valid level may be referred to as an active state. In Figure 4In the example of , the present invention provides two energy-saving states for the memory: a sub-low power state (SPWD) and a low power state (PWD). The low power state may refer to a state in which only the components required to restore the memory to a higher power state based on a first predetermined combination signal of a chip selection signal and a first predetermined signal are powered. In the low power state, the memory 300 cannot respond to any instructions sent by the host 200 through the input signal line (that is, it can only react to the signal combination on a specific pin). In the sub-low power state, the memory 300 can respond to some instructions sent by the host 200 through the input signal line. Accordingly, some functions of the memory 300 are disabled and some components are not powered accordingly. For example, in the sub-low power state, the memory 300 cannot receive operation instructions for the memory array, and accordingly, the components used to perform operations on the memory array (for example, a high voltage generating component, a read amplifier, a row decoder, a column decoder, etc.) are disabled.

[0072] like Figure 4 As shown, the memory 300 in the low power state exits from the low power state to the standby state in response to a combination signal of the chip strobe signal and the first predetermined interface signal (eg, a combination of CS# and SCLK signals).

[0073] The memory 300 in the low power state exits from the low power state to the second low power state in response to the chip select signal and the second predetermined signal combination of the second predetermined interface signal (for example, a combination of the CS# signal and the SI signal). The second predetermined signal combination needs to be different from the first predetermined signal combination. In some embodiments, the first predetermined interface and the second predetermined interface are different. For example, a combination signal from the chip select interface and the clock interface is used to exit from the low power state to the standby state, and a combination signal from the chip select interface and the write protection interface is used to exit from the low power state to the second low power state. In some embodiments, the first predetermined interface and the second predetermined interface may be the same, but the signals thereon are different. In some embodiments, a state transition from a low power state to one of the other two states can be performed solely by virtue of the chip select signal becoming low.

[0074] The memory 300 in the standby state enters the second low power state in response to the received second low power state instruction (SPWD_cmd), and enters the low power state in response to the received low power state instruction (PWD_cmd). The memory 300 in the second low power state enters the low power state in response to the received low power state instruction (PWD_cmd_1), and enters the standby state in response to the received exit second low power state instruction (exit_SPWD_cmd).

[0075] Thus, the memory 300 can directly perform operations permitted by the second-lowest power consumption state in a state with lower power consumption than the standby state (i.e., the second-lowest power consumption state). After the operation in the second-lowest power consumption state is completed, it can be determined whether to enter the low-power consumption state with lower power consumption or the standby state as needed, thereby achieving more effective power saving and more flexible operation.

[0076] Figure 4 PWD_cmd and PWD_cmd_1 are used to distinguish instructions for entering a low-power state in different states. However, in actual operation, the opcodes corresponding to PWD_cmd and PWD_cmd_1 can be the same or different. In other words, in both the standby state and the second-lowest power state, since entering a low-power state requires responding to an opcode, the power manager 321 must power the instruction decoder 331, enabling the instruction decoder 331 so that the memory 300 enters a low-power state based on the low-power state instruction.

[0077] It should be understood that, although Table 1 and Figure 4 The embodiment of the present invention including the secondary low power consumption state is shown, but the memory of the present invention may also include only two states: the standby state and the low power consumption state, that is, the middle column of Table 1 is deleted. Figure 4 The principle of the present invention is still applicable even if the secondary low power consumption state is deleted.

[0078] Figure 5 A timing diagram for entering a low power state according to an embodiment of the present invention is shown. As shown in the figure, in the standby state, the low power state is entered by receiving the corresponding instruction. Specifically, the CS pin receives a valid chip selection signal (shown as a low level), the CLK pin receives a clock signal, and in the subsequent 8 clock cycles (here, it can be stipulated that 8 clock cycles, i.e. 8 dummycycles, are required to read the signal from SI), the memory receives an 8-bit opcode sequentially from the SI pin. The state of receiving instructions in the standby state can be further subdivided into the "activated state" shown in the figure as described above. In different embodiments, the opcode may also have different bits. The memory is in t DP The decoding and corresponding control operations are completed within the time, so that the memory enters a low power consumption state.

[0079] In standby mode, the voltage of the VDD_PWD voltage domain is VDD, and the normal power supply to the first circuit set is used to ensure that the memory correctly receives and responds to the instruction. After the chip selection signal is pulled low and the instruction to enter the low power state (for example, PWD_cmd) is received, the controller part of the SPI instruction & control logic circuit 331 outputs the corresponding control signal to the low power control logic circuit 322, thereby DPAfter a certain time, the power manager 321 stops supplying power to the first circuit set, and the VDD_PWD voltage domain is suspended, that is, all circuits in the first circuit set are disabled.

[0080] When the CS pin and the first predetermined interface receive a first predetermined combination of signals, the memory in the low power consumption state may respond to the signal combination, thereby causing the memory to leave the low power consumption state.

[0081] Figure 6 FIG1 shows a timing diagram of leaving a low power consumption state according to an embodiment of the present invention. Figure 6 In the example, the first predetermined interface is an external clock pin. The memory can exit the low power state under the action of a low-level chip select signal on the CS pin and an external clock signal triggered a predetermined number of times (for example, n times, n is greater than or equal to 0, preferably, n is less than 8). At this time, the SI pin and the SO pin are still in an ignored state. In response to receiving the correct signal combination, such as the chip select signal and the external clock signal triggered a predetermined number of times, the low power control logic 322 causes the power manager 321 to power the first circuit set, thereby leaving the low power state.

[0082] exist Figure 6 In the example, the first predetermined combination signal on the chip strobe pin and the first predetermined pin is: CS# is pulled low, then SCLK is triggered n times (n>0, which can be based on actual design requirements), and then CS# is pulled high again. The low-power logic circuit 322 recognizes the above predetermined signal combination and then waits for T RES The low-power logic circuit 322 enables the power manager 321 to start supplying power to the first circuit set. At this time, VDD_DPD changes from floating to VDD, and the chip enters the standby mode.

[0083] Although Figure 6 The example of using the CS# combined with SCLK signal combination to exit the low power state is shown. However, in actual applications, CS# can be combined with any one or more of the SI, SO, WP#, and HOLD# pins to exit the low power state, and the specific signal form and signal combination used on the pins can also be arbitrary. However, in general, the signal of the selected pin should be given during the period when the chip selection signal is valid. For example, during the period when the CS signal is pulled low and then changed high, a low level is given on the selected pin (for example, WP#), thereby enabling the low power logic circuit 322 to implement the above signal combination and to exit the low power state at T RES Then the power manager 321 is notified to start supplying power to the first circuit set.

[0084] In one embodiment, the present invention can be implemented as a memory control method, wherein the memory includes a first circuit set and a second circuit set, the first circuit set including a memory cell array, and a first control logic circuit for operating the memory cell array based on a received external instruction, the second circuit set including a second control logic circuit and a power manager, the method including: in response to an instruction to enter a low power state, the power manager disabling the first circuit set so that the memory enters a low power state; and in response to a first predetermined combination signal of a chip selection signal and a predetermined interface input signal, the second control logic circuit causing the power manager to power the first circuit set so that the memory enters a standby state from the low power state.

[0085] Furthermore, the present invention can also be implemented as a system, for example Figure 1 The electronic device shown includes a host, an interface bus, and the memory described above. The memory is coupled to the host via its input / output interface (eg, SPI interface) connected to the interface bus.

[0086] The memory, memory control method, and memory control system according to the present invention have been described in detail above with reference to the accompanying drawings. The present invention uses, for example, CS# and SCLK to exit low-power mode, thereby disconnecting power to all unrelated circuits within the chip, thereby significantly reducing power consumption in low-power mode.

[0087] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both.

[0088] While various embodiments of the present invention have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory comprising: A first circuit set including a memory cell array and a first control logic circuit for operating the memory cell array based on a received external instruction; as well as A second circuit set including a second control logic circuit and a power manager, In response to the instruction to enter a low power state, the power manager disables the first circuit set, and the memory enters a low power state. In response to receiving a first predetermined combination signal of a chip selection signal and an input signal of a first predetermined interface, the second control logic circuit causes the power manager to power the first circuit set so that the memory enters a standby state from the low power consumption state.

2. The memory according to claim 1, wherein The first predetermined interface is a clock interface, and In response to receiving the first predetermined combination signal of a chip strobe signal and a clock signal with a predetermined number of toggles, the second control logic circuit enables the power manager to power the first circuit set.

3. The memory according to claim 1, wherein The first predetermined interface includes at least one of the following: Maintain the interface; Write protection interface; Clock interface; Data input interface; and Data output interface.

4. The memory according to claim 1, wherein The memory includes a power port, the power port is connected to an external power source, and the second circuit set is powered by the external power source with low power consumption.

5. The memory according to claim 1, wherein The second circuit set includes a chip selection signal buffer and a first predetermined interface signal buffer.

6. The memory according to claim 1, wherein The first circuit set includes an instruction decoder, In response to the instruction decoder receiving an instruction to enter a low power consumption state, the power manager disables the first circuit set, and the memory enters a low power consumption state from a standby state.

7. The memory according to claim 1, wherein the second circuit set further comprises a status register, wherein: The status register is in an enabled state in a standby state and a low power consumption state.

8. The memory according to claim 1, wherein The memory further includes a third set of circuits, The third circuit set includes an instruction decoder, and the second circuit set also includes a status register and an ID register. In response to a combined signal of a chip selection signal and an input signal of a second predetermined interface, the low-power second control logic circuit causes the power manager to power the third circuit set while keeping the first circuit set disabled, so that the memory enters a second-low power state from the low-power state.

9. A memory control method, wherein the memory includes a first circuit set and a second circuit set, wherein the first circuit set includes a memory cell array and a first control logic circuit that operates the memory cell array based on a received external instruction, and the second circuit set includes a second control logic circuit and a power manager, the method comprising: In response to an instruction to enter a low power state, the power manager disables the first set of circuits so that the memory enters a low power state; as well as In response to a first predetermined combination signal of a chip selection signal and a predetermined interface input signal, the second control logic circuit enables the power manager to supply power to the first circuit set so that the memory enters a standby state from the low power state.

10. A system comprising: Host; Interface bus; as well as The memory according to any one of claims 1 to 8, which is coupled to the host via a connection between an input / output interface and the interface bus.

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