A wafer planarization method

Abstract

The present invention discloses a wafer flattening method, comprising: S1: forming a plurality of ridge structures on the surface of the wafer; S2: forming a dielectric layer on the surface of the wafer, so that a protrusion protruding from the surface of the dielectric layer is formed at the ridge structure; S3: grinding the dielectric layer using a first grinding method to remove the protrusion; S4: grinding the dielectric layer using a second grinding method to expose the top of the ridge structure, thereby completing the flattening operation on the ridge structure. The beneficial effect of the present invention is that the wafer surface is flattened by the grinding method, so that the parasitic capacitance of the dielectric layer is reduced, thereby enabling the device to be used in high-speed modulation occasions. The grinding method has a wide range of applications and can be applied to dielectric layers with less stress. At the same time, the wafer surface flattening process of the present technical solution can enable the grinding equipment to automatically reduce the grinding rate, thereby reducing the demand for processing equipment while achieving higher processing accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device processing, and in particular to a wafer planarization method. Background Art

[0002] In semiconductor devices, ridge structures are a common device structure and are widely used in semiconductor devices such as lasers, photoelectric receivers, and modulators. Taking semiconductor lasers and semiconductor optical amplifiers as examples, such semiconductor devices often use semiconductor materials to form active regions. The active regions are stimulated to generate electromagnetic radiation to emit lasers and achieve their optical properties. Since semiconductor optical devices have the advantages of low power consumption, long service life, high electro-optical conversion efficiency, and wide coverage band, they can be widely used in fiber communications, laser storage, laser display, laser marking, mechanical processing, biomedicine, and military fields. As shown in the attached figure, Figure 1 As shown, the ridge structure height of existing ridge devices is typically over 1µm. To achieve better metal connection characteristics, a thicker vapor deposition layer is often formed on the top of the device using a vapor deposition process, and a metal connection is then made on top of the ridge structure. This technology often leads to increased costs and reduced yield. Furthermore, according to the capacitance formula C = ∈A / d, as the vapor deposition layer thickness increases, the device's parasitic capacitance also increases, making such devices unsuitable for high-speed modulation.

[0003] Existing technologies typically address this technical issue by flattening the device surface through processes such as Polymide, CMP, and mechanical grinding. Polymide processes are prone to deformation during facet cleavage, which can affect device performance and yield; CMP processes are costly. Traditional mechanical grinding processes often suffer from low grinding precision and damage to ridged devices during the planarization process. Summary of the Invention

[0004] In view of the above problems existing in the prior art, a wafer planarization method is now provided.

[0005] The specific technical solutions are as follows:

[0006] A wafer planarization method, comprising:

[0007] Step S1: forming a plurality of ridge structures on the surface of the wafer;

[0008] Step S2: forming a dielectric layer on the surface of the wafer, so that a protrusion protruding from the surface of the dielectric layer is formed at the ridge structure;

[0009] Step S3: grinding the dielectric layer using a first grinding method to remove the protrusion;

[0010] Step S4: grinding the dielectric layer using a second grinding method to expose the top of the ridge structure, thereby completing a planarization operation on the ridge structure.

[0011] Preferably, in step S3, the first grinding method includes:

[0012] Step S31: polishing the dielectric layer using a first polishing rate;

[0013] Step S32: As the contact area between the protrusion and the polishing pad increases, the first polishing rate is gradually slowed down to a second polishing rate.

[0014] Preferably, in step S4, the second polishing method includes: polishing the surface of the dielectric layer at a third polishing rate;

[0015] The third polishing rate is lower than the second polishing rate.

[0016] Preferably, in both step S3 and step S4, a mechanical grinding process is used to grind the dielectric layer.

[0017] Preferably, the thickness of the dielectric layer is greater than the height of the ridge structure.

[0018] Preferably, the height of the ridge structure is between 1 μm and 10 μm.

[0019] Preferably, the dielectric layer is formed on the surface of the wafer by an evaporation process.

[0020] Preferably, the dielectric layer is made of silicon dioxide, aluminum oxide, hafnium dioxide or zirconium dioxide.

[0021] The above technical solution has the following advantages or beneficial effects:

[0022] 1. The wafer surface is flattened by grinding to reduce the parasitic capacitance of the dielectric layer, thereby enabling the device to be used in high-speed modulation applications;

[0023] 2. The grinding method has a wide range of applications and can be applied to dielectric layers with low stress. It can be applied to ridge devices of different heights.

[0024] 3. The grinding rate is self-adjusted based on the height of the remaining protrusion of the dielectric layer to achieve a faster overall grinding rate while being able to grind at a lower grinding rate when approaching the predetermined height, thereby facilitating control of the final height of the planarization process, thereby avoiding damage to the ridge structure caused by traditional mechanical grinding methods and improving the yield.

[0025] 4. Use mechanical grinding equipment to achieve lower production costs compared to CMP process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0027] Figure 1 It is a schematic diagram of the prior art;

[0028] Figure 2 is a flow chart of a method according to an embodiment of the present invention;

[0029] Figure 3 This is a flowchart of sub-steps of step S3 of an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the initial grinding state of an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of a first grinding state according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of a second grinding state according to an embodiment of the present invention;

[0033] Figure 7 Schematic diagram of the third grinding state according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0037] The wafer mentioned in the present invention refers to the chip used to make semiconductor circuits, and its material includes but is not limited to gallium arsenide, gallium nitride, indium phosphide or sapphire. The dielectric layer A1 refers to the structure covering the top of the device, and the ridge structure A3 refers to the structure of the device. Figure 1 The protruding structure above the semiconductor device depicted in FIG. This structure is commonly found in high-speed semiconductor devices such as laser transmitters, receivers, and modulators. It is typically located above the active area A4. In the prior art, a thicker metal layer A2 is typically used to connect the top of the ridge structure A3.

[0038] The present invention comprises:

[0039] A wafer planarization method, such as Figure 2 Shown, including:

[0040] Step S1: forming a plurality of ridge structures 2 on the surface of a wafer;

[0041] Step S2: forming a dielectric layer 1 on the surface of the wafer, so that a protrusion protruding from the surface of the dielectric layer 1 is formed at the ridge structure 2;

[0042] Step S3: grinding the dielectric layer 1 using a first grinding method to remove the protrusion;

[0043] Step S4 : grinding the dielectric layer 1 using a second grinding method to expose the top of the ridge structure 2 , thereby completing a planarization operation on the ridge structure 2 .

[0044] Specifically, in this embodiment, dielectric layer 1 is made of silicon dioxide and is formed on top of a ridge-shaped semiconductor device via an evaporation process. Because the ridge-shaped semiconductor device has a protruding ridge structure 2 at its top, when the evaporation process forms a dielectric layer 1 of uniform thickness on the device surface, the dielectric layer 1 above the ridge structure 2 will inevitably be higher than the dielectric layer 1 in the recessed portion. This can lead to connectivity issues between layers and within the same metal layer, so this technical solution requires planarization.

[0045] During the planarization process, this technical solution utilizes a mechanical polishing process to achieve lower processing costs. Furthermore, by automatically adjusting the polishing rate based on the thickness of the remaining protruding portion of the dielectric layer 1 during processing, a lower polishing rate is achieved near the end of the planarization process, thereby facilitating control of the final polishing height to expose the top of the ridge structure 2. This control method achieves a faster overall polishing process while accurately controlling the final polishing position, thereby improving the overall wafer planarization yield.

[0046] In a preferred embodiment, Figure 3 As shown, in step S3, the first grinding method includes:

[0047] Step S31: polishing the dielectric layer 1 using a first polishing rate;

[0048] Step S32: As the thickness of the protrusion decreases, the first grinding rate is gradually slowed down to a second grinding rate.

[0049] In a preferred embodiment, in step S4, the second polishing method includes: polishing the surface of the dielectric layer 1 at a third polishing rate;

[0050] The third polishing rate is lower than the second polishing rate.

[0051] It should be noted that Figures 4 to 7 As an embodiment, it is used to indicate that there are multiple protrusions of different heights on the wafer surface, and does not mean that the height of the protrusion at the center of the wafer surface is necessarily lower than the height of the protrusion near the circumference.

[0052] Specifically, if Figure 4 As shown, when the polishing pad 4 contacts the dielectric layer 1, it will inevitably first contact the protrusion of the dielectric layer 1 located above the ridge structure 2. Because the contact area between the protrusion and the polishing pad 4 is small, the friction between it and the polishing pad 4 is small, and the grinding rate is faster, thereby making the grinding rate at the higher protrusion position greater than the grinding rate at the lower protrusion position.

[0053] Then, if Figure 5 and Figure 6 As shown in FIG, as the grinding process continues, the higher protrusions will be ground first because they will first contact the polishing pad 4, so they will be ground first, so that the higher protrusions will be ground faster than the lower protrusions. At the same time, as the height of the polishing pad 4 decreases, the higher protrusions will be further ground until the polishing pad 4 is lowered. Figure 7 In the state shown, the protruding portion of the dielectric layer 1 is completely ground.

[0054] Furthermore, if Figure 7 As shown in FIG. 1 , after the polishing pad 4 has ground the protrusion, it contacts the entire dielectric layer 1 with a larger contact area. Based on the characteristics of the dielectric layer 1 formed by the evaporation process, its friction force also increases. This allows the adjustment of the grinding rate, thereby avoiding damage to the wafer surface when contacting the entire surface of the wafer, and achieving the flatness of the entire wafer. When the grinding process proceeds to the following Figure 6 After the state shown, the dielectric layer 1 needs to be further polished until the top of the ridge structure 2 is exposed from the dielectric layer 1 to achieve planarization.

[0055] Specifically, in this technical solution, the actual polishing rate is adjusted based on the surface characteristics of the dielectric layer 1. During the polishing process, when the polishing pad 4 first contacts the protrusion, the friction generated is also low due to the smaller contact area between the polishing pad 4 and the tip of the protrusion. Therefore, while the output power of the mechanical polishing equipment is constant, the polishing pad 4 can still maintain a high actual polishing rate, achieving rapid polishing of the protrusion of the dielectric layer 1. When the polishing pad 4 contacts the protrusion at a lower position, the contact area between the polishing pad 4 and the protrusion further increases, further increasing the friction. Experiments have shown that the relationship between contact area and friction is linear. Therefore, while the mechanical polishing equipment maintains its original output power, the polishing pad 4 gradually decreases due to the additional friction load that increases linearly with the height of the descent. After the polishing pad 4 completes polishing of the protrusion, it contacts the entire surface of the dielectric layer 1, and the contact area at this point is larger than that of the protrusion. While the mechanical polishing equipment maintains its original output power, the friction between the polishing pad 4 and the dielectric layer 1 further increases as the height of the polishing pad 4 decreases. It can be concluded that when the dielectric layer 1 reaches a specific height, the grinding rate of the polishing pad 4 will drop to an extremely low value, approaching self-stop. Based on the above principle, the self-stop of the mechanical grinding equipment can be achieved, which can reduce the processing cost while also allowing the dielectric layer 1 to be processed to the required height, thereby achieving a better wafer flattening effect. Alternatively, by controlling the thickness of the dielectric layer 1, when the wafer flattening process approaches the top of the ridge structure 2, the polishing pad 4 automatically drops to an extremely low grinding rate, facilitating precise control of the stop height of the polishing pad 4 to improve the yield of the wafer flattening process.

[0056] As an optional embodiment, there is a linear relationship between the remaining thickness of the dielectric layer 1 and the polishing rate of the polishing pad 4 when the protrusion is polished. By controlling the overall vapor-deposited thickness of the dielectric layer 1, the polishing rate of the polishing pad 4 after the protrusion is polished can be effectively adjusted. This allows the polishing pad 4 to accurately and automatically stop at a preset height while polishing the dielectric layer 1 to expose the top of the ridge structure 2. Alternatively, during the overall planarization of the dielectric layer 1 by the polishing pad 4, a lower polishing rate can be maintained to achieve accurate control of the final height of the planarization process.

[0057] In a preferred embodiment, in both step S3 and step S4 , a mechanical grinding process is used to grind the dielectric layer 1 .

[0058] In this technical solution, since the protrusions on the surface of the evaporated dielectric layer 1 have higher parts and lower parts, during the grinding process, the higher protrusions will be ground first, and then as the grinding height decreases, the polishing pad 4 gradually contacts the lower protrusions, and the contact area between it and the protrusions increases, and the friction force also increases accordingly. Based on this characteristic, the grinding rate can be adjusted according to the size of the contact surface, thereby achieving the flatness of the entire wafer. Therefore, lower production costs can be achieved through dry polishing. Among them, dry polishing refers to the use of mechanical grinding and polishing equipment to perform dry mechanical grinding on the wafer surface, which has lower production costs than the methods of chemical mechanical grinding and chemical polishing used in the prior art.

[0059] In a preferred embodiment, the thickness of the dielectric layer 1 is greater than the height of the ridge structure 2 .

[0060] Specifically, if Figure 3 As shown, the dielectric layer 1 formed by the evaporation process should completely cover the ridge-shaped semiconductor device, filling the areas of the ridge-shaped semiconductor device that do not have the protruding ridge structure 2, thereby achieving overall device surface flatness. By setting the thickness of the dielectric layer 1 to be greater than the thickness of the ridge structure 2, the recessed areas of the ridge-shaped semiconductor device can be effectively filled, and the device can be flattened during the subsequent polishing process.

[0061] In one embodiment, taking a ridge structure 2 with a height of 3 μm as an example, the dielectric layer 1 formed thereon by an evaporation process has a thickness of 5 μm. By setting the polishing pad 4 rotation speed to 3000 rpm, it can maintain a relatively fast polishing speed when polishing the higher dielectric layer. At the same time, when it completes polishing the protrusion, the polishing rate of the polishing pad 4 decreases to a very low value. At this time, the last 2 μm of the dielectric layer can be polished at a low speed, allowing the operator to accurately control the final flattening height.

[0062] In a preferred embodiment, the height of the ridge structure 2 is between 1 μm and 10 μm.

[0063] Specifically, in actual implementation, this technical solution is applicable to ridge structures 2 with a height between 1 μm and 10 μm. For ridge structures 2 of varying heights, simply by adjusting the thickness of the dielectric layer 1 and the rotational speed of the polishing pad 4, the polishing rate of the polishing pad 4 can be reduced to an extremely low value upon completion of polishing the protrusions.

[0064] In a preferred embodiment, the dielectric layer 1 is formed on the wafer surface by an evaporation process.

[0065] In a preferred embodiment, the dielectric layer 1 is made of silicon dioxide, aluminum oxide, hafnium dioxide or zirconium dioxide.

[0066] Specifically, the present technical solution is not only applicable to the dielectric layer 1 made of the above-mentioned material, but also applicable to dielectric materials made of other materials with smaller internal stress.

[0067] The beneficial effects of the present invention are:

[0068] 1. The wafer surface is flattened by grinding to reduce the parasitic capacitance of the dielectric layer, thereby enabling the device to be used in high-speed modulation applications.

[0069] 2. The grinding method has a wide range of applications and can be applied to dielectric layers with low stress. It can be applied to ridge devices of different heights.

[0070] 3. The grinding rate is self-adjusted based on the height of the remaining protrusion of the dielectric layer to achieve a faster overall grinding rate while being able to grind at a lower grinding rate when approaching the predetermined height, thereby facilitating control of the final height of the planarization process, thereby avoiding damage to the ridge structure caused by traditional mechanical grinding methods and improving the yield.

[0071] 4. Use mechanical grinding equipment to achieve lower production costs compared to CMP process.

[0072] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A wafer planarization method, characterized in that: include: Step S1: forming a plurality of ridge structures on the surface of the wafer; Step S2: forming a dielectric layer on the surface of the wafer, so that a protrusion protruding from the surface of the dielectric layer is formed at the ridge structure; Step S3: grinding the dielectric layer using a first grinding method to remove the protrusion; Step S4: polishing the dielectric layer using a second polishing method to expose the top of the ridge structure, thereby completing a planarization operation on the ridge structure; In step S4 , the mechanical polishing equipment maintains the original output power so that the mechanical polishing equipment tends to self-stop when the dielectric layer is polished to a specific height.

2. The planarization method according to claim 1, wherein: In step S3, the first grinding method includes: Step S31: polishing the dielectric layer using a first polishing rate; Step S32: As the contact area between the protrusion and the polishing pad increases, the first polishing rate is gradually slowed down to a second polishing rate.

3. The planarization method according to claim 2, wherein: In step S4, the second polishing method includes: polishing the surface of the dielectric layer using a third polishing rate; The third polishing rate is lower than the second polishing rate.

4. The planarization method according to claim 3, wherein: In both step S3 and step S4, the dielectric layer is ground using a mechanical grinding process.

5. The planarization method according to claim 1, wherein: The thickness of the dielectric layer is greater than the height of the ridge structure.

6. The planarization method according to claim 1, wherein: The height of the ridge structure is between 1 μm and 10 μm.

7. The planarization method according to claim 1, wherein: The dielectric layer is formed on the surface of the wafer through an evaporation process.

8. The planarization method according to claim 1, wherein: The dielectric layer is made of silicon dioxide, aluminum oxide, hafnium dioxide or zirconium dioxide.

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