Array substrate and preparation method thereof, and display panel

Abstract

The present invention discloses an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a substrate, a gate, a gate insulating layer, an active layer, a source-drain layer, a passivation layer, and a transparent conductive layer stacked in sequence from bottom to top. The source-drain layer comprises a source electrode and a drain electrode arranged at intervals. The material of the active layer comprises indium gallium zinc oxide. The passivation layer comprises an organic flat layer and a first passivation layer stacked in sequence from bottom to top. The material of the first passivation layer comprises polyimide. In the array substrate proposed by the present invention, the passivation layer not only has the function of protecting the channel layer, but also can align the liquid crystal, so that the array substrate does not need to be provided with other complex functional layers, has a simple structure, stable performance, and simplifies the manufacturing process and technology.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] TFT (Thin Film Transistor) is the abbreviation of thin film transistor, which is an important component of the array substrate. In TFT technology, amorphous metal oxide TFT has advantages such as carrier mobility and leakage current, as well as relatively balanced manufacturing process and manufacturing cost. It is considered to be the mainstream technology for the next generation of display. a-IGZO TFT (transparent amorphous indium gallium zinc oxide thin film transistor) is currently the most used TFT, but because the back channel of a-IGZO TFT is easily affected by water molecules and oxygen molecules in the environment, the characteristics of TFT devices are affected to a certain extent. Therefore, it is required to passivate the back channel of a-IGZO TFT devices to block water and oxygen. At present, the materials for passivation of a-IGZO TFT devices mainly include silicon dioxide, silicon nitride, aluminum oxide, etc., but after the formation of these passivation layers, the back channel of the array substrate is easily bombarded by ions, which will deteriorate the stability of the TFT device, and the manufacturing process is complicated. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate and a preparation method thereof, and a display panel, aiming to provide an array substrate that is easy to manufacture and has good stability.

[0004] To achieve the above-mentioned purpose, the present invention proposes an array substrate, comprising a substrate, a gate, a gate insulating layer, an active layer, a source-drain layer, a passivation layer and a transparent conductive layer stacked in sequence from bottom to top, the source-drain layer comprising a source electrode and a drain electrode spaced apart, the material of the active layer comprises indium gallium zinc oxide, the passivation layer comprises an organic planarization layer and a first passivation layer stacked in sequence from bottom to top, and the material of the first passivation layer comprises polyimide.

[0005] Optionally,

[0006] The thickness of the gate is 15 to 25 nm; and / or,

[0007] The thickness of the gate insulating layer is 200-250 nm; and / or,

[0008] The thickness of the active layer is 40-60 nm; and / or,

[0009] The thickness of the source-drain layer is 150-250 nm; and / or,

[0010] The thickness of the organic planar layer is 800-1000 nm; and / or,

[0011] The thickness of the first passivation layer is 700-900 nm; and / or,

[0012] The material of the organic planar layer includes at least one of the organic substances of structural formula (1) and (2):

[0013]

[0014] Wherein, m and n are positive integers respectively, and X, Y and Q are each independently selected from a hydrogen atom, a halogen atom, a carboxyl group or an alkyl group.

[0015] The present invention further provides a method for preparing the array substrate as described above, comprising the following steps:

[0016] Providing a substrate and preparing a gate on the upper side of the substrate;

[0017] Preparing a gate insulating layer on the upper side of the gate;

[0018] preparing an active layer on the upper side of the gate insulating layer;

[0019] Using magnetron sputtering to prepare a source-drain layer on the upper side of the active layer;

[0020] Spin coating to sequentially form an organic planarization layer and a first passivation layer on the upper side of the source / drain layer;

[0021] A transparent conductive layer is prepared on the upper side of the passivation layer.

[0022] Optionally, the step of providing a substrate and preparing a gate on the upper side of the substrate includes:

[0023] A substrate is provided, and a gate is prepared on the substrate by using a magnetron sputtering method.

[0024] Optionally,

[0025] The working gas of the magnetron sputtering method is argon gas, and the flow rate of argon gas is 50-60 sccm; and / or,

[0026] The sputtering gas pressure of the magnetron sputtering method is 0.36-0.4 Pa; and / or,

[0027] The sputtering power of the magnetron sputtering method is 0.11 to 0.15 kW; and / or,

[0028] The sputtering rate of the magnetron sputtering method is 4-6 nm / s.

[0029] Optionally, the step of preparing an active layer on the upper side of the gate insulating layer includes:

[0030] An active layer is prepared on the upper side of the gate insulating layer by using a magnetron sputtering method.

[0031] Optionally,

[0032] The working gas of the magnetron sputtering method includes argon gas, and the flow rate of the argon gas is 40-50 sccm; and / or,

[0033] The reaction gas of the magnetron sputtering method includes oxygen, and the flow rate of the oxygen is 3-5 sccm; and / or,

[0034] The sputtering gas pressure of the magnetron sputtering method is 0.4-0.6 Pa; and / or,

[0035] The sputtering power of the magnetron sputtering method is 0.1 to 0.2 kW; and / or,

[0036] The sputtering rate of the magnetron sputtering method is 7-8 nm / min.

[0037] Optionally, the step of sequentially forming an organic planarization layer and a first passivation layer by spin coating on the upper side of the source / drain layer comprises:

[0038] Spin-coating a raw material of an organic flat layer on the upper side of the source-drain layer, baking at 100-120° C. for 1-1.2 hours to form a thin film, and etching the thin film to obtain an organic flat layer;

[0039] Polyimide is spin-coated on the upper side of the organic planar layer, and baked at 300-320° C. for 1-1.2 hours to form a polyimide film, and the polyimide film is etched to form a first passivation layer.

[0040] Optionally,

[0041] In the step of etching the polyimide film to form a passivation layer, the etching is reactive ion etching, the introduced gas includes argon gas, and the flow rate of the argon gas is 30-35 sccm; and / or,

[0042] In the step of etching the polyimide film to form the first passivation layer, the etching is reactive ion etching, the introduced gas includes oxygen, and the flow rate of oxygen is 100-110 sccm; and / or,

[0043] In the step of etching the polyimide film to form the first passivation layer, the etching is reactive ion etching with an etching power of 0.14-0.15 kW; and / or,

[0044] In the step of etching the polyimide film to form the first passivation layer, the etching is reactive ion etching, and the etching time is 400 to 500 seconds; and / or,

[0045] The film-forming speed of the polyimide film is greater than the film-forming speed of the thin film.

[0046] The present invention further proposes a display panel, comprising a color filter substrate, an array substrate and a liquid crystal layer, wherein the color filter substrate and the array substrate are arranged opposite to each other, the liquid crystal layer is arranged between the color filter substrate and the array substrate, and the array substrate comprises the array substrate described above.

[0047] In the technical solution provided by the present invention, the material of the first passivation layer is polyimide. Polyimide is an organic material, which can better protect the back channel of the TFT device, block water and oxygen, and improve the stability of the TFT device. In addition, polyimide also has the function of aligning the liquid crystal, which can save the step of coating a layer of polyimide on the TFT after it is manufactured. Finally, an organic flat layer is provided to increase the flatness of the first passivation layer and improve the uniformity of the film thickness of the first passivation layer, thereby reducing the occurrence of poor alignment. In the array substrate proposed by the present invention, the first passivation layer not only has the function of protecting the channel layer, but also can align the liquid crystal, so that the array substrate does not need to be provided with other complex functional layers, has a simple structure, stable performance, and simplifies the manufacturing process and technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention;

[0050] Figure 2 is a schematic flow chart of a method for preparing an array substrate according to Embodiment 2 of the present invention;

[0051] Figure 3 a to Figure 3 f is a schematic structural diagram corresponding to the preparation process of the array substrate preparation method according to Embodiment 2 of the present invention;

[0052] Figure 4 The electrical property curve of the array substrate obtained in Example 2a of the present invention;

[0053] Figure 5 NBTS transfer characteristic curve of the array substrate obtained in Example 2a of the present invention;

[0054] Figure 6 It is a schematic structural diagram of a display panel according to Embodiment 3 of the present invention.

[0055] Description of Figure Numbers:

[0056] Label name Label name 1 Substrate 6 Passivation layer 2 Gate 7 Transparent conductive layer 3 Gate insulation layer 100 Color film substrate 4 Active layer 200 Array substrate 5 Source and drain layer 300 Liquid crystal layer 51 Source 301 liquid crystal molecules 52 Drain 400 Border glue

[0057] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0059] In addition, the meaning of "and / or" appearing in the full text includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or a solution that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0060] Example 1

[0061] The structure of the array substrate is as follows Figure 1 As shown: the array substrate includes a substrate 1, a gate 2, a gate insulating layer 3, an active layer 4, a source-drain layer 5, a passivation layer 6 and a transparent conductive layer 7 which are stacked in sequence from bottom to top, the source-drain layer includes a source electrode 51 and a drain electrode 52 which are spaced apart, the material of the active layer 4 includes indium gallium zinc oxide, the passivation layer 6 includes an organic planar layer and a first passivation layer which are stacked in sequence from bottom to top, and the material of the first passivation layer includes polyimide.

[0062] The present invention provides an array substrate, see Figure 1 The array substrate comprises a substrate 1, a gate 2, a gate insulating layer 3, an active layer 4, a source-drain layer 5, a passivation layer 6 and a transparent conductive layer 7 which are stacked in sequence from bottom to top, the source-drain layer comprises a source electrode 51 and a drain electrode 52 which are spaced apart, the material of the active layer 4 comprises indium gallium zinc oxide, the passivation layer 6 comprises an organic planarization layer and a first passivation layer which are stacked in sequence from bottom to top, and the material of the first passivation layer comprises polyimide.

[0063] In the array substrate proposed in the present invention, the material of the first passivation layer is polyimide. Polyimide is an organic material and can better protect the back channel of the TFT device, block water and oxygen, and improve the stability of the TFT device. In addition, polyimide also has the function of aligning the liquid crystal, which can save the step of coating a layer of polyimide on the TFT after it is manufactured. Finally, an organic flat layer is provided to increase the flatness of the first passivation layer and improve the uniformity of the film thickness of the first passivation layer, thereby reducing the occurrence of poor alignment. In the array substrate proposed in the present invention, the first passivation layer not only has the function of protecting the channel layer, but also can align the liquid crystal, so that the array substrate does not need to be provided with other complex functional layers, has a simple structure, stable performance, and simplifies the manufacturing process and technology.

[0064] In the embodiment of the present invention, IGZO (indium gallium zinc oxide) is the abbreviation of indium gallium zinc oxide, and its carrier mobility is 20 to 30 times that of amorphous silicon. It can greatly improve the charging and discharging rate of the device to the pixel electrode, improve the response speed of the pixel, and achieve a faster refresh rate. At the same time, the faster response also greatly improves the row scanning rate of the pixel.

[0065] In order to further improve the performance of the array substrate of the present invention, in the embodiment of the present invention, preferably, the thickness of the gate is 15-25nm; the thickness of the gate insulating layer is 200-250nm; the thickness of the active layer is 40-60nm; the thickness of the source-drain layer is 150-250nm; the thickness of the passivation layer is 800-1000nm; the thickness of the first passivation layer is 700-900nm. In the embodiment of the present invention, since the first passivation layer needs to have the dual functions of blocking water and oxygen and aligning the liquid crystal, its thickness needs to be set to 700-900nm, and the organic flat layer assists the first passivation layer, and its thickness is preferably 800-1000nm, so that the flatness of the first passivation layer is increased, the uniformity of the film thickness of the first passivation layer is improved, thereby reducing the occurrence of poor alignment, so that the stability of the entire array substrate is better. At the same time, the thickness of the gate, gate insulating layer, active layer, source-drain layer, etc. is optimized and limited to the above range, which is more conducive to improving the performance and stability of the array substrate.

[0066] It can be understood that the thickness limitations of the above-mentioned layers may satisfy only one or several of them, or may satisfy them simultaneously. As a preferred embodiment of the present invention, all of the above-mentioned thickness limitations are satisfied. Experiments show that when all of the above-mentioned thickness limitations are satisfied, the performance and stability of the array substrate in all aspects are the best.

[0067] In addition, the present invention does not limit the material of each layer. In the embodiment of the present invention, the gate is made of molybdenum, the gate insulating layer is made of silicon dioxide, and the source and drain layers are made of molybdenum.

[0068] For the organic planar layer, preferably, the material of the organic planar layer includes at least one of the organic substances of structural formulas (1) and (2):

[0069]

[0070] Wherein, m and n are positive integers respectively, and X, Y and Q are each independently selected from a hydrogen atom, a halogen atom, a carboxyl group or an alkyl group.

[0071] Studies have shown that the organic planarization layer uses at least one of the above materials, has good fluidity, is more conducive to increasing the planarity of the first passivation layer, and improves the uniformity of the film thickness of the first passivation layer, thereby reducing the occurrence of poor alignment.

[0072] Example 2

[0073] The present invention further provides a method for preparing the array substrate as described above. Figure 2 The method for preparing the array substrate provided by the present invention comprises the following steps:

[0074] S10, providing a substrate, and preparing a gate on the upper side of the substrate.

[0075] Preferably, in an embodiment of the present invention, the gate is prepared by magnetron sputtering, that is, the above steps specifically include:

[0076] A substrate is provided, and a gate is prepared on the substrate by using a magnetron sputtering method.

[0077] The magnetron sputtering method is to fill a proper amount of argon gas in a high vacuum, apply a DC voltage of several hundred K between the cathode (columnar target or planar target) and the anode (coating chamber wall), generate a magnetron type abnormal glow discharge in the coating chamber, and ionize the argon gas. The argon ions are accelerated by the cathode and bombard the cathode target surface, sputtering the atoms on the target surface to form a thin film on the substrate surface. By replacing targets of different materials and controlling different sputtering times, thin films of different materials and thicknesses can be obtained. The magnetron sputtering method has the advantages of strong bonding between the coating layer and the substrate, and a dense and uniform coating layer.

[0078] The present invention does not impose any restrictions on the conditions for preparing the gate by magnetron sputtering. Preferably, the working gas of the magnetron sputtering method is argon, and the flow rate of argon is 50-60sccm. sccm is a unit of volume flow rate, which represents standard milliliters per minute. In an embodiment of the present invention, the flow rate of argon can be 50sccm, 51sccm, 52sccm, 53sccm, 54sccm, 55sccm, 56sccm, 57sccm, 58sccm, 59sccm, 60sccm, etc. Under the above flow rates, a uniform gate with moderate thickness can be obtained.

[0079] In addition, preferably, the sputtering pressure of the magnetron sputtering method is 0.36-0.4Pa, for example, it can be 0.36Pa, 0.37Pa, 0.38Pa, 0.39Pa, 0.4Pa, etc., the sputtering power of the magnetron sputtering method is 0.11-0.15kW, for example, it can be 0.11kW, 0.12kW, 0.13kW, 0.14kW, 0.15kW, etc., and the sputtering rate of the magnetron sputtering method is 4-6nm / s, for example, it can be 4nm / s, 5nm / s, 6nm / s, etc. It can be understood that the above-mentioned sputtering pressure, sputtering power and sputtering rate can be satisfied at the same time, or only one of them can be satisfied. As a preferred embodiment of the present invention, the conditions of sputtering pressure, sputtering power and sputtering rate are satisfied at the same time, so that the obtained gate has uniform thickness and high flatness.

[0080] In addition, after the magnetron sputtering method is completed, the prepared layer generally needs to be etched to obtain a gate of the desired shape. In an embodiment of the present invention, when the gate is molybdenum, the etching solution can be hydrogen peroxide, and the etching method commonly used in the art can be used for etching, which will not be described one by one here.

[0081] S20, preparing a gate insulating layer on the upper side of the gate.

[0082] The present invention does not limit the preparation method of the gate insulating layer. The material of the gate insulating layer is silicon dioxide, and can be prepared by chemical vapor phase preparation, atomic layer preparation and other methods.

[0083] S30, preparing an active layer on the upper side of the gate insulating layer.

[0084] The material of the active layer includes indium gallium zinc oxide (IGZO), and step S30 includes:

[0085] Using magnetron sputtering to prepare an active layer on the upper side of the gate insulating layer;

[0086] The present invention does not impose any restriction on the conditions for preparing the active layer by the magnetron sputtering method. Preferably, the working gas of the magnetron sputtering method includes argon gas, and the flow rate of the argon gas is 40-50 sccm, for example, it can be 40 sccm, 41 sccm, 42 sccm, 43 sccm, 44 sccm, 45 sccm, 46 sccm, 47 sccm, 48 sccm, 49 sccm, 50 sccm, etc. The reaction gas of the magnetron sputtering method includes oxygen gas, and the flow rate of the oxygen gas is 3-5 sccm, for example, it can be 3 sccm, 4 sccm, 5 sccm, etc. Under the above flow rate ratio of oxygen and argon gas, a uniform active layer IGZO with moderate thickness can be obtained.

[0087] In addition, preferably, the sputtering gas pressure of the magnetron sputtering method is 0.4~0.6Pa, for example, it can be 0.4Pa, 0.5Pa, 0.6Pa, etc., the sputtering power of the magnetron sputtering method is 0.1~0.2kW, for example, it can be 0.1kW, 0.2kW, etc., and the sputtering rate of the magnetron sputtering method is 7~8nm / min, for example, it can be 7nm / min, 8nm / min, etc. It can be understood that the above-mentioned sputtering gas pressure, sputtering power and sputtering rate can be satisfied at the same time, or only one of them can be satisfied. As a preferred embodiment of the present invention, the conditions of sputtering gas pressure, sputtering power and sputtering rate are met at the same time, so that the obtained active layer has uniform thickness and high flatness.

[0088] S40, preparing a source-drain layer on the upper side of the active layer by using a magnetron sputtering method.

[0089] The material of the source and drain layer is not limited by the present invention. In the embodiment of the present invention, the material of the source and drain layer is molybdenum. After being prepared by magnetron sputtering, the prepared molybdenum layer needs to be etched to obtain the source and drain of the desired shape. In the embodiment of the present invention, when the source and drain layer is molybdenum, the etching solution can be hydrogen peroxide, and the etching method commonly used in the art can be used for etching, which will not be described one by one here.

[0090] S50 , forming an organic planarization layer and a first passivation layer in sequence by spin coating on the upper side of the source / drain layer.

[0091] Spin coating is the abbreviation of rotary coating method. The main equipment is a glue spreader. Spin coating includes three steps: batching, high-speed rotation, and volatilization to form a film. The thickness of the film is controlled by controlling the glue spreading time, rotation speed, drop amount, and the concentration and viscosity of the solution used. It has the advantages of precise thickness control, high cost performance, energy saving, and low pollution.

[0092] Preferably, in the embodiment of the present invention, step S50 includes:

[0093] S51, spin-coating a raw material of an organic planar layer on the upper side of the source-drain layer, baking at 100-120° C. for 1-1.2 hours to form a thin film, and etching the thin film to obtain an organic planar layer;

[0094] S52 , spin-coating polyimide on the upper side of the organic planar layer, baking at 300-320° C. for 1-1.2 hours to form a polyimide film, and etching the polyimide film to form a first passivation layer.

[0095] The present invention does not limit the etching conditions of the polyimide film. Preferably, the etching is reactive ion etching, which utilizes gas discharge to form plasma for etching and has the advantages of controllability, flexibility, good repeatability, no chemical pollution, and high cleanliness.

[0096] During reactive ion etching, the gas introduced includes argon, and the flow rate of argon is 30 to 35 sccm, for example, it can be 30 sccm, 31 sccm, 32 sccm, 33 sccm, 34 sccm, 35 sccm, etc. More preferably, the gas introduced also includes oxygen, and the flow rate of oxygen is 100 to 110 sccm. Under the above gas flow rate, the passivation layer is prepared uniformly and has a moderate thickness.

[0097] In addition, preferably, the etching power of the reactive ion etching is 0.14-0.15 kW; the etching time is 400-500 s. Under the above conditions, the obtained polyimide passivation layer is more uniform.

[0098] In the embodiment of the present invention, preferably, the film forming speed of the polyimide film is greater than the film forming speed of the thin film, polyimide has high volatility, and the film forming speed of the organic planar layer is lower. After baking, it has a higher density, so that the protection of the polyimide film to the TFT is enhanced; at the same time, the two baking processes form a structure in which the polyimide film layer is loose on the top and tight on the bottom. When the polyimide film is subsequently opened, there will be no weakening problem, and the substrate and the metal can be in better contact, thereby avoiding the occurrence of poor alignment during alignment.

[0099] S60, preparing a transparent conductive layer on the upper side of the passivation layer.

[0100] The purpose of preparing the transparent conductive layer is to increase the light transmittance. The present invention does not limit the preparation method of the transparent conductive layer. The transparent conductive layer can be made of ITO (indium tin oxide) film, which can be prepared by the preparation method of ITO thin film layer commonly used in the art, which will not be repeated here.

[0101] The preparation method of the array substrate proposed in the present invention simplifies the preparation process by optimizing the preparation process conditions of the gate, active layer, passivation layer and other layers, protects the back channel and prevents it from being bombarded by ions. At the same time, the polyimide passivation layer can effectively block water and oxygen gas molecules in the environment, thereby improving the stability of the device. The polyimide passivation layer is formed by a spin coating process, which can reduce the damage of the passivation layer film forming process to the channel layer of the TFT device.

[0102] See also Figure 3 , is a schematic diagram of the preparation process of the array substrate, and an embodiment of the method for preparing the array substrate according to the present invention is given below:

[0103] (1) providing a substrate, and using a magnetron sputtering method to prepare a gate having a thickness of 15 to 25 nm on the substrate, wherein the working gas of the magnetron sputtering method is argon gas, the flow rate of the argon gas is 50 to 60 sccm, the sputtering gas pressure is 0.36 to 0.4 Pa, the sputtering power is 0.11 to 0.15 kW, and the sputtering rate is 4 to 6 nm / s, see Figure 3 a;

[0104] (2) A gate insulating layer with a thickness of 200 to 250 nm is prepared on the upper side of the gate. Figure 3 b;

[0105] (3) Using magnetron sputtering, an active layer with a thickness of 40 to 60 nm is prepared on the upper side of the gate insulating layer. The working gas of the magnetron sputtering method includes argon and oxygen. The flow rate of argon is 40 to 50 sccm, the flow rate of oxygen is 3 to 5 sccm, the sputtering pressure is 0.4 to 0.6 Pa, the sputtering power is 0.1 to 0.2 kW, and the sputtering rate is 7 to 8 nm / min. Figure 3 c;

[0106] (4) A source-drain layer with a thickness of 150 to 250 nm is prepared on the upper side of the active layer by magnetron sputtering. Figure 3 d;

[0107] (5) Spin coating the raw material of the organic planar layer [the organic substance of structural formula (1) and / or the organic substance of structural formula (2)] on the upper side of the source / drain layer, baking at 100-120° C. for 1-1.2 h to form a thin film, and etching the thin film to obtain an organic planar layer with a thickness of 800-1000 nm; spin coating polyimide on the upper side of the organic planar layer, baking at 300-320° C. for 1-1.2 h to form a polyimide film (the film formation rate of the polyimide film is greater than the film formation rate of the thin film), and performing reactive ion etching on the polyimide film, introducing gases including argon and oxygen, the argon flow rate is 30-35 sccm, the oxygen flow rate is 100-110 sccm, the etching power is 0.14-0.15 kW, the etching time is 400-500 s, and a first passivation layer with a thickness of 700-900 nm is formed, see Figure 3 e;

[0108] (6) preparing a transparent conductive layer on the upper side of the passivation layer, see Figure 3 f.

[0109] Example 2a

[0110] See also Figure 2 and Figure 3 , the preparation process of the array substrate is as follows:

[0111] (1) providing a substrate, and preparing a gate having a thickness of 15 nm on the substrate by a magnetron sputtering method, wherein the working gas of the magnetron sputtering method is argon gas, the flow rate of the argon gas is 50 sccm, the sputtering gas pressure is 0.36 Pa, the sputtering power is 0.11 kW, and the sputtering rate is 4 nm / s;

[0112] (2) preparing a gate insulating layer with a thickness of 200 nm on the upper side of the gate;

[0113] (3) using a magnetron sputtering method to prepare an active layer with a thickness of 40 nm on the upper side of the gate insulating layer, the working gas of the magnetron sputtering method includes argon and oxygen, the flow rate of argon is 40 sccm, the flow rate of oxygen is 3 sccm, the sputtering pressure is 0.4 Pa, the sputtering power is 0.1 kW, and the sputtering rate is 7 nm / min;

[0114] (4) preparing a source-drain layer with a thickness of 150 nm on the upper side of the active layer by magnetron sputtering;

[0115] (5) Spin-coating the raw material of the organic planar layer [the organic substance of structural formula (1)] on the upper side of the source and drain layer, baking at 100° C. for 1 h to form a thin film, and etching the thin film to obtain an organic planar layer with a thickness of 800 nm; spin-coating polyimide on the upper side of the organic planar layer, baking at 300° C. for 1 h to form a polyimide film (the film formation rate of the polyimide film is greater than the film formation rate of the thin film), and performing reactive ion etching on the polyimide film, introducing gases including argon and oxygen, the argon flow rate is 30 sccm, the oxygen flow rate is 100 sccm, the etching power is 0.14 kW, and the etching time is 400 s, to form a first passivation layer with a thickness of 900 nm;

[0116] (6) Preparing a transparent conductive layer on the upper side of the passivation layer.

[0117] Taking the array substrate obtained in Example 2a of the present invention as an example, the stability of the array substrate prepared by the present invention is explained.

[0118] First, the electrical property curve of the array substrate of Example 2a is measured at room temperature, wherein the source-drain voltage Vd=10V, the source-drain current Id is used as the ordinate, and the gate-source voltage Vg is used as the abscissa, and a curve is plotted to obtain: Figure 4 It can be concluded that the switching current ratio of Example 1 is Ion / Ioff=6×10 7 , the switching current is relatively large and the performance is better.

[0119] Next, under the conditions of Vg=-20V, Vd=1V, the NBTS transfer characteristic curve of the array substrate of Example 2a was measured. Figure 5 As shown, it can be clearly seen that the threshold voltage drift is small, which indicates that the array substrate manufactured in the embodiment of the present invention has good stability.

[0120] Example 2b

[0121] See also Figure 2 and Figure 3 , the preparation process of the array substrate is as follows:

[0122] (1) providing a substrate, and preparing a gate with a thickness of 25 nm on the substrate by a magnetron sputtering method, wherein the working gas of the magnetron sputtering method is argon gas, the flow rate of the argon gas is 60 sccm, the sputtering gas pressure is 0.4 Pa, the sputtering power is 0.15 kW, and the sputtering rate is 6 nm / s;

[0123] (2) preparing a gate insulating layer with a thickness of 250 nm on the upper side of the gate;

[0124] (3) using a magnetron sputtering method to prepare an active layer with a thickness of 60 nm on the upper side of the gate insulating layer, the working gas of the magnetron sputtering method includes argon and oxygen, the flow rate of argon is 50 sccm, the flow rate of oxygen is 5 sccm, the sputtering pressure is 0.6 Pa, the sputtering power is 0.2 kW, and the sputtering rate is 8 nm / min;

[0125] (4) preparing a source-drain layer with a thickness of 250 nm on the upper side of the active layer by a magnetron sputtering method;

[0126] (5) Spin-coating the raw materials of the organic planar layer [the organic matter of structural formula (1) and the organic matter of structural formula (2), the molar ratio of the two being 8:1] on the upper side of the source and drain layer, baking at 120° C. for 1.2 h to form a thin film, and etching the thin film to obtain an organic planar layer with a thickness of 1000 nm; spin-coating polyimide on the upper side of the organic planar layer, baking at 320° C. for 1.2 h to form a polyimide film (the film formation rate of the polyimide film is greater than the film formation rate of the thin film), and performing reactive ion etching on the polyimide film, introducing gases including argon and oxygen, the argon flow rate being 35 sccm, the oxygen flow rate being 110 sccm, the etching power being 0.15 kW, and the etching time being 500 s, to form a first passivation layer with a thickness of 700 nm;

[0127] (6) Preparing a transparent conductive layer on the upper side of the passivation layer.

[0128] Example 2c

[0129] See also Figure 2 and Figure 3 , the preparation process of the array substrate is as follows:

[0130] (1) providing a substrate, and preparing a gate with a thickness of 20 nm on the substrate by a magnetron sputtering method, wherein the working gas of the magnetron sputtering method is argon gas, the flow rate of the argon gas is 55 sccm, the sputtering gas pressure is 0.38 Pa, the sputtering power is 0.13 kW, and the sputtering rate is 5 nm / s;

[0131] (2) preparing a gate insulating layer with a thickness of 225 nm on the upper side of the gate;

[0132] (3) using a magnetron sputtering method to prepare an active layer with a thickness of 50 nm on the upper side of the gate insulating layer, the working gas of the magnetron sputtering method includes argon and oxygen, the flow rate of argon is 45 sccm, the flow rate of oxygen is 4 sccm, the sputtering pressure is 0.5 Pa, the sputtering power is 0.15 kW, and the sputtering rate is 7.5 nm / min;

[0133] (4) preparing a source-drain layer with a thickness of 200 nm on the upper side of the active layer by magnetron sputtering;

[0134] (5) Spin coating the raw material of the organic planar layer [the organic substance of structural formula (2)] on the upper side of the source and drain layer, baking at 110° C. for 1.h to form a thin film, and etching the thin film to obtain an organic planar layer with a thickness of 900 nm; spin coating polyimide on the upper side of the organic planar layer, baking at 310° C. for 1.1 h to form a polyimide film (the film formation rate of the polyimide film is greater than the film formation rate of the thin film), and performing reactive ion etching on the polyimide film, introducing gases including argon and oxygen, the argon flow rate is 32 sccm, the oxygen flow rate is 105 sccm, the etching power is 0.15 kW, and the etching time is 450 s, to form a first passivation layer with a thickness of 800 nm;

[0135] (6) Preparing a transparent conductive layer on the upper side of the passivation layer.

[0136] Example 2d

[0137] See also Figure 2 and Figure 3 , the preparation process of the array substrate is as follows:

[0138] (1) providing a substrate, and preparing a gate having a thickness of 18 nm on the substrate by a magnetron sputtering method, wherein the working gas of the magnetron sputtering method is argon gas, the flow rate of the argon gas is 54 sccm, the sputtering gas pressure is 0.37 Pa, the sputtering power is 0.12 kW, and the sputtering rate is 4 nm / s;

[0139] (2) preparing a gate insulating layer with a thickness of 210 nm on the upper side of the gate;

[0140] (3) using a magnetron sputtering method to prepare an active layer with a thickness of 45 nm on the upper side of the gate insulating layer, the working gas of the magnetron sputtering method includes argon and oxygen, the flow rate of argon is 43 sccm, the flow rate of oxygen is 3 sccm, the sputtering pressure is 0.4 Pa, the sputtering power is 0.13 kW, and the sputtering rate is 7 nm / min;

[0141] (4) preparing a source-drain layer with a thickness of 190 nm on the upper side of the active layer by magnetron sputtering;

[0142] (5) Spin-coating the raw materials of the organic planar layer [the organic matter of structural formula (1) and the organic matter of structural formula (2), the molar ratio of the two being 10:1] on the upper side of the source and drain layer, baking at 115° C. for 1 hour to form a thin film, and etching the thin film to obtain an organic planar layer with a thickness of 850 nm; spin-coating polyimide on the upper side of the organic planar layer, baking at 308° C. for 1 hour to form a polyimide film (the film formation rate of the polyimide film is greater than the film formation rate of the thin film), and performing reactive ion etching on the polyimide film, introducing gases including argon and oxygen, the argon flow rate being 32 sccm, the oxygen flow rate being 103 sccm, the etching power being 0.14 kW, and the etching time being 410 s, to form a first passivation layer with a thickness of 850 nm;

[0143] (6) Preparing a transparent conductive layer on the upper side of the passivation layer.

[0144] Example 2e

[0145] See also Figure 2 and Figure 3 , the preparation process of the array substrate is as follows:

[0146] (1) providing a substrate, and preparing a gate having a thickness of 23 nm on the substrate by a magnetron sputtering method, wherein the working gas of the magnetron sputtering method is argon gas, the flow rate of the argon gas is 57 sccm, the sputtering gas pressure is 0.39 Pa, the sputtering power is 0.14 kW, and the sputtering rate is 6 nm / s;

[0147] (2) preparing a gate insulating layer with a thickness of 240 nm on the upper side of the gate;

[0148] (3) using a magnetron sputtering method to prepare an active layer with a thickness of 55 nm on the upper side of the gate insulating layer, the working gas of the magnetron sputtering method includes argon and oxygen, the flow rate of argon is 49 sccm, the flow rate of oxygen is 4 sccm, the sputtering pressure is 0.6 Pa, the sputtering power is 0.17 kW, and the sputtering rate is 8 nm / min;

[0149] (4) preparing a source-drain layer with a thickness of 230 nm on the upper side of the active layer by a magnetron sputtering method;

[0150] (5) Spin-coating the raw materials of the organic planar layer [the organic matter of structural formula (1) and the organic matter of structural formula (2), the molar ratio of the two being 15:1] on the upper side of the source and drain layer, baking at 1050° C. for 1.1 h to form a thin film, and etching the thin film to obtain an organic planar layer with a thickness of 950 nm; spin-coating polyimide on the upper side of the organic planar layer, baking at 315° C. for 1.2 h to form a polyimide film (the film formation rate of the polyimide film is greater than the film formation rate of the thin film), and performing reactive ion etching on the polyimide film, introducing gases including argon and oxygen, the argon flow rate being 33 sccm, the oxygen flow rate being 107 sccm, the etching power being 0.15 kW, and the etching time being 480 s, to form a first passivation layer with a thickness of 750 nm;

[0151] (6) Preparing a transparent conductive layer on the upper side of the passivation layer.

[0152] Example 3

[0153] See also Figure 6 The display panel includes a color filter substrate 100, an array substrate 200 and a liquid crystal layer 300. The color filter substrate 100 is arranged opposite to the array substrate 200. The liquid crystal layer 300 is arranged between the color filter substrate 100 and the array substrate 200. The liquid crystal layer 300 is composed of liquid crystal molecules 301. The array substrate 200 includes the array substrate as described above. In addition, the display panel also includes a frame glue 400. The frame glue 400 assembles the color filter substrate 100 and the array substrate 200 together to seal the display panel and prevent the liquid crystal molecules 301 from overflowing and water vapor from intruding.

[0154] In summary, the array substrate provided in the present invention does not need to be specially provided with an alignment layer, has a simpler structure, simplifies the manufacturing process and technology, and has good stability.

[0155] The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. For those skilled in the art, the present invention may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the patent protection scope of the present invention.

[0156] The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. For those skilled in the art, the present invention may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the patent protection scope of the present invention.

Claims

1. An array substrate, comprising a substrate, a gate, a gate insulating layer, an active layer, a source-drain layer, a passivation layer and a transparent conductive layer stacked in sequence from bottom to top, wherein the source-drain layer comprises a source electrode and a drain electrode arranged at intervals, characterized in that: The material of the active layer includes indium gallium zinc oxide, the passivation layer includes an organic planar layer and a first passivation layer stacked in sequence from bottom to top, and the material of the first passivation layer includes polyimide; wherein, The passivation layer is prepared by the following method: Spin-coating a raw material of an organic flat layer on the upper side of the source-drain layer, baking at 100-120° C. for 1-1.2 hours to form a thin film, and etching the thin film to obtain an organic flat layer; Polyimide is spin-coated on the upper side of the organic planar layer, and baked at 300-320° C. for 1-1.2 hours to form a polyimide film, and the polyimide film is etched to form a first passivation layer.

2. The array substrate according to claim 1, characterized in that: The thickness of the gate is 15 to 25 nm; and / or, The thickness of the gate insulating layer is 200-250 nm; and / or, The thickness of the active layer is 40-60 nm; and / or, The thickness of the source-drain layer is 150-250 nm; and / or, The thickness of the organic planar layer is 800-1000 nm; and / or, The thickness of the first passivation layer is 700-900 nm; and / or, The material of the organic planar layer includes at least one of the organic substances of structural formula (1) and (2): Wherein, m and n are positive integers respectively, and X, Y and Q are each independently selected from a hydrogen atom, a halogen atom, a carboxyl group or an alkyl group.

3. A method for preparing an array substrate according to claim 1 or 2, characterized in that: The following steps are involved: Providing a substrate and preparing a gate on the upper side of the substrate; Preparing a gate insulating layer on the upper side of the gate; preparing an active layer on the upper side of the gate insulating layer; Using magnetron sputtering to prepare a source-drain layer on the upper side of the active layer; Spin-coating a raw material of an organic flat layer on the upper side of the source-drain layer, baking at 100-120° C. for 1-1.2 hours to form a thin film, and etching the thin film to obtain an organic flat layer; Spin-coating polyimide on the upper side of the organic planar layer, baking at 300-320° C. for 1-1.2 hours to form a polyimide film, and etching the polyimide film to form a first passivation layer; A transparent conductive layer is formed on the upper side of the first passivation layer.

4. The method for preparing an array substrate according to claim 3, wherein: The step of providing a substrate and preparing a gate on the upper side of the substrate comprises: A substrate is provided, and a gate is prepared on the substrate by using a magnetron sputtering method.

5. The method for preparing an array substrate according to claim 4, wherein: The working gas of the magnetron sputtering method is argon gas, and the flow rate of argon gas is 50-60 sccm; and / or, The sputtering gas pressure of the magnetron sputtering method is 0.36-0.4 Pa; and / or, The sputtering power of the magnetron sputtering method is 0.11 to 0.15 kW; and / or, The sputtering rate of the magnetron sputtering method is 4-6 nm / s.

6. The method for preparing an array substrate according to claim 3, wherein: The step of preparing an active layer on the upper side of the gate insulating layer comprises: An active layer is prepared on the upper side of the gate insulating layer by using a magnetron sputtering method.

7. The method for preparing an array substrate according to claim 6, wherein: The working gas of the magnetron sputtering method includes argon gas, and the flow rate of the argon gas is 40-50 sccm; and / or, The reaction gas of the magnetron sputtering method includes oxygen, and the flow rate of the oxygen is 3-5 sccm; and / or, The sputtering gas pressure of the magnetron sputtering method is 0.4-0.6 Pa; and / or, The sputtering power of the magnetron sputtering method is 0.1 to 0.2 kW; and / or, The sputtering rate of the magnetron sputtering method is 7-8 nm / min.

8. The method for preparing an array substrate according to claim 3, wherein: In the step of etching the polyimide film to form a passivation layer, the etching is reactive ion etching, the introduced gas includes argon gas, and the flow rate of the argon gas is 30-35 sccm; and / or, In the step of etching the polyimide film to form the first passivation layer, the etching is reactive ion etching, the introduced gas includes oxygen, and the flow rate of the oxygen is 100-110 sccm; and / or, In the step of etching the polyimide film to form the first passivation layer, the etching is reactive ion etching with an etching power of 0.14-0.15 kW; and / or, In the step of etching the polyimide film to form the first passivation layer, the etching is reactive ion etching, and the etching time is 400 to 500 seconds; and / or, The film forming speed of the polyimide film is greater than the film forming speed of the thin film.

9. A display panel, characterized in that: It comprises a color filter substrate, an array substrate and a liquid crystal layer, wherein the color filter substrate and the array substrate are arranged opposite to each other, the liquid crystal layer is arranged between the color filter substrate and the array substrate, and the array substrate comprises the array substrate as claimed in claim 1 or 2.

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