Display panel and manufacturing method thereof

Abstract

The application discloses a display panel and a manufacturing method thereof. The display panel comprises a substrate, a first gate, a first gate insulating layer, an active layer, an interlayer dielectric layer, a first via, a second via, a source electrode and a drain electrode. The first gate is arranged on the substrate. The first gate insulating layer is arranged on the substrate. The active layer is arranged on the substrate and is different from the first gate. The active layer comprises at least a first sub-active layer and a second sub-active layer arranged in a stack. The first sub-active layer is arranged on the substrate. The second sub-active layer is arranged on one side of the first sub-active layer away from the substrate. The number of atoms of gallium in the first sub-active layer is greater than that in the second sub-active layer. The first via and the second via at least penetrate the interlayer dielectric layer. The interlayer dielectric layer is arranged on the substrate. The source electrode is electrically connected to the active layer through the first via. The drain electrode is electrically connected to the active layer through the second via. The display panel and the manufacturing method thereof can improve the stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a manufacturing method thereof. BACKGROUND

[0002] At present, a single film layer of indium gallium zinc oxide is generally used as an active layer. Due to a large oxygen flow in the film forming process, the oxygen content in the indium gallium zinc oxide film layer is high, thereby causing poor conductivity and low mobility of the device. If the oxygen flow is small during deposition, the oxygen content in the indium gallium zinc oxide film layer is low, and the oxygen vacancies are high, which causes many defects at the interface between the first gate insulating layer and the indium gallium zinc oxide film layer and the interface between the second gate insulating layer and the indium gallium zinc oxide film layer, thereby causing poor stability of the device.

[0003] Therefore, it is necessary to provide a new technical scheme to solve the above technical problems. SUMMARY

[0004] Embodiments of the present application provide a display panel and a manufacturing method thereof, which are used to improve the stability of the display panel.

[0005] Embodiments of the present application provide a display panel, which comprises:

[0006] a first gate electrode, disposed on the substrate;

[0007] a first gate insulating layer, disposed on the substrate;

[0008] an active layer, disposed on the substrate, the active layer and the first gate electrode are disposed in different layers, the active layer at least comprises a first sub-active layer and a second sub-active layer which are stacked, the first sub-active layer is disposed on the substrate, the second sub-active layer is disposed on a side of the first sub-active layer away from the substrate, the number of atoms of gallium in the first sub-active layer is greater than the number of atoms of gallium in the second sub-active layer;

[0009] an interlayer dielectric layer, disposed on the substrate;

[0010] a first via, at least penetrating the interlayer dielectric layer;

[0011] a second via, at least penetrating the interlayer dielectric layer;

[0012] a source electrode, disposed on the interlayer dielectric layer, and electrically connected to the active layer through the first via;

[0013] a drain electrode, disposed on the interlayer dielectric layer, and electrically connected to the active layer through the second via.

[0014] In the display panel provided by the embodiment of the present application, the active layer further comprises:

[0015] The third sub-active layer is arranged on the second sub-active layer, and the atomic number of gallium in the third sub-active layer is greater than that in the second sub-active layer.

[0016] In the display panel provided by the embodiment of the present application, the material of the first sub-active layer comprises indium gallium zinc oxide, wherein the ratio of the atomic number of indium, the atomic number of gallium and the atomic number of zinc in the first sub-active layer is indium: gallium: zinc = M: 1: N, wherein 0 < M < 1 and 0 < N < 1, and the ratio of the atomic number of indium, the atomic number of gallium and the atomic number of zinc in the third sub-active layer is indium: gallium: zinc = X: 1: Y, wherein 0 < X < 1 and 0 < Y < 1.

[0017] In the display panel provided by the embodiment of the present application, the first sub-active layer comprises a nitrogen element doped indium gallium zinc oxide active layer, and the third sub-active layer comprises a nitrogen element doped indium gallium zinc oxide active layer.

[0018] In the display panel provided by the embodiment of the present application, the material of the second sub-active layer comprises indium gallium zinc oxide, wherein the ratio of the atomic number of indium, the atomic number of gallium and the atomic number of zinc in the second sub-active layer is indium: gallium: zinc = 1: 1: 1.

[0019] In the display panel provided by the embodiment of the present application, the first gate electrode is arranged on the substrate, the first gate insulating layer covers the first gate electrode, the active layer is arranged on one side of the first gate insulating layer away from the substrate, and the interlayer dielectric layer covers the active layer and the first gate insulating layer.

[0020] In the display panel provided by the embodiment of the present application, the display panel further comprises:

[0021] The second gate insulating layer is arranged on one side of the active layer away from the first gate insulating layer.

[0022] The second gate electrode is arranged on one side of the second gate insulating layer away from the active layer.

[0023] The third via hole penetrates through the interlayer dielectric layer.

[0024] The fourth via hole penetrates through the interlayer dielectric layer and the first gate insulating layer.

[0025] The connecting electrode is arranged in the third via hole and the fourth via hole, and is used for connecting the first gate electrode and the second gate electrode.

[0026] In the display panel provided by the embodiment of the present application, the active layer is arranged on the substrate, the first gate insulating layer covers the substrate and the active layer, the first gate electrode is arranged on the side of the first gate insulating layer away from the substrate, and the interlayer dielectric layer covers the first gate electrode and the first gate insulating layer.

[0027] In the display panel provided by the embodiment of the present application, the thickness of the first sub-active layer and the thickness of the third sub-active layer are less than or equal to 15 nanometers, and the thickness of the second sub-active layer is between 10 nanometers and 90 nanometers.

[0028] In the display panel provided by the embodiment of the present application, the display panel further comprises:

[0029] a passivation layer arranged on the interlayer dielectric layer;

[0030] a contact electrode arranged on the passivation layer, one end of the contact electrode being connected to the drain electrode;

[0031] a planarization layer arranged on the passivation layer;

[0032] an anode arranged on the planarization layer, the other end of the contact electrode being connected to the anode;

[0033] a pixel definition layer arranged on the planarization layer and covering the anode;

[0034] a light-emitting layer arranged in the opening of the pixel definition layer;

[0035] a cathode arranged on the light-emitting layer.

[0036] The embodiment of the present application also provides a manufacturing method of a display panel, which comprises the following steps:

[0037] providing a substrate;

[0038] forming a first gate electrode on the substrate;

[0039] forming a first gate insulating layer on the substrate;

[0040] forming an active layer on the substrate, the active layer and the first gate electrode being arranged in different layers, the active layer comprising at least a first sub-active layer and a second sub-active layer arranged in layers, the second sub-active layer being arranged on the side of the first sub-active layer away from the substrate, the number of atoms of gallium in the first sub-active layer being greater than the number of atoms of gallium in the second sub-active layer;

[0041] forming an interlayer dielectric layer on the substrate;

[0042] forming a first via and a second via on the interlayer dielectric layer;

[0043] forming a source and a drain on the substrate, wherein the source is electrically connected to the active layer through the first via, and the drain is electrically connected to the active layer through the second via; wherein,

[0044] the step of forming the active layer on the substrate comprises:

[0045] forming indium gallium zinc oxide on the substrate, and doping the indium gallium zinc oxide with nitrogen to form the first sub-active layer;

[0046] forming indium gallium zinc oxide on the first sub-active layer to form the second sub-active layer.

[0047] The embodiment of the present application further provides a manufacturing method of a display panel, which comprises the following steps:

[0048] forming an active layer on the substrate, wherein the active layer is arranged in layers with the first gate electrode, the active layer comprises at least a first sub-active layer and a second sub-active layer arranged in layers, the second sub-active layer is arranged on a side of the first sub-active layer away from the substrate, and the atomic number of gallium in the first sub-active layer is greater than that in the second sub-active layer;

[0049] forming a first gate insulating layer on the active layer;

[0050] forming a first gate electrode on the first gate insulating layer;

[0051] forming an interlayer dielectric layer on the first gate electrode;

[0052] forming a first via and a second via on the interlayer dielectric layer;

[0053] forming a source and a drain on the substrate, wherein the source is electrically connected to the active layer through the first via, and the drain is electrically connected to the active layer through the second via; wherein,

[0054] the step of forming the active layer on the substrate comprises:

[0055] forming indium gallium zinc oxide on the substrate, and doping the indium gallium zinc oxide with nitrogen to form the first sub-active layer;

[0056] forming indium gallium zinc oxide on the first sub-active layer to form the second sub-active layer.

[0057] The embodiment of the present application provides a display panel and a manufacturing method thereof. In the display panel provided by the embodiment of the present application, the active layer is arranged in a structure of at least two layers, i.e., a first sub-active layer and a second sub-active layer, wherein the atomic number of gallium in the first sub-active layer is greater than the atomic number of gallium in the second sub-active layer. Since the combination ability of gallium and oxygen atoms is strong, the generation of deep level defects can be effectively inhibited, thereby improving the stability of the device.

[0058] In order to make the above content of the present application more obvious and easy to understand, the preferred embodiments are specifically described below, and the accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figure 1 A structure schematic diagram of the display panel provided by the first embodiment of the present application is shown in the figure.

[0060] Figure 2 A structure schematic diagram of the display panel provided by the second embodiment of the present application is shown in the figure.

[0061] Figure 3 A structure schematic diagram of the display panel provided by the third embodiment of the present application is shown in the figure.

[0062] Figure 4 A plane structure schematic diagram of the display panel provided by the third embodiment of the present application is shown in the figure.

[0063] Figure 5 A circuit diagram of the thin film transistor of the display panel provided by the third embodiment of the present application is shown in the figure.

[0064] Figure 6 A step flow chart of the manufacturing method of the display panel provided by the first embodiment of the present application is shown in the figure.

[0065] Figure 7 A step flow chart of the manufacturing method of the display panel provided by the third embodiment of the present application is shown in the figure.

[0066] Figures 8 to 13 A schematic diagram of the manufacturing method of the display panel provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0067] In order to make the above content of the present application more obvious and easy to understand, the preferred embodiments are specifically described below, and the accompanying drawings are described in detail as follows.

[0068] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0069] In the description of the present application, it needs to be understood that the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0070] The present application provides a display panel and a manufacturing method thereof. The following will be described in detail. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0071] The present application provides a display panel, which comprises a substrate, a first gate, a first gate insulating layer, an active layer, an interlayer dielectric layer, a first via, a second via, a source and a drain. The first gate is disposed on the substrate. The first gate insulating layer is disposed on the substrate. The active layer is disposed on the substrate, and the active layer and the first gate are disposed in different layers. The active layer comprises at least a first sub-active layer and a second sub-active layer disposed in layers. The first sub-active layer is disposed on the substrate, and the second sub-active layer is disposed on the side of the first sub-active layer away from the substrate. The atomic number of gallium in the first sub-active layer is greater than that in the second sub-active layer. The interlayer dielectric layer is disposed on the substrate. The first via at least penetrates the interlayer dielectric layer. The second via at least penetrates the interlayer dielectric layer. The source is disposed on the interlayer dielectric layer and electrically connected to the active layer through the first via. The drain is disposed on the interlayer dielectric layer and electrically connected to the active layer through the second via.

[0072] In the display panel provided in the embodiment of the present application, the active layer is arranged in a structure of at least two layers, i.e., a first sub-active layer and a second sub-active layer, wherein the atomic number of gallium in the first sub-active layer is greater than that in the second sub-active layer. Since gallium has strong combination ability with oxygen atoms, the generation of deep level defects can be effectively inhibited, thereby improving the stability of the device.

[0073] The display panel provided in the present application is described in detail below through specific embodiments.

[0074] Please refer to Figure 1 , Figure 1 The structure schematic diagram of the display panel provided in the first embodiment of the present application. The embodiment of the present application provides a display panel 100, which comprises a substrate 101, a first gate 102a, an active layer 104, a source 106 and a drain 107, a first gate insulating layer 103a, an interlayer dielectric layer 105, a passivation layer 108, a contact electrode 202, a planarization layer 201, a pixel definition layer 203, an anode 204, a light-emitting layer 205 and a cathode 206. Specifically, the active layer 104 is arranged on the substrate 101. The first gate insulating layer 103a covers the substrate 101 and the active layer 104. The active layer 104 comprises at least a first sub-active layer 104a and a second active layer 104b arranged in a stack, the first sub-active layer 104a is arranged on the substrate 101, and the second sub-active layer 104b is arranged on the side of the first sub-active layer 104a away from the substrate 101, wherein the atomic number of gallium in the first sub-active layer 104a is greater than that in the second sub-active layer 104b. The first gate 102a is arranged on the side of the first gate insulating layer 103a away from the substrate 101. The interlayer dielectric layer 105 covers the first gate 102a and the first gate insulating layer 103a. The first via hole h1 and the second via hole h2 penetrate the interlayer dielectric layer 105 and the first gate insulating layer 103a, the source 106 is electrically connected to the active layer 104 through the first via hole h1, and the drain 107 is electrically connected to the active layer 104 through the second via hole h2. The passivation layer 108 is arranged on the interlayer dielectric layer 105 and covers the source 106 and the drain 107. The contact electrode 202 is arranged on the passivation layer 108, one end of the contact electrode 202 is connected to the drain 107. The planarization layer 201 is arranged on the passivation layer 108. The anode 204 is arranged on the planarization layer 201, and the other end of the contact electrode 202 is connected to the anode 204. The pixel definition layer 203 is arranged on the planarization layer 201 and covers the anode 204. The light-emitting layer 205 is arranged in the opening of the pixel definition layer 203. The cathode 206 is arranged on the light-emitting layer 205.

[0075] In the display panel 100 provided in the embodiment of the present application, the active layer 104 is arranged in a structure of at least two layers, i.e., a first sub-active layer 104a and a second sub-active layer 104b, wherein the atomic number of gallium in the first sub-active layer 104a is greater than the atomic number of gallium in the second sub-active layer 104b. Since gallium has strong combination ability with oxygen atoms, the generation of deep level defects at the interface between the first gate insulating layer 103a and the active layer 104 can be effectively inhibited, thereby improving the stability of the device.

[0076] Further, please continue to refer to Figure 1 The active layer 104 can further include a third sub-active layer 104c, the third sub-active layer 104c is arranged on the second sub-active layer 104b, and the atomic number of gallium in the third sub-active layer 104c is greater than the atomic number of gallium in the second sub-active layer 104b.

[0077] It should be noted that the atomic number of gallium in the first sub-active layer 104a in the embodiment of the present application can be greater than the atomic number of gallium in the third sub-active layer 104a. In another embodiment, the atomic number of gallium in the first sub-active layer 104a can be less than or equal to the atomic number of gallium in the third sub-active layer 104a.

[0078] In the display panel 100 provided in the embodiment of the present application, the active layer 104 is arranged in a three-layer stacked structure, i.e., a first sub-active layer 104a, a second sub-active layer 104b and a third sub-active layer 104c, wherein the atomic number of gallium in the first sub-active layer 104a and the third sub-active layer 104 is greater than the atomic number of gallium in the second sub-active layer 104b. Since gallium has strong combination ability with oxygen atoms, the generation of deep level defects at the interface between the substrate 101 and the active layer 104 and the interface between the active layer 104 and the interlayer dielectric layer 105 can be effectively inhibited, thereby improving the stability of the device.

[0079] Please refer to Figure 2 , Figure 2 The structure schematic diagram of the display panel provided in the second embodiment of the present application. The display panel 100 provided in the second embodiment of the present application is different from the display panel 100 provided in the first embodiment in that the first gate 102a is arranged on the substrate 101. The first gate insulating layer 103a covers the first gate 102a. The active layer 104 is arranged on the side of the first gate insulating layer 103a away from the substrate 101. The interlayer dielectric layer 105 covers the active layer 104 and the first gate insulating layer 103a.

[0080] In the display panel 100 provided in the embodiment of the present application, the active layer 104 is arranged in a three-layered structure, i.e., a first sub-active layer 104a, a second sub-active layer 104b and a third sub-active layer 104c, wherein the atomic number of gallium in the first sub-active layer 104a and the third sub-active layer 104c is greater than that in the second sub-active layer 104b. Since gallium has strong combination ability with oxygen atoms, the generation of deep level defects at the interface between the first gate insulating layer and the active layer 104 and the interface between the active layer 104 and the interlayer dielectric layer 105 can be effectively inhibited, thereby improving the stability of the device.

[0081] Please refer to Figure 3 and Figure 4 , Figure 3 the structural schematic diagram of the display panel provided in the third embodiment of the present application. Figure 4 The planar structural schematic diagram of the display panel provided in the third embodiment of the present application. The display panel 100 provided in the third embodiment of the present application is different from the display panel 100 provided in the second embodiment in that the display panel 100 can further include a second gate insulating layer 103b, a second gate 102b, a third via hole h3, a fourth via hole h4 and a connecting electrode 109. The second gate insulating layer 103b is arranged on the side of the active layer 104 away from the first gate insulating layer 103a. The second gate 102b is arranged on the side of the second gate insulating layer 103b away from the active layer 104. The third via hole h3 penetrates the interlayer dielectric layer 105. The fourth via hole h4 penetrates the interlayer dielectric layer 105 and the first gate insulating layer 103a. The connecting electrode 109 is arranged in the third via hole h3 and the fourth via hole h4, and is used to connect the first gate 102a and the second gate 102b.

[0082] In the embodiment of the present application, the structure of the display panel 100 is designed as a double-gate structure, i.e., including the first gate 102a and the second gate 102b, and the first gate 102a and the second gate 102b are connected through the connecting electrode 109, so as to improve the mobility of the display panel 100 through the double-gate structure. Further, the active layer 104 is arranged in a three-layered structure, i.e., the first sub-active layer 104a, the second sub-active layer 104b and the third sub-active layer 104c, wherein the atomic number of gallium in the first sub-active layer 104a and the third sub-active layer 104c is greater than that in the second sub-active layer 104b. Since gallium has strong combination ability with oxygen atoms, the generation of deep level defects at the interface between the first gate insulating layer and the active layer 104 and the interface between the active layer 104 and the second gate insulating layer 103b can be effectively inhibited, thereby improving the stability of the device.

[0083] In some embodiments, the substrate 101 can be a glass substrate or a flexible substrate. The substrate 101 can further include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer, and a buffer layer, which are sequentially stacked. The second flexible substrate layer and the first flexible substrate layer can be made of at least one of PI (polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluoromethylbenzene containing polyarylate), or PCO (polycycloolefin). The buffer layer can be made of one or more of a stack structure of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride. The material of the first gate 102a can be selected from Cr, W, Ti, Ta, Mo, Al, Cu, or other metals or alloys. The gate metal layer made of multiple layers of metals can also meet the requirements.

[0084] The material of the first gate insulating layer 103a can be one of silicon nitride, silicon oxide, silicon oxynitride, or aluminum trioxide, or any combination thereof.

[0085] In some embodiments, the material of the first sub-active layer 104a includes indium gallium zinc oxide, and the ratio of the number of indium atoms, the number of gallium atoms, and the number of zinc atoms in the first sub-active layer 104a is indium: gallium: zinc = M: 1: N, where 0 < M < 1 and 0 < N < 1. For example, in an embodiment, the ratio of the number of indium atoms, the number of gallium atoms, and the number of zinc atoms in the first sub-active layer 104a is any one of indium: gallium: zinc = 0.1: 1: 0.2, 0.4: 1: 0.2, 0.3: 1: 0.3, or 0.1: 1: 0.8.

[0086] The material of the third sub-active layer 104c includes indium gallium zinc oxide, and the ratio of the number of indium atoms, the number of gallium atoms, and the number of zinc atoms in the third sub-active layer 104c is indium: gallium: zinc = X: 1: Y, where 0 < X < 1 and 0 < Y < 1. For example, in an embodiment, the ratio of the number of indium atoms, the number of gallium atoms, and the number of zinc atoms in the first sub-active layer 104a is any one of indium: gallium: zinc = 0.3: 1: 0.2, 0.4: 1: 0.2, 0.3: 1: 0.3, or 0.6: 1: 0.8.

[0087] It should be noted that the number of gallium atoms in the first sub-active layer 104a and the third sub-active layer 104c can be the same or different.

[0088] The material of the second sub-active layer includes indium gallium zinc oxide, and the ratio of the number of indium atoms, the number of gallium atoms, and the number of zinc atoms in the second sub-active layer 104b is indium: gallium: zinc = 1: 1: 1.

[0089] Since the oxygen bonding tendency (or "bonding energy") of indium, gallium, and zinc are different from each other, there are some oxygen vacancies in which some of indium, gallium, and zinc are not bonded with oxygen. The oxygen vacancy can be expressed as a "deep energy level" formed near the valence band in the energy level. The energy difference ΔEDC between the deep energy level and the conduction band is about 2.4 eV. The deep energy level of IGZO has an energy level slightly higher than the valence band. Therefore, the electron at the valence band energy level can easily transition to the deep energy level. Then, by a lower energy, the electron can transition to the conduction band. As a result, the carrier mobility of IGZO is very high.

[0090] However, when a thin film transistor including IGZO used for a channel element is used for a long time or exposed to very strong light, the mobility characteristics of IGZO can deteriorate. Note that one of the main reasons is that the oxygen vacancy (or defect state) that causes the "deep energy level" will increase, and then the electron that transitions from the valence band to the "deep energy level" can be trapped in the "deep energy level", and thus these trapped electrons can hinder the transition to the conduction band. In other words, if the number of defects that form the "deep energy level" is too large, so that the electron that transitions from the valence band does not transition to the conduction band, but remains in the "deep energy level". This is called "deep energy level trap". The more oxygen vacancies, the more defects at the interface of the first gate insulating layer 103a and the active layer 104, and the active layer 104 and the second gate insulating layer 103b, resulting in poor stability and low mobility of the display panel.

[0091] Therefore, the embodiments of the present application set the active layer 104 as three layers, i.e. the first sub-active layer 104a, the second sub-active layer 104b and the third sub-active layer 104c, wherein the number of gallium atoms in the first sub-active layer 104a and the third sub-active layer 104c is greater than the number of gallium atoms in the second sub-active layer 104b. Since gallium has strong binding ability with oxygen atoms, the generation of deep energy level defects can be effectively suppressed, thereby improving the stability of the device, thereby improving the reliability of the display panel. The ratio of the number of indium atoms, the number of gallium atoms and the number of zinc atoms in the second sub-active layer 104b is indium: gallium: zinc = 1:1:1, which ensures the conductivity and mobility of the display panel.

[0092] In some embodiments, the first sub-active layer 104a includes a nitrogen element doped indium gallium zinc oxide active layer, and the third sub-active layer 104c includes a nitrogen element doped indium gallium zinc oxide active layer. Since nitrogen atoms have strong binding ability with oxygen vacancies, the introduction of nitrogen elements can occupy oxygen vacancies, effectively regulating the carrier concentration and defect concentration in the active layer, thereby improving the mobility of the display panel and improving the reliability of the display panel.

[0093] In some embodiments, at least one of phosphorus, fluorine, selenium or tellurium can also be doped into the first sub-active layer 104a and / or the third sub-active layer 104c.

[0094] In some embodiments, the thickness of the first sub-active layer 104a and the thickness of the third sub-active layer 104c are less than or equal to 15 nanometers, and the thickness of the second sub-active layer 104b is between 10 nanometers and 90 nanometers. Optionally, the thickness of the first sub-active layer 104a can be any one of 0.5 nanometers, 3 nanometers, 5 nanometers, 8 nanometers, or 12 nanometers. The thickness of the third sub-active layer 104c can be any one of 0.5 nanometers, 3 nanometers, 5 nanometers, 8 nanometers, or 12 nanometers. The thickness of the second sub-active layer 104b can be any one of 15 nanometers, 23 nanometers, 35 nanometers, 58 nanometers, or 70 nanometers. In the embodiments of the present application, because the ratio of the number of indium atoms, the number of gallium atoms, and the number of zinc atoms in the second sub-active layer 104b is indium: gallium: zinc = 1: 1: 1, the second sub-active layer 104b has the best conductivity, and the thickness of the first sub-active layer 104a and the third sub-active layer 104c are both less than the thickness of the second sub-active layer 104b, that is, the conductivity of the active layer is ensured, and the stability of the display panel can be improved.

[0095] The interlayer medium layer 105 can be an oxide or an oxynitride.

[0096] The source electrode 106 and the drain electrode 107 can be made of Cr, W, Ti, Ta, Mo, Al, Cu, or the like metal or alloy, and a gate metal layer composed of multiple layers of metal can also meet the needs.

[0097] The material of the second gate insulating layer 103b can be one or any combination of silicon nitride, silicon oxide, silicon oxynitride, or aluminum trioxide.

[0098] The material of the second gate electrode 102b can be selected from Cr, W, Ti, Ta, Mo, Al, Cu, or the like metal or alloy, and a gate metal layer composed of multiple layers of metal can also meet the needs.

[0099] The connecting electrode 109 can be made of Cr, W, Ti, Ta, Mo, Al, Cu, or the like metal or alloy, and a gate metal layer composed of multiple layers of metal can also meet the needs. In some embodiments, the connecting electrode 109 can be made of the same material as the first gate electrode 102a and the second gate electrode 102b.

[0100] The material of the passivation layer 108 can be an inorganic non-metallic film layer material of SiOx, SiOx / SiNx stack, or SiOx / SiNx / Al2O3 stack.

[0101] Please refer to Figure 5 , Figure 5A circuit diagram corresponding to the display panel provided in the embodiment of the present application is shown in the figure. The first gate electrode 102a is connected to the first node Q, the second gate electrode 102b is connected to the second node P, and the first gate electrode 102a and the second gate electrode 102b are electrically connected through the connecting electrode 109. In the embodiment of the present application, the bottom gate of the dual-gate thin film transistor is used as the main gate, so that the threshold voltage of the driving transistor is adjusted by using the voltage of the top-gate source, to complete the extraction and compensation of the threshold voltage, thereby reducing the complexity of the pixel circuit and achieving better display uniformity. Since the dual-gate transistor has better stability, the threshold voltage variation of the dual-gate transistor is smaller than that of the single-gate transistor under long-term electrical stress, so that the threshold voltage extraction can be performed once and the next threshold voltage extraction can be performed after a long period of time, which undoubtedly makes the timing of the pixel circuit simpler and the driving speed faster.

[0102] Please refer to Figure 1 and Figure 6 , Figure 6 The step flow chart of the manufacturing method of the display panel provided in the first embodiment of the present application is shown in the figure. The manufacturing method of the display panel includes the following steps:

[0103] Step B001: providing a substrate 101.

[0104] Specifically, the substrate 101 can be a glass substrate or a flexible substrate. In some embodiments, the substrate 101 can further include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer, and a buffer layer which are sequentially stacked. The second flexible substrate layer and the first flexible substrate layer are made of the same material, which can include at least one of PI (polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyether sulfone), PAR (aromatic fluorine toluene containing polyarylate), or PCO (polycyclic olefin).

[0105] Step B002: forming an active layer 104 on the substrate 101, the active layer 104 and the first gate electrode 102a are arranged in different layers, and the active layer 104 at least includes a first sub-active layer 104a and a second sub-active layer 104b which are stacked, the second sub-active layer 104b is arranged on the side of the first sub-active layer 104a away from the substrate 101, and the atomic number of gallium in the first sub-active layer 104a is greater than that in the second sub-active layer 104b. The step of forming the active layer 104 on the substrate 101 includes:

[0106] forming indium gallium zinc oxide on the substrate 101, and doping the indium gallium zinc oxide with nitrogen to form the first sub-active layer 104a.

[0107] Specifically, a first sub-active layer 104a is formed on the substrate 101 by using magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, etc.

[0108] Next, an indium gallium zinc oxide is formed on the first sub-active layer 104a to form a second sub-active layer 104b.

[0109] Specifically, a second sub-active layer 104b is formed on the first sub-active layer 104a by using magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, etc.

[0110] Optionally, the step B002 can further include: forming an oxide material on the second sub-active layer 104b by using magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, etc., and performing nitrogen doping on the oxide material to form a third sub-active layer 104c.

[0111] Step B003: forming a first gate insulating layer 103a on the active layer 104.

[0112] The material of the first gate insulating layer 103a can be one or a combination of silicon oxide, silicon nitride, high dielectric constant dielectric material (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric material, and the thickness of the first gate insulating layer 103a can be 500 nm to 1000 nm, especially 600 nm. The first gate insulating layer 103a can be formed by using plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology, etc.

[0113] Step B004: forming a first gate 102a on the first gate insulating layer 103a.

[0114] The first gate 102a can be a single metal layer or a multi-layer metal layer composed of one or a combination of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) and chromium (Cr). The first gate 102a can also be a non-reflective material, such as one or a combination of conductive metal oxides (such as ITO) or other conductive materials. The thickness of the first gate 102a can be 10 nm to 800 nm according to the needs, especially 200 nm.

[0115] Step B005: forming an interlayer dielectric layer 105 on the first gate 102a.

[0116] The interlayer dielectric layer 105 is deposited on the substrate 101 by using plasma chemical vapor deposition method. The material of the interlayer dielectric layer 105 can be one or a combination of silicon oxide, silicon nitride, high dielectric constant dielectric material (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric material, and the thickness of the interlayer dielectric layer 105 can be 100 nm to 1200 nm, especially 400 nm.

[0117] Step B006: Forming first via hole h1 and second via hole h2 on the interlayer dielectric layer 105.

[0118] The first via hole h1, the second via hole h2, the third via hole h3 and the fourth via hole h4 are formed by one photolithography process. Specifically, the first via hole h1 can be a source contact hole, and the second via hole h2 can be a drain contact hole.

[0119] Step B007: Forming source 106 and drain 107 on the substrate 101, wherein the source 106 is electrically connected to the active layer 104 through the first via hole h1, and the drain 107 is electrically connected to the active layer 104 through the second via hole h2.

[0120] Specifically, the electrode conductive layer is deposited on the interlayer dielectric layer 105 and the first via hole h1 and the second via hole h2 by magnetron sputtering, reactive sputtering, thermal evaporation, electron beam evaporation, etc., and the material of the electrode conductive layer can be one or a combination of more than one of metal (such as molybdenum, copper, aluminum, titanium, chromium, etc.), conductive metal oxide (such as ITO) or other conductive materials. Then, the source 106 and the drain 107 are formed by etching.

[0121] Please refer to Figure 7 , Figure 7 The step flow chart of the manufacturing method of the display panel provided by the third embodiment of the present application is shown in the following.

[0122] Step B01: Providing a substrate 101, please refer to Figure 8 .

[0123] Specifically, the substrate 101 can be a glass substrate or a flexible substrate. In some embodiments, the substrate 101 can further include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer and a buffer layer which are sequentially stacked. The second flexible substrate layer and the first flexible substrate layer are made of the same material, which can include at least one of PI (polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyether sulfone), PAR (aromatic fluoromethylbenzene containing polyarylate) or PCO (polycyclic olefin).

[0124] Step B02: Forming a first gate 102a on the substrate 101, please continue to refer to Figure 8 .

[0125] Specifically, a first gate conductive layer 1021 is first deposited on the substrate 101. The first gate conductive layer 1021 can be formed of a single metal layer or a multi-layer metal layer of a single element or an alloy of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) and chromium (Cr). The first gate conductive layer 1021 can also be formed of a non-reflective material, such as one or more combinations of conductive metal oxides (such as ITO) or other conductive materials. The thickness of the first gate conductive layer 1021 can be 10 nm to 800 nm, particularly 200 nm, as required. The first gate conductive layer 1021 can be formed on the substrate 101 by using a magnetron sputtering, reactive sputtering, thermal evaporation, electron beam evaporation or other technique. The reflective light referred to herein means that the transmittance is less than 20%. The first gate conductive layer 1021 can then be patterned to form a first gate electrode 102a. Specifically, a photoresist is first spin-coated on the first gate conductive layer 1021, and then subjected to photolithography, photoresist stripping, cleaning and other operations to finally obtain the patterned first gate electrode 102a.

[0126] Step B03: forming a first gate insulating layer 103a on the substrate 101, please refer to Figure 9 .

[0127] Specifically, a first gate insulating layer 103a is deposited on the substrate 101 and the first gate electrode 102a. The material of the first gate insulating layer 103a can be one or more combinations of silicon oxide, silicon nitride, high dielectric constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric materials, and the thickness of the first gate insulating layer 103a can be 500 nm to 1000 nm, particularly 600 nm. The first gate insulating layer 103a can be formed by using plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology, etc.

[0128] Step B04: forming an active layer 104 on the substrate 101, the active layer 104 and the first gate electrode 102a are arranged in different layers, and the active layer 104 at least includes a first sub-active layer 104a and a second sub-active layer 104b arranged in layers, the atomic number of gallium in the first sub-active layer 104a is greater than the atomic number of gallium in the second sub-active layer, please refer to Figure 10 .

[0129] The step of forming the active layer 104 on the substrate 101 includes:

[0130] forming an indium gallium zinc oxide on the substrate 101, and doping the indium gallium zinc oxide with nitrogen to form the first sub-active layer 104a.

[0131] Specifically, the first oxide material layer 1041 is formed on the first gate insulating layer 103a by using magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, and nitrogen doping is performed on the first oxide material layer 1041 by using magnetron sputtering. The thickness of the first oxide material layer 1041 is less than or equal to 15 nm.

[0132] Next, indium gallium zinc oxide is formed on the first sub-active layer 104a to form a second sub-active layer 104b.

[0133] Specifically, the second oxide material layer 1042 is formed on the first oxide material layer 1041 by using magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating. The thickness of the second oxide material layer 1042 is between 10 nm and 90 nm.

[0134] Optionally, step B04 can further include: forming a third oxide material layer 1043 on the second oxide material layer 1042 by using magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, and nitrogen doping is performed on the third oxide material layer 1043 by using magnetron sputtering. The thickness of the third oxide material layer 1043 is less than or equal to 15 nm.

[0135] Next, the first oxide material layer 1041, the second oxide material layer 1042 and the third oxide material layer 1043 are patterned to form an active layer 104. Specifically, photoresist can be spin-coated on the third oxide material layer 1043, then photoetching and etching are performed, and then the photoresist is removed and cleaned to obtain the active layer 104. The active layer 104 includes a doped region and a channel region, and the channel region is located on both sides of the active region.

[0136] After step B04, the following steps can be further included:

[0137] A second gate insulating layer 103b is formed on the active layer 104. Specifically, the material of the second gate insulating layer 103b can be one or a combination of silicon oxide, silicon nitride, high dielectric constant dielectric material (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric material, and the thickness of the second gate insulating layer 103b can be 50 nm to 500 nm, especially 300 nm. The second gate insulating layer 103b can be formed by using plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology, etc. Please refer to Figure 11 .

[0138] After the step of forming the second gate insulating layer 103b on the active layer 104, the following steps can be further included:

[0139] A second gate conductive layer 1022 is deposited on the second gate insulating layer 103b. The second gate conductive layer 1022 can be a single metal layer or a multi-layer metal layer made of one or more of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), and chromium (Cr). The second gate conductive layer 1022 can also be made of a non-reflective material, such as one or more of conductive metal oxides (e.g., ITO) or other conductive materials. The thickness of the second gate conductive layer 1022 can be 100 nm to 800 nm, and specifically 200 nm, as desired. The second gate conductive layer 1022 can be formed on the substrate 101 using techniques such as magnetron sputtering, reactive sputtering, thermal evaporation, electron beam evaporation, etc. As used herein, "reflective" means a transmittance of at least 20%. The second gate conductive layer 1022 can then be patterned to form a second gate 102b. Specifically, a photoresist is spin-coated on the second gate conductive layer 1022, and then subjected to photolithography, resist stripping, cleaning, etc. to obtain the patterned second gate 102b. See FIG. 1B. Figure 11 .

[0140] Step B05: Forming an interlayer dielectric layer 105 on the substrate 101. See FIG. 1C. Figure 12 .

[0141] Specifically, the interlayer dielectric layer 105 is deposited on the substrate 101 using a plasma chemical vapor deposition method. The material of the interlayer dielectric layer 105 can be one or more of silicon oxide, silicon nitride, high-dielectric-constant dielectric materials (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.), and organic dielectric materials, and the thickness of the interlayer dielectric layer 105 can be 100 nm to 1200 nm, and specifically 400 nm.

[0142] Step B06: Forming a first via h1 and a second via h2 on the interlayer dielectric layer 105. See FIG. 1D. Figure 12 .

[0143] Step B06 also includes forming a third via h3 and a fourth via h4. Specifically, the first via h1, the second via h2, the third via h3, and the fourth via h4 are formed in one photolithography process. The first via h1, the second via h2, and the third via h3 penetrate the interlayer dielectric layer 105, and the fourth via h4 penetrates the interlayer dielectric layer 105 and the first gate insulating layer 103a. Specifically, the first via h1 can be a source contact hole, the second via h2 can be a drain contact hole, and the third via h3 and the fourth via h4 can be connection electrode contact holes.

[0144] Step B07: Forming a source 106 and a drain 107 on the substrate 101, where the source 106 is electrically connected to the active layer 104 through the first via h1, and the drain 107 is electrically connected to the active layer 104 through the second via h2. See FIG. 1E.Figure 13 .

[0145] In an embodiment, step B07 further comprises forming the connecting electrode 109. Wherein the connecting electrode 109, the source electrode 106 and the drain electrode 107 can be formed by the same photolithography process. Specifically, the electrode conductive layer is deposited on the interlayer dielectric layer 105 and the first via h1, the second via h2, the third via h3 and the fourth via h4 by magnetron sputtering, reactive sputtering, thermal evaporation, electron beam evaporation, etc. The material of the electrode conductive layer can be one or a combination of metal (such as molybdenum, copper, aluminum, titanium, chromium, etc.), conductive metal oxide (such as ITO) or other conductive materials. Then, the source electrode 106, the drain electrode 107 and the connecting electrode 109 are formed by etching.

[0146] After step B07, further comprising forming a passivation layer 108 on the substrate 101, please refer to Figure 3 .

[0147] Specifically, the passivation layer 108 is deposited on the substrate 101 by plasma chemical vapor deposition method. The material of the passivation layer 108 can be one or a combination of silicon oxide, silicon nitride, high dielectric constant dielectric material (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric material, and the thickness of the passivation layer 108 can be 50nm-800nm, and particularly can be 400nm.

[0148] The embodiment of the present application provides a display panel and a manufacturing method thereof. In the display panel provided by the embodiment of the present application, the active layer is provided as three layers, i.e., a first sub-active layer, a second sub-active layer and a third sub-active layer, wherein the atomic number of gallium in the first sub-active layer and the third sub-active layer is greater than that in the second sub-active layer. Since the combination ability of gallium and oxygen atom is strong, the generation of deep level defects can be effectively inhibited, thereby improving the stability of the device, and thus the reliability of the display panel is improved. And the ratio of the atomic number of indium, the atomic number of gallium and the atomic number of zinc in the second sub-active layer is indium: gallium: zinc = 1: 1: 1, which ensures the conductivity and mobility of the display panel.

[0149] To sum up, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a first gate electrode disposed on the substrate; a first gate insulating layer disposed on the substrate; an active layer disposed on the substrate, the active layer and the first gate electrode being disposed in different layers, the active layer comprising at least a first sub-active layer and a second sub-active layer disposed in layers, the first sub-active layer being disposed on the substrate, the second sub-active layer being disposed on a side of the first sub-active layer away from the substrate, the first sub-active layer having a number of gallium atoms greater than that of the second sub-active layer; an interlayer dielectric layer disposed on the substrate; a first via hole at least penetrating the interlayer dielectric layer; a second via hole at least penetrating the interlayer dielectric layer; a source electrode disposed on the interlayer dielectric layer and electrically connected to the active layer through the first via hole; a drain electrode disposed on the interlayer dielectric layer and electrically connected to the active layer through the second via hole; wherein the material of the first sub-active layer comprises indium gallium zinc oxide, and the ratio of the number of indium atoms, the number of gallium atoms and the number of zinc atoms in the first sub-active layer is any one of indium: gallium: zinc = 0.1:1:0.2, 0.4:1:0.2, 0.3:1:0.3 or 0.1:1:0.

8.

2. The display panel of claim 1, wherein, The active layer further comprises: a third sub-active layer disposed on the second sub-active layer, the third sub-active layer having a number of gallium atoms greater than that of the second sub-active layer.

3. The display panel of claim 2, wherein, The ratio of the number of indium atoms, the number of gallium atoms and the number of zinc atoms in the third sub-active layer is indium: gallium: zinc = X:1:Y, 0X<1, 0Y<1.

4. The display panel of claim 3, wherein, The first sub-active layer comprises a nitrogen-doped indium gallium zinc oxide active layer, and the third sub-active layer comprises a nitrogen-doped indium gallium zinc oxide active layer.

5. The display panel of claim 1, wherein, The material of the second sub-active layer comprises indium gallium zinc oxide, and the ratio of the number of indium atoms, the number of gallium atoms and the number of zinc atoms in the second sub-active layer is indium: gallium: zinc = 1:1:

1.

6. The display panel of claim 1 or 2, wherein, The first gate electrode is disposed on the substrate, the first gate insulating layer covers the first gate electrode, the active layer is disposed on a side of the first gate insulating layer away from the substrate, and the interlayer dielectric layer covers the active layer and the first gate insulating layer.

7. The display panel of claim 6, wherein, The display panel further comprises: a second gate insulating layer disposed on a side of the active layer away from the first gate insulating layer; a second gate electrode disposed on a side of the second gate insulating layer away from the active layer; a third via hole penetrating the interlayer dielectric layer; a fourth via hole penetrating the interlayer dielectric layer and the first gate insulating layer; a connection electrode disposed in the third via hole and the fourth via hole, for connecting the first gate electrode and the second gate electrode.

8. The display panel of claim 1 or 2, wherein, The active layer is disposed on the substrate, the first gate insulating layer covers the substrate and the active layer, the first gate electrode is disposed on a side of the first gate insulating layer away from the substrate, and the interlayer dielectric layer covers the first gate electrode and the first gate insulating layer.

9. The display panel of claim 2, wherein, The thickness of the first sub-active layer and the third sub-active layer is less than or equal to 15 nanometers, and the thickness of the second sub-active layer is between 10 nanometers and 90 nanometers.

10. The display panel of claim 1, wherein, The display panel further comprises: a passivation layer disposed on the interlayer dielectric layer; a contact electrode disposed on the passivation layer, one end of the contact electrode being connected to the drain electrode; a planarization layer disposed on the passivation layer; an anode disposed on the planarization layer, the other end of the contact electrode being connected to the anode; a pixel definition layer disposed on the planarization layer and covering the anode; a light-emitting layer disposed in an opening of the pixel definition layer; a cathode disposed on the light-emitting layer.

11. A manufacturing method of a display panel, comprising: The manufacturing method of the display panel comprises the following steps: providing a substrate; forming a first gate electrode on the substrate; forming a first gate insulating layer on the substrate; forming an active layer on the substrate, the active layer and the first gate electrode being disposed in different layers, the active layer at least comprising a first sub-active layer and a second sub-active layer disposed in layers, the second sub-active layer being disposed on a side of the first sub-active layer away from the substrate, the number of gallium atoms in the first sub-active layer being greater than the number of gallium atoms in the second sub-active layer; wherein the material of the first sub-active layer comprises indium gallium zinc oxide, and the ratio of the number of indium atoms, the number of gallium atoms and the number of zinc atoms in the first sub-active layer is any one of indium: gallium: zinc = 0.1:1:0.2, 0.4:1:0.2, 0.3:1:0.3 or 0.1:1:0.8; forming an interlayer dielectric layer on the substrate; forming a first via hole and a second via hole on the interlayer dielectric layer; forming a source electrode and a drain electrode on the substrate, the source electrode being electrically connected to the active layer through the first via hole, and the drain electrode being electrically connected to the active layer through the second via hole; wherein the step of forming an active layer on the substrate comprises: forming indium gallium zinc oxide on the substrate and performing nitrogen doping on the indium gallium zinc oxide to form the first sub-active layer; forming indium gallium zinc oxide on the first sub-active layer to form the second sub-active layer.

12. A manufacturing method of a display panel, comprising: The manufacturing method of the display panel comprises the following steps: providing a substrate; Forming an active layer on the substrate, the active layer at least comprising a first sub-active layer and a second sub-active layer arranged in a stack, the second sub-active layer being arranged on a side of the first sub-active layer away from the substrate, an atomic number of gallium in the first sub-active layer being greater than an atomic number of gallium in the second sub-active layer; wherein a material of the first sub-active layer comprises indium gallium zinc oxide, and wherein a ratio of an atomic number of indium, an atomic number of gallium and an atomic number of zinc in the first sub-active layer is any one of indium: gallium: zinc = 0.1:1:0.2, 0.4:1:0.2, 0.3:1:0.3 or 0.1:1:0.8; Forming a first gate insulating layer on the active layer; Forming a first gate electrode on the first gate insulating layer, the first gate electrode and the active layer being arranged in different layers; Forming an interlayer dielectric layer on the first gate electrode; Forming a first via hole and a second via hole on the interlayer dielectric layer; Forming a source electrode and a drain electrode on the substrate, the source electrode being electrically connected to the active layer through the first via hole, and the drain electrode being electrically connected to the active layer through the second via hole; wherein The step of forming an active layer on the substrate comprises: forming indium gallium zinc oxide on the substrate, and performing nitrogen doping on the indium gallium zinc oxide to form the first sub-active layer; forming indium gallium zinc oxide on the first sub-active layer to form the second sub-active layer.

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