A FIR filter with counting function

Abstract

The present invention discloses an FIR filter with an automatic counting function, which includes a read-write control module, a filter calculation module, a data cache space and a filter coefficient memory; the read-write control module is used to read out the data to be filtered from the data cache space in sequence according to the relationship between the amount of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, using a read address generated by counting, and transmit the read data to be filtered to the filter calculation module; the filter calculation module is used to control the data to be filtered output by the data cache space and the filter coefficient output by the filter coefficient memory to perform filter calculation; wherein the filter calculation method is matched with the relationship between the amount of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter.

Description

Technical Field

[0001] The present invention relates to the technical field of finite impulse response filters, and in particular to an FIR filter with a counting function. Background Art

[0002] Among digital filters, the FIR (Finite Impulse Response) filter is a finite-length unit pulse impulse response digital filter and is the most basic component in digital signal processing systems. It can have strict linear phase-frequency characteristics while ensuring arbitrary amplitude-frequency characteristics. At the same time, its unit sampling response is finite length. Therefore, FIR filters are widely used in communications, image processing, pattern recognition and other fields.

[0003] The order of an FIR filter refers to the number of harmonics filtered; the length of an FIR filter reflects the frequency band of the filter; the sum of the FIR filter order and the value 1 equals the number of FIR filter coefficients, which is also equal to the number of filter taps. The number of FIR filter taps is the abbreviation for the number of filter taps. A tap is a coefficient or delay pair in an FIR filter. The number of FIR taps is used to indicate the storage space required for the filter, the number of calculations required, and the amount the filter can filter out. In practice, more taps mean more stopband attenuation, less ripple, narrower filtering, and so on. The passband of a filter represents the signal frequency components that can pass through the filter without attenuation; the stopband of a filter represents the signal frequency components attenuated by the filter.

[0004] When used in audio processing products such as analog-to-digital converters and digital receivers, FIR (Finite Impulse Response) filters are used to downconvert analog front-end signals to lower-frequency digital signals, or upconvert analog-to-digital signals to higher-frequency digital signals.

[0005] Noise is filtered and sampled signals are extracted to achieve signal filtering processing to obtain a low sampling rate or high sampling rate signal with higher signal quality for audio decoding, adaptive processing, etc. to achieve down-conversion or up-conversion. In the above process, the FIR filter transmits data serially. For an N-order FIR filter, each data read from its internal buffer is related to the previous N-1 data sequences from the same buffer that need to be filtered. The FIR filters in the existing technology often ignore the storage space capacity. In order to overcome the problem of inserted noise signals, the existing technology will control the data sequences involved in the calculation between different clock cycles to periodically suspend transmission, but this will affect the continuity or correlation between the new data and the old data, making it difficult to filter and process effective results from the effective data. Summary of the Invention

[0006] To address the above technical deficiencies, the present invention discloses an FIR filter with an automatic counting function, which utilizes the change in the count value of the relevant read address to perform an effective extraction filtering function on the filtered data to obtain accurate filtering results. The specific technical solution is as follows:

[0007] An FIR filter with an automatic counting function, the FIR filter includes a read-write control module, a filter calculation module, a data cache space and a filter coefficient memory; the read-write control module is used to control the writing of the to-be-filtered data input to the FIR filter into the data cache space, and to count and generate a read address; the read-write control module is used to read out the to-be-filtered data from the data cache space in sequence according to the relationship between the number of to-be-filtered data written into the data cache space and the transposition enable count threshold of the FIR filter, and transmit the read to-be-filtered data to the filter calculation module; the filter coefficient memory ... After reading the data to be filtered, the required filter coefficients are output to the filtering calculation module in sequence according to the order in which the read-write control module reads the data to be filtered from the data cache space; the filtering calculation module is used to control the data to be filtered output by the data cache space and the filter coefficients output by the filter coefficient memory to perform filtering calculation, wherein, when the filtering calculation module performs a filtering calculation, the read-write control module continues to control the data to be filtered newly input to the FIR filter to be written into the data cache space but does not participate in the filtering calculation; wherein, the filtering calculation method is to match the size relationship between the number of data to be filtered written into the data cache space and the transpose enable count threshold of the FIR filter.

[0008] Furthermore, the FIR filter is also provided with a system clock source for counting and generating system clock cycles; wherein, the time consumed for writing a piece of data to be filtered is configured to be equal to one system clock cycle, and the time consumed for reading a piece of data to be filtered is configured to be equal to one system clock cycle; wherein, the number of pieces of data to be filtered written into the data cache space is equal to the number of pieces of data to be filtered sampled from the outside by the FIR filter.

[0009] Furthermore, the read-write control module also includes a reference address counter; the reference address counter is used to perform a self-increment operation and generate a reference address every time two data to be filtered are written to the data cache space, triggering the read-write control module to use the reference address to read the data to be filtered from the data cache space, wherein the reference address is the first read address that needs to be traversed in the data cache space to start the current filtering calculation; the change value of the count value generated by the self-increment operation of the reference address counter is a value of 2; when the filtering calculation module outputs a filtering result, it is determined that the FIR filter has passed a filtering cycle since the two data to be filtered were written, and it is determined that only one filtering calculation is completed in one filtering cycle; wherein the decimation rate of the FIR filter is 2 times, or the interpolation rate of the FIR filter is 2 times; wherein, while performing a filtering calculation in the current filtering cycle, new data to be filtered is allowed to continue to be written to the data cache space to start the next filtering cycle, so as to achieve a timing interval in which two adjacent filtering cycles partially overlap.

[0010] Furthermore, when the amount of to-be-filtered data written into the data cache space is represented by a change in a count value of a reference address counter, the transposition enable count threshold of the FIR filter is represented by the number of taps of the FIR filter.

[0011] Furthermore, the method of using the read address to read out the data to be filtered from the data cache space in sequence according to the size relationship between the number of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, and transmitting the read data to be filtered to the filtering calculation module includes: when the read-write control module determines that the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the read-write control module is used to read out the data to be filtered in the pre-read address from the data cache space and transmit it to the filtering calculation module; wherein the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; wherein the pre-read address is obtained by counting starting from a corresponding reference address in each filtering cycle; the reference address in a filtering cycle is the first pre-read address participating in the read operation in the filtering cycle.

[0012] Furthermore, the read-write control module includes a pre-address counter and a read address selector; when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the read address selector selects the pre-address counter to generate a pre-read address and output it to the data cache space to read the data to be filtered in the corresponding address; the pre-address counter is used to, when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, start from the reference address in the current filtering cycle and perform a self-decrement operation in each system clock cycle, and then trigger the read-write control module to read the data to be filtered from the pre-address obtained in each self-decrement operation, and then transmit it to the filtering calculation module in sequence; wherein, each time the pre-address counter decrements, the change in the count value generated is a value of 1, and a pre-address read address is obtained after each self-decrement operation; the initial count value of the pre-address counter in each filtering cycle is the reference address generated by the reference address counter in the corresponding filtering cycle.

[0013] Furthermore, when the number of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address set by the FIR filter, perform a self-add operation on the starting storage address, and then output the filter coefficient in the storage address obtained by the self-addition to the filtering calculation module until the address offset of the storage address obtained by the self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1, and then record the latest storage address as the intermediate calculation storage address, and then perform a self-decrement operation on the intermediate calculation storage address, and then output the filter coefficient in the storage address obtained by the self-decrement to the filtering calculation module. The filter coefficients are output to the filtering calculation module until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1, and the process is repeated until the number of filter coefficients output from the filter coefficient memory in a current filtering cycle is equal to the number of to-be-filtered data participating in the filtering calculation in the current filtering cycle; wherein the number of taps of the FIR filter is an odd number; wherein, in the process of performing a self-addition operation on the starting storage address, each time a self-addition operation is performed, the storage address increases by a value of 1; and in the process of performing a self-decrement operation on the intermediate calculation storage address, each time a self-decrement operation is performed, the storage address decreases by a value of 1.

[0014] Furthermore, when the number of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, within each filtering cycle, start from the starting storage address matched by the FIR filter, perform a self-addition operation on the starting storage address, and then output the filter coefficient from the storage address obtained by the self-addition to the filtering calculation module, until the address offset of the storage address obtained by the self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 2, and then record the latest storage address as the intermediate calculation storage address, and then perform a self-decrement operation on the intermediate calculation storage address, and then output the filter coefficient from the storage address obtained by the self-decrement to the filtering calculation module, until the self-decrement operation is completed. The address offset of the obtained storage address relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter and the value 2, and the process is repeated until the number of filter coefficients read from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered participating in the filtering calculation in the current filtering cycle; wherein, the number of taps of the FIR filter is an even number; the filtering calculation module continuously reads out two identical filter coefficients from the intermediate calculation storage address; wherein, in the process of performing a self-increment operation on the starting storage address, each time the self-increment operation is performed, the address indicated by the storage address increases by a value of 1; in the process of performing a self-decrement operation on the intermediate calculation storage address, each time the self-decrement operation is performed, the address indicated by the storage address decreases by a value of 1.

[0015] Furthermore, the filtering calculation module is used to control the multiplication of the data to be filtered output by the data cache space and the filter coefficients in the same reading order output by the filter coefficient memory when the number of data to be filtered written into the data cache space is less than or equal to the transpose enable count threshold of the FIR filter, and input the results into the adder for accumulation processing to obtain the processed filtering results within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by time-sharing multiplexing of a multiplier; wherein, the filtering calculation module includes an adder and a multiplier.

[0016] Furthermore, the method of sequentially reading the data to be filtered from the data cache space using a read address according to the size relationship between the number of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, and transmitting the read data to be filtered to the filtering calculation module includes: when the read-write control module determines that the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the read-write control module is used to configure the reference address generated by the reference address counter as the first folding read address according to the counting timing of the reference address counter, and configure the sum of the reference address and the value 1 as the second folding read address; the read-write control module is also used to configure the sum of the first folding read address and the second folding read address as the post-read address, and read the data to be filtered in the post-read address from the data cache space according to the counting timing of the reference address counter, and transmit it to the filtering calculation module; wherein the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter.

[0017] Furthermore, the read-write control module includes a first folding address counter and a second folding address counter; when the amount of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the first folding address counter is used to perform a self-decrement operation on the first folding read address in each filtering cycle to generate a new first folding read address, thereby triggering the read-write control module to read the data to be filtered from the first folding read address obtained by each self-decrement operation until the number of self-decrement operations reaches a first preset folding sampling number, while still allowing new data to be filtered to be written into the data cache space; when the amount of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the second folding address counter is further used to perform a self-increment operation on the second folding read address in each filtering cycle to generate a new second folding read address, thereby triggering the read-write control module to read the data to be filtered from the second folding read address obtained by each self-increment operation until the number of self-increment operations reaches a second preset folding sampling number, while still allowing new data to be filtered to be written into the data cache space.

[0018] Furthermore, the first folding address counter is used to perform a self-decrement operation on the first folding read address once every two consecutive system clock cycles to obtain a new first folding read address, and these two consecutive system clock cycles are recorded as a folding address read cycle; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, under the control of the read-write control module, within the folding address read cycle, the data to be filtered in the first folding read address is read to the filtering calculation module, and the data to be filtered in the second folding read address is read to the filtering calculation module; wherein, the second folding address counter is used to perform a self-increment operation once under the folding address read cycle to achieve obtaining a new second folding read address every two consecutive system clock cycles.

[0019] Furthermore, the read-write control module also includes an address adder and a read address selector; the address adder is used to add the second folding read address generated by the second folding address counter and the first folding read address generated by the first folding address counter within the folding address read cycle to generate a post-read address within the folding address read cycle; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, the read address selector selects the post-read address generated by the address adder and outputs it to the data cache space, so as to play the role of reading two data to be filtered in the corresponding addresses within the folding address read cycle.

[0020] Furthermore, when the amount of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, before the read-write control module determines to configure the reference address as the first folding read address, if the read-write control module determines that the reference address is equal to the filtering starting address, the filtering target address is updated to the reference address, and the updated reference address is configured as the starting address of the first folding read address, and then the first folding address counter is used to perform a self-decrement operation on the first folding read address starting from the starting address of the first folding read address; wherein, the change value of the count value generated by the self-decrement operation of the first folding address counter once is a value of 1; When the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, before the read-write control module determines to configure the reference address as the second folding read address, if the read-write control module determines that the reference address is equal to the filtering target address, the filtering starting address is updated to the reference address, and then the sum of the updated reference address and the value 1 is configured as the starting address of the second folding read address. Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address, wherein the change in the count value generated by the self-increment operation of the second folding address counter is a value of 1.

[0021] Furthermore, the process of the first folding address counter performing a self-decrement operation on the first folding read address includes: configuring the starting address of the first folding read address as the first folding read address, and whenever the first folding read address is decremented to the filtering starting address, updating the filtering target address to the first folding read address in the next system clock cycle, so that the first folding read address implements address loop traversal within the address range limited by the number of taps of the FIR filter; then the first folding address counter continues to perform a self-decrement operation on the first folding read address; the process of the second folding address counter performing a self-increment operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is added to the filtering target address, updating the filtering starting address to the second folding read address in the next system clock cycle, so that the second folding read address implements address loop traversal within the address range limited by the number of taps of the FIR filter; then the second folding address counter continues to perform a self-increment operation on the second folding read address.

[0022] Furthermore, when the count value of the reference address counter is the difference between the number of taps of the FIR filter and the numerical value 2, the read-write control module updates the filter starting address to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the filter starting address to the reference address; when the count value of the reference address counter is the difference between the number of taps of the FIR filter and the numerical value 1, the read-write control module updates the sum of the filter starting address and the numerical value 1 to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the sum of the filter starting address and the numerical value 1 to the reference address.

[0023] Furthermore, in each folding address reading cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read; wherein, the filtering target address is an address pre-configured in the data cache space, which is the address with the largest sequence among the addresses participating in the reading operation in each filtering cycle; wherein, the filtering starting address is an address pre-configured in the data cache space, which is the address with the smallest sequence among the addresses read in each filtering cycle; wherein, the difference between the filtering target address and the filtering starting address is equal to the difference between the number of taps of the FIR filter and the value 1.

[0024] Furthermore, the number of taps of the FIR filter is an odd number; within one filtering cycle or one filtering calculation, when the second preset folding sampling number is greater than the first preset folding sampling number, the first folding read address stops changing in advance of the second folding read address; within one filtering cycle or one filtering calculation, when the second preset folding sampling number is less than the first preset folding sampling number, the second folding read address stops changing in advance of the first folding read address.

[0025] Furthermore, when the number of taps of the FIR filter is an even number, the second preset folding sampling number is equal to the first preset folding sampling number.

[0026] Furthermore, when the amount of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to perform a self-addition operation on the starting storage address once every two system clock cycles, starting from the starting storage address matched by the FIR filter, within each filtering cycle, so that the address corresponding to the starting storage address performs a self-addition operation once every two system clock cycles, and then the filter coefficients in the storage address obtained by the self-addition operation are read out from the filter coefficient memory in sequence to the filtering calculation module; when the number of taps of the FIR filter is an odd number, the address offset of the storage address obtained by the self-addition operation relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1, and then the latest storage address obtained is recorded as the intermediate calculation storage address; wherein, in the process of performing the self-addition operation on the starting storage address, each self-addition operation generates a storage address, and the change value of the storage address generated by two adjacent self-addition operations is the value 1.

[0027] Furthermore, the filtering calculation module is used to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, first control the to-be-filtered data in the first folding read address output by the data cache space and the to-be-filtered data in the second folding read address output by the data cache space to be added in each folding address read cycle; then multiply the result of the addition with the filter coefficients in the same reading order output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address. number; wherein, in each filtering cycle, the multiplication operation is implemented by a multiplier in time-sharing multiplexing; the filtering calculation module includes an adder and a multiplier; the transpose enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; when the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, if the number of taps of the FIR filter is an odd number, the filter coefficient in the intermediate calculation storage address is multiplied with the data to be filtered in the first folded read address output by the data cache space in the same reading order, and then the multiplication result is input into the adder for accumulation processing to obtain the processed filtering result in the corresponding filtering cycle.

[0028] Furthermore, when the amount of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to perform a self-addition operation on the starting storage address once every two system clock cycles, starting from the starting storage address matched by the FIR filter, within each filtering cycle, so that the address corresponding to the starting storage address performs a self-addition operation once every two system clock cycles, and then the filter coefficients in the storage address obtained by the self-addition operation are read out from the filter coefficient memory in sequence to the filtering calculation module; when the number of taps of the FIR filter is an even number, the address offset of the storage address obtained by the self-addition operation relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 2, and then the latest storage address obtained is recorded as the intermediate calculation storage address; wherein, in the process of performing the self-addition operation on the starting storage address, each self-addition operation generates a storage address, and the change value of the storage address generated by two adjacent self-addition operations is the value 1.

[0029] Furthermore, the filtering calculation module is used to control the addition of the data to be filtered in the first folding read address output by the data cache space and the data to be filtered in the second folding read address output by the data cache space in each folding address read cycle when the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter; then multiply the result of the addition with the filter coefficients in the same reading order output by the filter coefficient memory; and then input the multiplication result into the adder for accumulation processing, and repeat this in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address; wherein, each filtering cycle In the embodiment, the multiplication operation is realized by a multiplier in time-sharing multiplexing; the filtering calculation module includes an adder and a multiplier; the transpose enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; when the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, if the number of taps of the FIR filter is an even number, the data cache space is controlled to output the sum of the data to be filtered in the first folding read address and the data to be filtered in the second folding read address within the same folding address read cycle, and multiply the filter coefficient in the intermediate calculation storage address, and then input the multiplication result into the adder for accumulation processing to obtain the processed filtering result within the corresponding filtering cycle.

[0030] Compared with the prior art, the present invention divides filtering calculation stages corresponding to the input number of data to be filtered based on the relationship between the number of data to be filtered written into the data cache space and the transposition enable counting threshold of the FIR filter, and adopts different counting methods in different filtering calculation stages to generate read addresses that are adapted to the filtering calculation of first addition and then multiplication or first multiplication and then addition under the current data amount, thereby meeting the correlation between the data to be filtered participating in the filtering calculation under different data input amounts. The read addresses generated by the counting of the present invention support loop changes within the address range limited by the number of taps, thereby ensuring the continuity of the data to be filtered by overwriting the old addresses with new data. On the other hand, the change of the read address as the counting starting point in each filtering calculation or each filtering cycle is related to the decimation rate or interpolation rate of the FIR filter, so that the self-increment operation of the read address in the same filtering cycle and / or the self-decrement operation of the read address in the same filtering cycle executes the filtering calculation within the filtering cycle. This can support the automatic counting and periodic filtering calculation requirements of FIR filters of different orders, except for half-band filters, and simultaneously extract valid data from the real-time input data to be filtered and filter to obtain valid filtering results. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A module connection block diagram of an FIR filter with an automatic counting function is disclosed in one embodiment of the present invention.

[0032] Figure 2 It is a schematic diagram of the structural principle of a counter inside a read-write control module disclosed in another embodiment of the present invention.

[0033] Figure 3 This is a diagram showing the dynamic changes in data flow of a 5-tap FIR filter.

[0034] Figure 4 This is a schematic diagram of the dynamic changes in data flow of a 6-tap FIR filter. DETAILED DESCRIPTION

[0035] The following describes the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The present invention provides drawings to further illustrate the various embodiments. These drawings form part of the disclosure and are primarily used to illustrate the embodiments and, in conjunction with the relevant descriptions in the specification, to explain the operating principles of the embodiments.

[0036] Unless otherwise defined, the technical terms or scientific terms involved in the present invention should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "the" and the like involved in this application do not indicate a quantitative limitation and may represent the singular or the plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions, such as: a process, method, system product or device that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The terms "first", "second", "third" and the like involved in this application are merely used to distinguish similar correspondences and do not represent a specific order for the objects.

[0037] One embodiment of the present invention discloses an FIR filter with an automatic counting function, which can be used for extracting and filtering mono or dual-channel audio signals of audio equipment according to the filtering algorithm requirements of the actual application field (audio or video). Specifically, it can perform filtering calculations on the original input data while inputting a new data. It is an FIR filter that supports a pipeline structure. Figure 1As shown, the FIR filter includes a read-write control module, a filter calculation module, a data cache space, and a filter coefficient memory. The FIR filter is pre-configured with the number of taps, decimation rate, and interpolation rate, and supports external software parameters or program intervention and modification. Specifically, the FIR filter is provided with a dedicated parameter configuration register for storing relevant performance parameters of various types of FIR filters, including but not limited to the bit width of input and output data, the bit width of the filter coefficient, the number of taps and order of the FIR filter, the number of filter coefficients, the length of the filter, the decimation rate of the filter, the interpolation rate (interpolation multiple), the filtering period required for a single filtering operation, the effective time point of the chip select signal, the high time point of the enable signal, the starting address of the read address of the filter coefficient memory or the starting reading time point, that is, determining the start and end time points and corresponding address intervals for reading and calculating the filter coefficients; wherein the number of taps of the FIR filter is equal to the sum of the order of the FIR filter and the value 1. In the present invention, the bit width of each data to be filtered written into the data cache space is pre-configured by a specific register, and the bit width occupied by each data to be filtered is less than or equal to the maximum bit width allowed to be read and written by the data cache space.

[0038] In this embodiment, the read / write control module is used to generate the read addresses required by the FIR filter for filtering calculations. These read addresses can be used to limit the address range for reading the data cache space to meet the tap number requirement of the FIR filter. During hardware implementation, the read addresses are counted by a dedicated counter at the same clock or divided by frequency depending on the actual data transmission rate. It is worth noting that the starting address and starting time of the read operation need to be determined before reading the data. The data cache space is implemented using SRAM, that is, static random-access memory (SRAM).

[0039] A read-write control module is used to control the writing of the data to be filtered of the input FIR filter into the data cache space. Specifically, the read-write control module, as the data read-write logic, can write the input data into the data cache space in the corresponding clock cycle according to the sampling rate or interpolation rate of the FIR filter; at the same time, it can count and generate the read address required for the filtering calculation according to the number of taps of the FIR filter and the amount of data to be filtered written in real time, and transmit the data previously written in the read address to the filtering calculation module, wherein, when the filtering calculation module performs a filtering calculation on a batch of data to be filtered, it allows the read-write control module to continue to control the writing of a new batch of data to be filtered into the data cache space.

[0040] like Figure 1As shown, port I1 of the read-write control module is used to transmit a clock signal to the data cache space, and is configured as a driving clock signal for reading data in an associated read address in the data cache space; port I2 of the read-write control module is used to transmit a chip select signal to the data cache space, and the chip select signal is used to start selecting an address interval in the data cache space that needs to be read or enter a working state; port I3 of the read-write control module is used to transmit an enable signal to the data cache space, and the enable signal is used to distinguish between read enable and write enable; port I4 of the read-write control module is used to transmit an associated read address generated by the read-write control module to the data cache space;

[0041] The port I5 of the read-write control module is used to write the data to be filtered into the data cache space; the port O6 of the read-write control module is used to receive the data to be filtered read from the data cache space. The data read from the data cache space will be transmitted to the filtering calculation module by other ports of the read-write control module. The data transmitted to the filtering calculation module, such as Figure 1 fir_rdata is shown below.

[0042] The read / write control module is configured to sequentially read the data to be filtered from the data cache space and provide it to the filtering calculation module using a read address generated by counting, based on a relationship between the amount of data to be filtered written into the data cache space and a transposition enable count threshold of the FIR filter, and transmit the read data to be filtered to the filtering calculation module. When determining the relationship between the amount of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, the amount of data to be filtered written into the data cache space is equivalent to the amount of data to be filtered input into the FIR filter, excluding newly written data to be filtered by the filtering calculation module during a filtering calculation. Determining the relationship between the amount of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter is to detect whether the amount of data to be filtered input into the FIR filter meets a certain count threshold, and is used to determine the filtering calculation method that should be currently adopted by the FIR filter. Compared with the prior art of extracting and filtering the same batch of data, the amount of computation is reduced, especially when the number of taps is large. It should be noted that the relationship between the amount of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter is determined by a specific enable signal and received by the read-write control module, corresponding to Figure 2The specific enable signal Thr_sel can be obtained by the read / write control module by counting the amount of external data input to the FIR filter or the amount of data written to the data cache space. Optionally, the transposition enable count threshold of the FIR filter can be the number of taps of the FIR filter, or a value greater than the number of taps of the FIR filter, or a value smaller than the number of taps of the FIR filter.

[0043] The filtering calculation module is used to control the filtering calculation of the data to be filtered output by the data cache space and the filter coefficients output by the filter coefficient memory. Specifically, in the filtering calculation performed by the FIR filter, the calculation method under different filtering stages is divided according to the relationship between the number of data to be filtered written into the data cache space and the transpose enable count threshold of the FIR filter. The time and resources consumed by the calculation process under different filtering stages are different. The filter coefficient memory is also used to store the filter coefficients required by the FIR filter that needs to be reused, wherein the filter coefficient memory can be implemented using ROM, that is, using a read-only memory (ROM). Figure 1 As shown, the filter coefficient memory transmits the filter coefficient to the filtering calculation module through its port rom_out.

[0044] The filter coefficient memory is used to output the required filter coefficients to the filter calculation module in sequence after the read-write control module starts to read the data to be filtered from the data cache space, starting from the starting storage address corresponding to the FIR filter, in accordance with the order in which the read-write control module reads the data to be filtered from the data cache space. It is worth noting that the order in which the filter calculation module reads the storage addresses of the filter coefficients from the filter coefficient memory is the same as the order in which the read-write control module reads the cache addresses of the data to be filtered from the data cache space, so that the data to be filtered output from the data cache space is at the corresponding address position (odd or even) output from the filter coefficient memory. The address position identified by the number, which involves the filter coefficient of the base address which is pre-configured and obtained by self-increment or self-subtraction on this basis, can perform a filtering calculation once within the same filtering cycle. It should be noted that, in this embodiment, the time consumed for performing a filtering calculation on a piece of input data to be filtered is one filtering cycle, but the data to be filtered output by the data cache space and the filter coefficient output by the filter coefficient memory are not necessarily output synchronously, but it can be guaranteed that a complete filtering calculation is performed within the same filtering cycle; and when the filtering calculation module performs a filtering calculation, the read-write control module continues to control the new input FIR filter data to be filtered to be written into the data cache space but does not participate in the filtering calculation.

[0045] Compared with the prior art, the embodiment of the present invention divides the filtering calculation stage corresponding to the input number of the data to be filtered according to the size relationship between the number of data to be filtered written into the data cache space and the transpose enable counting threshold of the FIR filter, and adopts different counting methods in different filtering calculation stages to generate a reading address for the filtering calculation of adding first and then multiplying or multiplying first and then adding that is suitable for the current data volume, so as to meet the correlation between the data to be filtered participating in the filtering calculation under different data input volumes.

[0046] In some embodiments, when the amount of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, a high-level folding selection signal is generated, corresponding to Figure 2 The selection signal Thr_sel=1, the data path of the corresponding counter in the read-write control module is selected to generate the corresponding read address; when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, a low-level folding selection signal is generated, corresponding to Figure 2The selection signal Thr_sel=0, the data path of the corresponding counter in the read-write control module is selected to generate another read address; wherein, the reading timing of the read-write control module for reading the data cache space is determined by the counting timing of the specific counter selected by the FIR filter.

[0047] In this embodiment, the FIR filter is further provided with a system clock source for counting and generating system clock cycles, corresponding to Figure 1 The clock signal output by port I1 of the read-write control module in this embodiment is designed as the counting clock of the FIR filter. The clock beats generated by counting it are used as the system clock period, and frequency division is also supported to realize frequency division processing of the counting clock. Among them, the time consumed for writing a piece of data to be filtered is configured as a system clock cycle, and the time consumed for reading a piece of data to be filtered is configured as a system clock cycle; in this embodiment, the FIR filter is used to configure the time consumed for writing a piece of data to be filtered input from the external input into the data cache space to be equal to one system clock cycle, that is, under the control of the read-write control module, excluding other delay operations, during the process of writing a piece of data to be filtered into the data cache space, a write clock cycle is set to be equal to one system clock cycle; the FIR filter is also used to configure the time consumed for reading a piece of data to be filtered from the data cache space to be equal to one system clock cycle, that is, under the control of the read-write control module, excluding other delay operations, during the process of reading a piece of data to be filtered from the data cache space, a read clock cycle is set to be equal to one system clock cycle; wherein, a piece of data to be filtered is information of a sampling point sampled from the outside by the FIR filter, and in this embodiment, it is also data read from the data cache space by the read-write control module. The amount of data to be filtered written into the data cache space is equal to the amount of data to be filtered sampled from the outside by the FIR filter, which is the amount of data to be filtered required for actually performing one filtering calculation.

[0048] Based on the above embodiment, the read-write control module further includes a reference address counter, which can be specifically provided in the read-write control module as a counting logic component for obtaining the starting read address of the data to be filtered required for each filtering calculation; the reference address counter is used to perform a self-increment operation each time two data to be filtered are written to the data cache space from the outside of the FIR filter, or when the filtering calculation module starts a filtering calculation, i.e., perform a self-increment operation on the count value of the reference address counter and generate a reference address, wherein the change in the count value generated by the self-increment operation of the reference address counter is a value of 2, i.e., it is counted once plus two, which meets the requirement of twice the decimation rate or twice the interpolation rate of the FIR filter. Specifically, in this embodiment, the decimation rate of the FIR filter is set to 2, so that in some embodiments, the address offset between the reference addresses obtained in two adjacent filtering cycles is equal to the value of 2, because in the corresponding embodiment, the address offset between the reference addresses obtained in two adjacent filtering cycles can be set to be equal to the decimation rate or interpolation rate of the FIR filter; then, the filtering calculation module is triggered to use the reference address to output all the data from the data cache space. The filtering calculation module performs filtering calculation on the data to be filtered; and when the filtering calculation module calculates a filtering result, it is determined that the FIR filter has passed one filtering cycle since writing the two data to be filtered and has completed one filtering calculation, including two system clock cycles required to write the two data to be filtered, the total cycle for sequentially reading the data to be filtered from the data cache space (the specific value is related to the number of data to be filtered that need to be read from the data cache space in one filtering calculation), and the cycle required for the multiplication and accumulation calculation included in the filtering calculation. In this embodiment, one filtering cycle is set to be greater than two system clock cycles. Therefore, in this embodiment, the length of the read, write, and calculation cycles is set to ensure that a complete filtering calculation is performed, thereby obtaining a valid filtering result. Therefore, the filtering calculation module outputs a filtering result after each filtering cycle. That is, in this embodiment, when the filtering calculation module outputs a filtering result, it is determined that the FIR filter has passed one filtering cycle since writing the two data to be filtered, and that only one filtering calculation is completed within one filtering cycle. The reference address is the read address of the first data to be filtered output by the data cache space within the filtering cycle.It is worth noting that while performing a filtering calculation in the current filtering cycle, it is allowed to continue writing new data to be filtered into the data cache space to start the next filtering cycle. The FIR filter disclosed in this embodiment is composed of a digital logic circuit. The pipeline structure of the FIR filter determines that the reading, writing and calculation of the input data to be filtered are performed synchronously, so as to achieve a timing interval in which two adjacent filtering cycles partially overlap. It should be supplemented that the initial count value set in the reference address counter can be a value of 0 or a value of 1. This embodiment chooses to configure the initial count value set in the reference address counter to a value of 0 for explanation. In summary, this embodiment determines that the continuous cycles and counting rules required for a filtering calculation are required under the condition that the FIR filter has a 2x decimation rate or a 2x interpolation rate, which adapts to the effective division of the cycles consumed by the filtering calculation of the FIR filter.

[0049] Preferably, when the number of data to be filtered written into the data cache space is represented by the change value of the count value of the reference address counter, based on the timing rule that the reference address counter adds two counts every time two data to be filtered are written, the transposition enable count threshold of the FIR filter is represented by the number of taps of the FIR filter, so that the size relationship between the transposition enable count threshold of the FIR filter and the number of data to be filtered written into the data cache space is equivalent to the size relationship between the number of taps of the FIR filter and the change value of the count value of the reference address counter, which facilitates the counting of the number of data to be filtered written into the data cache space. This preferred example is that in the application scenario where the number of taps of the FIR filter is odd or even, it is beneficial to use the reference address counter to accurately count the number of data to be filtered actually written into the data cache space in each filtering cycle.

[0050] Preferably, when the count value of the reference address counter is the difference between the number of taps of the FIR filter and the value 2, the read-write control module updates the filter starting address to the count value currently obtained by the reference address counter in the next system clock cycle, thereby updating the filter starting address to the reference address, and allowing the reference address counter to perform a self-increment operation starting from the updated reference address; it is worth noting that the update rule of the reference address is not affected by the relationship between the number of data to be filtered in the write data cache space and the transpose enable count threshold of the FIR filter; wherein, the filter starting address is an address pre-configured in the data cache space, and as the address with the smallest order among the addresses participating in the read operation in each filtering cycle, it can be represented by the value 0 or the value 1. In this preferred example, the filter starting address is set to the value 0. The reference address counter has an initial count value, which is the count value set before the reference address counter starts counting. In order to match Figure 4According to the description, under the premise that the number of taps of the FIR filter is an even number, this preferred embodiment sets the initial count value to the value 0, then the count value of the reference address counter can be incremented by the value 2 in each filtering cycle to the difference between the number of taps of the FIR filter and the value 2, then the read-write control module updates the filtering starting address to the count value currently obtained by the reference address counter in the next system clock cycle, so that the reference address counter has enough counting range to cover the valid address interval limited by the number of taps of the FIR filter (the number of address units included in the address interval is equal to the number of taps of the FIR filter), and also avoids the reference address counter from overflowing in the process of incrementing by the value 2 in each filtering cycle or avoids the read-write control module from reading data in an invalid address. On the other hand, under the premise that the number of taps of the FIR filter is an odd number, the initial count value of the reference address counter is configured to be 1, then the count value of the reference address counter can be incremented by 2 in each filtering cycle to the difference between the number of taps of the FIR filter and 2, and then the read-write control module updates the filtering starting address to the count value currently obtained by the reference address counter in the next system clock cycle, so that the reference address counter is adjusted to start incrementing again from the filtering starting address.

[0051] Preferably, when the count value of the reference address counter is the difference between the number of taps of the FIR filter and the value 1, the read-write control module will update the sum of the filter starting address and the value 1 to the count value currently obtained by the reference address counter in the next system clock cycle, and update the sum of the filter starting address and the value 1 to the reference address; wherein, the count value of the reference address counter can be understood as the reference address it generates; the filter starting address is an address pre-configured in the data cache space, and as the address with the smallest order among the addresses participating in the read operation in each filtering cycle, it can be represented by the value 0 or the value 1. In this preferred embodiment, it is set to the value 0. The initial count value of the reference address counter is the count value set before the reference address counter starts counting. In order to match Figure 3As explained above, under the premise that the number of taps of the FIR filter is an odd number, this preferred embodiment sets the initial count value to the value 0, and then the count value of the reference address counter can be incremented by the value 2 in each filtering cycle to the difference between the number of taps of the FIR filter and the value 1. Then, the read-write control module updates the value 1 to the current count value obtained by the reference address counter in the next system clock cycle, so that the reference address counter is adjusted to start incrementing again from the sum of the filtering starting point address and the value 1. This allows the reference address counter to have sufficient counting range to cover the valid address range defined by the number of taps of the FIR filter, and also prevents the reference address counter from reading data in an invalid address (outside the read address range defined by the number of taps of the FIR filter) during the process of incrementing by the value 2 in each filtering cycle.

[0052] On the other hand, under the premise that the number of taps of the FIR filter is an even number, the initial count value of the reference address counter is configured to be 1, then the count value of the reference address counter can be incremented by 2 in each filtering cycle to the difference between the number of taps of the FIR filter and 1, and then the read-write control module updates the value 1 to the current count value obtained by the reference address counter in the next system clock cycle, so that the reference address counter is adjusted to start incrementing again from the sum of the filtering starting address and the value 1.

[0053] In combination with the foregoing embodiment, it can be seen that the method of reading out the data to be filtered from the data cache space in sequence using the read address according to the size relationship between the number of data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, and transmitting the read data to be filtered to the filtering calculation module includes: when the read-write control module determines that the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the read-write control module reads out the data to be filtered in the pre-read address from the data cache space in sequence and transmits it to the filtering calculation module; wherein the transposition enable count threshold of the FIR filter is preferably set to the number of taps of the FIR filter, so that this embodiment can use the difference between the number of taps of the FIR filter and the value 1 as the maximum count value to divide the read address and read cycle, so that the address counted by the relevant counter does not exceed the read address range limited by the number of taps of the FIR filter.

[0054] It should be noted that the pre-read address is obtained by counting from a reference address within each filtering cycle, specifically determined by the real-time count value of the reference address counter, and is counted once for each filtering calculation or each filtering cycle. A reference address within each filtering cycle is the first pre-read address to participate in a read operation within that filtering cycle, so that the data to be filtered in the pre-read address corresponding to the reference address is transmitted to the filtering calculation module according to the corresponding read timing. This divides the effective read address and the read data to be filtered of the read / write control module for each filtering calculation, ensuring that the input data is continuously acquired and used for continuous filtering calculations.

[0055] As an implementation method of an FIR filter with an odd number of taps, Figure 2 As shown, the read-write control module includes a pre-address counter and a read address selector; when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the read address selector enables the count value generated by the pre-address counter to be output to the data cache space, so as to read the data to be filtered in the corresponding address; specifically, when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, in some embodiments, the selection signal Thr_sel is set to a low level, and the data path between the pre-address counter and the port I4 of the read-write control module is enabled, so that the count value generated by the pre-address counter is output to the data cache space, so that the pre-address counter provides the pre-read address to the data cache space.

[0056] The pre-address counter is used to start from the reference address in the current filtering cycle, perform a self-decrement operation according to the system clock cycle, and then trigger the read-write control module to read the data to be filtered in the pre-read address after each self-decrement operation from the data cache space, and then transmit it to the filtering calculation module in sequence until the count value of the pre-address counter is reduced to a value of 0 or a value of 1 in the current filtering cycle; wherein, each time the pre-address counter is self-decremented, the change value of the count value generated is a value of 1, and a pre-read address is obtained after each self-decrement operation, which is achieved in a filtering calculation process as a cycle, and can also be achieved in the same filtering cycle. decremented to a value of 0 or 1; in view of the count values ​​generated by the pre-address counter in different filtering cycles, this embodiment configures the initial count value of the pre-address counter in each filtering cycle as the reference address generated by the reference address counter in a corresponding filtering cycle, that is, the reference address counter performs a self-increment operation once to generate a reference address in one filtering cycle, which serves as the initial count value (starting count value) required for the pre-address counter to perform multiple self-decrement operations (to output data in multiple consecutive pre-read addresses to the filtering calculation module) in order to assist the filtering calculation module in performing one filtering calculation in the filtering cycle.

[0057] In this embodiment, the initial count value set in the reference address counter is configured as 0, so the reference address set in the data cache space can be configured as 0. Since the pre-read address is counted from a reference address in each filtering cycle, that is, the pre-read address can be set as the reference address and is the first pre-read address to participate in the read operation in a filtering cycle or a filtering calculation process, the read-write control module can read the data to be filtered from address 0 in one filtering cycle, thereby improving the coverage rate of the address range of the read data. In this embodiment, in each filtering cycle, two consecutive system clock cycles are first used to sequentially write two data to be filtered into the data cache space, and then the data is read from the data cache space according to the corresponding read timing to the filtering calculation module for filtering calculation. When a filtering calculation is started, the reference address counter does not perform any counting operation in the same filtering cycle except for adding two to the count of the first two data to be filtered written. Instead, the count value is maintained until new data to be filtered is written and the next filtering cycle begins.

[0058] exist Figure 3In the embodiment of the present invention, when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the reference address may be when the number of data to be filtered written into the data cache space is less than or equal to 5 (the number of taps of the FIR filter is equal to 5, and the number of taps of the FIR filter is equal to the transposition enable count threshold of the FIR filter). Figure 3 The initial address of the first filter cycle (filter cycle numbered 1) is 0, the reference address of the second filter cycle (filter cycle numbered 2) is 2, and the reference address of the third filter cycle (filter cycle numbered 3) is 4. At this time, 5 data to be filtered have been written, and the order from the latest written to the first written is X5, X4, X3, X2 and X1.

[0059] exist Figure 3 In an embodiment of the present invention, when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, that is, when the number of data to be filtered written into the data cache space is less than or equal to 5 (the number of taps of the FIR filter is equal to 5, and the number of taps of the FIR filter is equal to the transposition enable count threshold of the FIR filter), the reference address is Figure 3 The initial address of the third filtering cycle (filtering cycle with serial number 2) is 4, which has reached the difference between the number of taps of the FIR filter and the value 1. If the reference address counter continues to perform self-increment operation on the currently obtained reference address (count value), the new reference address generated becomes the value 5. Under the premise that the initial count value set in the reference address counter is configured as the value 0, the number of addresses traversed is already 6, which exceeds the number of taps of the FIR filter. Therefore, the reference address of the fourth filtering cycle (filtering cycle with serial number 4) is configured as the value 1, and then after the fourth filtering cycle (filtering cycle with serial number 4), 7 data to be filtered have been written, from the newly written to the first written, they are X7, X6, X5, X4, X3, X2 and X1, where the smaller the i in Xi, the earlier it is written, but the later it is read.

[0060] In some embodiments, there is always a new data entry at address 0 of the data cache space. Figure 3 The window and occupies the first position of the window, in particular, Figure 3In the first filtering cycle, the outside of the FIR filter only writes one to-be-filtered data X1 to the data cache space. Accordingly, the reference address in the first filtering cycle is 0, which may be pre-configured by the read-write control module. When a filtering calculation is started, the filtering calculation module performs filtering calculation using the to-be-filtered data and outputs the filtering result y0. In the first filtering cycle, since only one to-be-filtered data is written, the reference address counter does not perform a counting operation, so the initial count value of the reference address counter is configured as the reference address, and further configured as the first pre-read address participating in the read operation in the filtering cycle or the filtering calculation process.

[0061] As a second embodiment of an FIR filter with an odd number of taps, the read-write control module includes a pre-address counter, which is used to start from the reference address corresponding to the current filtering cycle and perform a self-decrement operation according to the system clock cycle when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter. Specifically, the pre-address counter performs a self-decrement operation using the corresponding reference address converted in the read-write control module in the current filtering cycle. Optionally, before performing the first self-decrement operation, a delay period is required to allow the written data to be filtered to be stably cached in the data cache space; at the same time, the pre-decrement operation after each self-decrement operation is performed. The pre-read address is transmitted to the data cache space to trigger the read-write control module to read the data to be filtered from the pre-read address after each decrement operation in the data cache space, and then transmit it to the filter calculation module in sequence until the latest pre-read address is a value of 0 or a value of 1. In this embodiment, the initial count value set by the pre-address counter is the reference address, which can be a value of 0; the pre-address counter acts as a decrement counter. Each time the pre-address counter performs a decrement operation, the corresponding change in the count value is a value of 1, and the count value generated after each decrement operation is configured as the pre-read address, so that after the current decrement operation, a new pre-read address is obtained relative to the previous decrement operation. Therefore, the pre-address counter can traverse the data cache space one address unit at a time, with a value of 1 as the address offset step, specifically the address range defined by the number of taps of the FIR filter.

[0062] As a third implementation method of an FIR filter with an odd number of taps, in order to perform a filtering calculation, still in the implementation scenario where the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address matched by the FIR filter, perform a self-add operation on the starting storage address according to the system clock cycle, and then read the corresponding stored filter coefficients to the filtering calculation module in sequence according to the storage address obtained by self-addition, specifically, in each system clock cycle. The obtained storage address is added by one in the same system clock cycle, then in the same system clock cycle, the address offset step of the storage address is equal to the address offset step of the aforementioned pre-read address, and is kept changing under the same system clock source until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1; it should be noted that, in one filtering cycle, the reading order of the filter coefficients required for the same filtering calculation is the same as the reading order of the data to be filtered, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1. Then, the filter coefficient memory records the latest storage address as the intermediate calculation storage address, and then performs a self-decrement operation on the intermediate calculation storage address, and then reads the corresponding stored filter coefficients to the filter calculation module in sequence according to the storage address obtained by self-decrement, until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1, and repeats in sequence until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle (corresponding to the start of the current filtering calculation) is equal to the number of filter data to be filtered in the current filtering cycle, which may vary depending on the number of filtering calculations actually performed or the filtering cycle. It should be noted that in the process of performing the self-increment operation on the starting storage address, each self-increment operation triggers the address corresponding to the storage address to automatically increase by 1; in the process of performing the self-decrement operation on the intermediate calculation storage address, each self-decrement operation triggers the address corresponding to the storage address to automatically decrease by 1; wherein, the intermediate calculation storage address is the address with the largest order among the storage addresses of the filter coefficients set in the filter coefficient memory, that is, the tail address of the address range storing the corresponding filter coefficients.

[0063] exist Figure 3In the third filtering cycle, starting from the address position with the initial address being the value 4, from left to right, the data in the fifth row of boxes are sequentially the data to be filtered in the pre-read address after the self-decrement operation read by the read-write control module from the data cache space. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address position is the pre-read address obtained by the earlier self-decrement; the data in the squares closer to the right are read later, and the corresponding address position is the pre-read address obtained by the later self-decrement. Preferably, the data in one square is read in each system clock cycle. Similarly, the data in the sixth row of boxes are the filter coefficients in the storage addresses after the self-addition operation read from the filter coefficient memory, starting from the address position corresponding to the grid h1, that is, the starting storage address corresponding to the FIR filter. From left to right, the data in the grids closer to the left are read earlier, and the corresponding address positions are the storage addresses obtained by self-addition earlier; the data in the grids closer to the right are read later, and the corresponding address positions are the storage addresses obtained by self-addition later, until the self-addition reaches h3. At this time, the address position corresponding to the h3 square is offset from the address position corresponding to the h1 square by a value of 2, which is equal to half the difference between the number of taps of the FIR filter (value 5) and the value 1 (equal to the value 2). The filter coefficient memory configures the address position corresponding to the h3 square as the intermediate calculation storage address; then, starting from the h3 square, the intermediate calculation storage address is decremented until it reaches the h1 square. At this time, the address offset of the storage address obtained by the decrement relative to the intermediate calculation storage address is equal to The number of taps of the FIR filter (value 5) is half of the difference between the value 1 (equal to the value 2). At this time, in the sixth row of boxes, the filter coefficients h1, h2, h3, h2 and h1 read from left to right correspond exactly to the data to be filtered X5, X4, X3, X2 and X1 to be filtered in the fifth row of boxes participating in the filtering calculation, wherein X5 is the data to be filtered in the pre-read address read first, and X1 is the data to be filtered in the pre-read address read last; then the number of filter coefficients read from the filter coefficient memory in the third filtering cycle meets the number of data to be filtered participating in the filtering calculation in the third filtering cycle, and the filter coefficients in the storage address obtained by the self-addition operation before obtaining the intermediate calculation storage address and the filter coefficients in the storage address obtained by the self-subtraction operation after obtaining the intermediate calculation storage address constitute the symmetrical filter coefficients of the FIR filter, that is, the filter coefficients h1 and h2 read on the left and right sides of h3 constitute a set of symmetrical filter coefficients, so as to obtain a symmetrical filtering result in the current filtering calculation (in the third filtering cycle).

[0064] On the basis of the above embodiment, the filtering calculation module is used to control the multiplication of the data to be filtered output by the data cache space and the filter coefficients in the same reading order output by the filter coefficient memory when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, and input the result into the adder for accumulation processing to obtain a filtering result after processing within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by a multiplier in time-sharing multiplexing, minimizing the multiplier resources; wherein, under the premise that the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the number of multiplication operations within a filtering cycle is equal to the number of data to be filtered or the number of filter coefficients required for the current filtering calculation, but does not exceed the number of taps of the FIR filter. The filtering calculation module includes an adder and a multiplier, which constitute a calculation method of performing multiplication first and then performing addition. Corresponding to Figure 3 , the filtering result y4 obtained in the third filtering cycle is equal to the sum of the product of X5 and h1, the product of X4 and h2, the product of X3 and h3, the product of X2 and h2, and the product of X1 and h1, and the number of multiplication operations in the third filtering cycle is equal to 5. The transpose enable count threshold of the FIR filter is equal to the number of taps of the FIR filter.

[0065] As a fourth implementation method of an FIR filter with an odd number of taps, when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, the read-write control module is used to configure the reference address generated by the reference address counter as the first folded read address according to the counting timing of the reference address counter; and configure the sum of the reference address and the numerical value 1 as the second folded read address, which is equivalent to adding an address offset to the reference address to offset one address relative to the reference address so as to achieve non-overlap with the first folded read address; the read-write control module is also used to configure the sum of the first folded read address and the second folded read address as the post-read address, and read the data to be filtered in the post-read address from the data cache space according to the counting timing of the reference address counter, and transmit it to the filtering calculation module.

[0066] Specifically, the reference address counter disclosed in this embodiment is also used to continue to perform a self-increment operation on the count value when the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter; and the change value of the count value generated by the reference address counter in each self-increment operation is a value of 2, and the reference address obtained after the self-increment operation is configured as the starting address of the first folding read address (the first folding read address read first in a filtering cycle) in each filtering cycle; in some embodiments, it can be equivalent to that every time two data to be filtered are written, that is, a filtering calculation is started, the reference address counter is counted by two, and then, every time a filtering calculation is started, the reference address counter is counted by two. It is worth noting that if the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the reference address counter may still be performing a self-increment operation to record the sequence number of the current filtering cycle or the number of data to be filtered written. Therefore, when the number of data to be filtered written into the data cache space exceeds the transposition enable count threshold of the FIR filter, the reference address counter provides a corresponding starting read address for the data to be filtered that needs to be extracted and filtered in each filtering cycle as the starting address information of the data for actual filtering calculation.

[0067] Specifically, the read-write control module includes a first folding address counter; when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the first folding address counter is used to perform a self-decrement operation on the first folding read address in each filtering cycle to generate a new first folding read address, so as to trigger the read-write control module to read the to-be-filtered data in the first folding read address after each self-decrement operation from the data cache space, until the number of self-decrement operations reaches a first preset folding sampling number, but still allowing new to-be-filtered data to be written into the data cache space, but the new to-be-filtered data is not counted in the to-be-filtered data required for the current filtering calculation, but is recorded as the to-be-filtered data required for the next filtering calculation. The change in the count value generated by one self-decrement operation of the first folding address counter is a value of 1, that is, each time the first folding address counter performs a self-decrement operation, the corresponding count value is reduced by a value of 1.

[0068] Before the read-write control module determines to configure the reference address generated by the reference address counter as the first folding read address, which is equivalent to configuring the reference address as the starting address of the first folding read address (the first first folding read address that needs to be read in the corresponding filtering cycle or participating in the corresponding filtering calculation), the read-write control module is used to update the filtering target address to the reference address when it is determined that the reference address is equal to the filtering starting address, and then configure the updated reference address as the starting address of the first folding read address, so that the first folding read address can be deducted from a reasonable address offset value during the self-decrement operation to obtain the data to be filtered in the valid address obtained by the self-decrement operation, thereby avoiding obtaining invalid data and losing data associated with the current filtering cycle or the current filtering calculation.

[0069] It should be noted that the filtering target address is an address pre-configured in the data cache space. It is the address with the largest order of reads among the addresses participating in the reading operation in each filtering cycle. The filtering target address is greater than the filtering starting address, and the difference between the filtering target address and the filtering starting address is equal to the difference between the number of taps of the FIR filter and the value 1. Generally, when the filtering starting address is set to the value 0, the filtering target address is set to the difference between the number of taps of the FIR filter and the value 1. This can be applied to the scenario where the address read for the first time by the read-write control module in a filtering calculation is the address position marked with the value 0. The second folding address counter can start to perform a self-increment operation from this address position, and the first folding address counter can start to perform a self-decrement operation from the difference between the number of taps of the FIR filter and the value 1. Alternatively, when the filtering starting address is set to the value 1, the filtering target address is set to the number of taps of the FIR filter. This can be applied to the scenario where the address read for the first time by the read-write control module in a filtering calculation is the address position marked with the value 1. The second folding address counter can start to perform a self-increment operation from this address position, and the first folding address counter can start to perform a self-decrement operation from the number of taps of the FIR filter. Then, the first folding address counter is used to perform a self-decrement operation on the first folding read address starting from the starting address of the first folding read address, so as to realize an orderly data reading operation based on a decimation rate of twice that specified by the FIR filter; wherein the first folding read address can also represent the order of the first folding read addresses in the data cache space; the process of the first folding address counter performing the self-decrement operation on the first folding read address includes: configuring the starting address of the first folding read address as the first folding read address, and whenever the first folding read address is decremented to the filtering starting address, updating the filtering target address to the first folding read address in the next system clock cycle, so that the updated first folding read address is more stable, so as to be normally read by the read-write control module, and also allowing the first folding read address to implement address loop traversal within the address range limited by the number of taps of the FIR filter, so as to timely traverse the latest written data to be filtered and reduce the occupied space of the cache address. It is worth noting that because the previously cached data can be read into the filtering calculation module in a timely manner, the newly written data can overwrite the address unit where the previously cached data in the data cache space is located. After the above-mentioned self-decrementing operation to the filtering start address and completing the loop, or self-increasing operation to the filtering target address and completing the loop, the first folding address counter continues to perform the self-decrementing operation on the first folding read address.

[0070] It should be noted that the first folding address counter performs a self-decrement operation on the first folding read address once every two consecutive system clock cycles to obtain a new first folding read address, which is also consistent with the counting timing of the reference address counter, and these two consecutive system clock cycles are recorded as the folding address read cycle, wherein the first folding address counter performs a self-increment operation, and its count value increases by a value of 1; the second folding address counter is used to perform a self-increment operation once in the folding address read cycle to obtain a new second folding read address within every two consecutive system clock cycles, wherein the second folding address counter performs a self-increment operation, and its count value decreases by a value of 1 relative to the previous count value. Therefore, when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, under the control of the read-write control module, within a folding address read cycle, the data to be filtered in the first folding read address is read to the filter calculation module, and the data to be filtered in the second folding read address is read to the filter calculation module. It can also be that the data to be filtered in the first folding read address is read to the filter calculation module while the data to be filtered in the second folding read address is read to the filter calculation module; the reading is repeated in this way until the data to be filtered of the first folding read address and the data to be filtered of the second folding read address within the current filtering cycle are read, which is equivalent to: when the transposition enable count threshold of the FIR filter is the number of taps of the FIR filter, the number of data to be filtered read within a filtering cycle (including the number of data to be filtered in the first folding read address and the number of data to be filtered in the second folding read address) is equal to the number of taps of the FIR filter.

[0071] On the other hand, the read / write control module includes a second folding address counter; when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the second folding address counter is further configured to perform a self-increment operation on the second folding read address within each filtering cycle to generate a new second folding read address, thereby triggering the read / write control module to read the to-be-filtered data in the second folding read address after each self-increment operation from the data cache space, until the number of self-increment operations reaches a second preset folding sampling number, while still allowing new to-be-filtered data to be written into the data cache space. However, the new to-be-filtered data is not counted as to-be-filtered data required for the current filtering calculation, but is recorded as to-be-filtered data required for the next filtering calculation. The change in the count value generated by each self-increment operation of the second folding address counter is a value of 1, i.e., each time the second folding address counter performs a self-increment operation, the corresponding count value generated increases by a value of 1 relative to the previous count value.

[0072] Before the read-write control module determines to configure the reference address as the second folding read address, which is equivalent to configuring the sum of the reference address and the value 1 as the starting address of the second folding read address (the first second folding read address that needs to be read in the corresponding filtering cycle or participating in the corresponding filtering calculation), the read-write control module is used to, when it is determined that the reference address generated by the reference address counter in the current filtering calculation or the current filtering cycle is equal to the filtering target address, update the filtering starting address to the reference address by the second folding address counter, and then configure the sum of the reference address and the value 1 as the starting address of the second folding read address, so as to avoid overlap with the starting address of the first folding read address, avoid reading the same data to be filtered, and also facilitate the second folding read address to add a reasonable address offset value during the self-increment operation, obtain the data to be filtered in the valid address obtained by the self-increment operation, avoid obtaining invalid data and losing data associated with the current filtering cycle or the current filtering calculation.

[0073] Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address, wherein the change value of the count value generated by the second folding address counter self-increasing once is a value of 1, so that the second folding read address is increased by a value of 1 in one self-increment operation relative to the previous self-increment operation, so as to realize a comprehensive data reading operation in an address offset direction different from the first folding read address. Then, the process of the second folding address counter performing a self-increment operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is self-added to the filtering target address, updating the filtering starting address to the second folding read address in the next system clock cycle, so that the second folding read address can realize address loop traversal within the address range limited by the number of taps of the FIR filter, which can not only traverse to the latest written data to be filtered, but also reduce the allocation amount of the cache address, and then insert it into the uncovered area of ​​the first folding read address to realize loop traversal of the read address, and completely traverse the address range limited by the number of taps of the FIR filter without overlap within the same filtering cycle.

[0074] It should be noted that, at the reading timing corresponding to the number of taps of the FIR filter, or at the counting timing corresponding to the reference address counter, the second folding address counter is used to perform a self-increment operation on the second folding read address once every two consecutive system clock cycles to obtain a new second folding read address, and record these two consecutive system clock cycles as the counting cycle of the second folding read address, which is equivalent to the folding address read cycle; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, under the control of the read-write control module, within the folding address read cycle (equivalent to two consecutive system clock cycles), the data to be filtered in the first folding read address is first read to the filter calculation module, and then the data to be filtered in the second folding read address is read to the filter calculation module, or the data to be filtered in the first folding read address and the data to be filtered in the second folding read address are read synchronously; the reading is repeated until the number of data to be filtered read within a filtering cycle is equal to the number of data to be filtered written to participate in the current filtering calculation, which is equivalent to the sum of the number of data to be filtered at the first folding read address and the number of data to be filtered at the second folding read address defined within the current filtering cycle. In this embodiment, in each folding address reading cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read relative to the filtering target address, so as to realize folding calculation of the data to be filtered at the second folding read address input into the filtering calculation module within one filtering cycle and the data to be filtered at the first folding read address symmetrical in address position.

[0075] like Figure 2As shown, the read-write control module further includes an address adder and a read address selector; the two input ends of the address adder are respectively connected to the count output end set by the second folding address counter and the count output end set by the first folding address counter, and the output end of the address adder is connected to an input end of the read address selector; the address adder is used to add the second folding read address fir_raddr2 generated by the second folding address counter and the first folding read address fir_raddr1 generated by the first folding address counter during the folding address read cycle to generate the folding address read cycle. A post-read address fir_raddr_after within the period is equivalent to adding the first folded read address to an offset address equal to the second folded read address, and the sum is equal to the post-read address, which is output by the address adder to the read address selector; it should be noted that after the first folded read address fir_raddr1 as the base address and the second folded read address fir_raddr2 as the offset address enter the address adder, a physical address is synthesized, and the logical sum of the output is formed by left shifting or right shifting the address segment to form a physical address with a bit width different from the input address.

[0076] The read / write control module disclosed in this embodiment generates a high-level folding selection signal when the number of the to-be-filtered data in the write data cache space is greater than the transposition enable count threshold of the FIR filter, corresponding to Figure 2 The selection signal Thr_sel=1, the read address selector selects the post-read address generated by the address adder and outputs it to the data cache space, specifically by Figure 1 and 2 The data is transmitted out of the port I4 so that the read-write control module can read the two data to be filtered in the corresponding address during the folding address read cycle, namely the data to be filtered in the first folding read address and the data to be filtered in the second folding read address.

[0077] It should be added that the address offset between the starting address of the second folded read address and the starting address of the first folded read address is equal to the difference between the number of taps of the FIR filter and the value 1, so that under the premise that the direction of traversal of the second folded read address is different from the traversal direction of the first folded read address, each address in the same address range is traversed together, for example, by updating the first folded read address to traverse from the first address to the last address, and by updating the second folded read address to traverse from the last address to the first address, the traversal of the same address range is completed completely with the same traversal step size.

[0078] In the above embodiment, in each folding address reading cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read relative to the filtering target address, forming a head-to-tail address symmetric form of the FIR filter structure centered on the address position last read within a filtering cycle or a filtering calculation, that is, the first folding read address and the second folding read address in each folding address reading cycle are symmetric about the center of the address position last read within a filtering cycle.

[0079] Preferably, within a filtering cycle or a filtering calculation, when the second preset folding sampling number is greater than the first preset folding sampling number, the first folding read address stops changing in advance of the second folding read address, and if the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter, then the difference between half of the difference between the number of taps of the FIR filter and the value 1 and the value 1 is equal to the first preset folding sampling number, and half of the difference between the number of taps of the FIR filter and the value 1 is equal to the second preset folding sampling number, and the first folding read address is first decremented to obtain an intermediate address position within the current filtering cycle, and the intermediate address position is the address position obtained by the first folding address counter decrementing the first folding read address by one for the last time. Alternatively, within a filtering cycle or a filtering calculation, when the second preset folding sampling number is less than the first preset folding sampling number, the difference between half of the difference between the number of taps of the FIR filter and the numerical value 1 and the numerical value 1 is equal to the second preset folding sampling number, and half of the difference between the number of taps of the FIR filter and the numerical value 1 is equal to the first preset folding sampling number, so that the second folding read address is first self-added to obtain an intermediate address position within the current filtering cycle, and the intermediate address position is the address position obtained by the second folding address counter adding one to the second folding read address for the last time within the same filtering cycle.

[0080] As an embodiment of an FIR filter with a tap number equal to 5, the reference address corresponds to Figure 3 The initial address of the reference address counter, in this embodiment, the count value of the reference address counter in each filtering cycle is configured as the reference address in each filtering cycle as the updated reference address; the reference address in the first filtering cycle is 0, which is the initial count value of the reference address counter. Figure 3In the example, each time a filtering calculation begins, it is considered to have entered a filtering cycle, and the reference address counter counts once. Except for the first filtering cycle, in which only one data item to be filtered is written, in subsequent filtering cycles, each time two new data items to be filtered are written to the data cache space, a read and filtering calculation is performed. After completing the first filtering calculation and obtaining the filtering result y0, that is, after one filtering cycle, in the second filtering cycle, the data in the first row of boxes is shifted two coefficient positions to the right as a whole, becoming the data in the third row of boxes. Compared to the data in the first row of boxes, two new data items are added to occupy the two leftmost grids. At this time, the filtering calculation module begins a new filtering calculation, and the reference address counter counts up by two. The reference address counter increases the reference address in the first filtering cycle by 2, and the reference address in the second filtering cycle is 2. After completing the second filtering calculation and obtaining the filtering result y2, in the third filtering cycle, the data in the third row box is shifted two coefficient bits to the right as a whole and becomes the data in the fifth row box. Two new data are added relative to the data in the third row box to occupy the two leftmost grids. At this time, the filtering calculation module starts a new filtering calculation (the third filtering calculation), and the reference address counter counts by two. The reference address of the third filtering cycle is offset by two address units to the right relative to the reference address of the second filtering cycle, and the reference address of the third filtering cycle is obtained as a value of 4; thereby: the address offset between the reference addresses obtained in two adjacent filtering cycles is equal to the decimation rate (twice the decimation rate) or interpolation rate of the FIR filter. At this time, the reference address counter is used to count the shift operation of the read address of the data cache space, which also facilitates the use of the shift register to cache the newly written data to be filtered. After completing the third filtering calculation and obtaining the filtering result y4, in the fourth filtering cycle, the data in the fifth row of boxes are shifted two coefficient bits to the right as a whole and become the data in the seventh row of boxes. Two new data are added relative to the data in the fifth row of boxes to occupy the two leftmost grids. At this time, the number of data to be filtered written into the data cache space is greater than the transpose enable count threshold of the FIR filter, that is, the number of data to be filtered written into the data cache space is greater than 5 (the number of taps of the FIR filter is equal to 5, and the number of taps of the FIR filter is equal to the transpose enable count threshold of the FIR filter). At this time, the filtering calculation module starts a new filtering calculation (the fourth filtering calculation). At this time, a total of 5 data to be filtered are written.Since the address offset value of the reference address of the third filtering cycle relative to the reference address in the first filtering cycle is equal to the difference between the number of taps of the FIR filter and the numerical value 1, that is, the count value of the reference address counter in the third filtering cycle is the difference between the number of taps of the FIR filter and the numerical value 1, the reference address counter has counted 5 address units (including the initial count value), so the sum of the filtering starting point address and the numerical value 1 is configured as the reference address of the fourth filtering cycle, which is equal to the numerical value 1, corresponding to. Figure 3 The initial address of the fourth filtering cycle in the filter buffer is 0. The filtering starting address is a pre-configured address in the data cache space. It is the smallest address in the order of the addresses involved in the read operation in each filtering cycle. In this case, the filtering starting address is configured as 0.

[0081] It is worth noting that in order to obtain the reference address of the fourth filtering cycle, if the reference address counter continues to perform a self-increment operation on the reference address of the fourth filtering cycle (the change value of the count value in one self-increment operation is a value of 2), the obtained reference address exceeds the number of taps of the FIR filter. Invalid data is easily read according to the reference address, and it is not suitable to be set as Figure 3 The initial address of the fourth filtering cycle in Figure 3 The initial address of the fourth filter cycle in is set to the value 1.

[0082] After completing the fourth filtering calculation and obtaining the filtering result y6, in the fifth filtering cycle, the data in the seventh row of boxes are shifted rightward by two coefficient positions, becoming the data in the ninth row of boxes. Two new data are added to the leftmost two cells relative to the data in the seventh row of boxes. At this time, the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, that is, the number of data to be filtered in the write data cache space is greater than 5 (the number of taps of the FIR filter is equal to 5, and the number of taps of the FIR filter is equal to the transposition enable count threshold of the FIR filter). At this time, the filtering calculation module begins a new filtering calculation (the fifth filtering calculation) to obtain the filtering result y8, and the reference address counter is incremented by two, resulting in a reference address of 3 for the fifth filtering cycle. It should be noted that the aforementioned initial address is the first operation address required for the filtering calculation module to perform filtering calculation or folding calculation, and is also the address of the first data involved in the calculation in each filtering cycle.

[0083] Corresponding to Figure 3 In the window of the extracted data, in the 4th filtering cycle, when the number of taps is 5, according to Figure 2The post-read address fir_raddr_after at the output end of the read address selector shown is equivalent to the first folding read address and the second folding read address transmitted successively. Then, the read-write control module first reads the seventh input data X7 (data at the first folding read address) and the third input data X3 (data at the second folding read address) to form a first pair of added parameters and sends them to the filtering calculation module; then reads the sixth input data X6 (data at the first folding read address) and the fourth input data X4 (data at the second folding read address) to form a second pair of added parameters and sends them to the filtering calculation module; finally, reads the fifth input data X5 (data at the first folding read address or the second folding read address) and sends it to the filtering calculation module. After reading the data to be filtered at the first folding read address and the data to be filtered at the second folding read address defined in the current filtering cycle, the filtering calculation module is triggered to complete a folding calculation of the data, so that the FIR filter completes a filtering calculation when the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter.

[0084] As a data extraction embodiment of an FIR filter with a tap number of 5, the transposition enable count threshold of the FIR filter is equal to the tap number of the FIR filter; Figure 3In the fourth filtering cycle, starting from the initial address 1, the first folded read address is decremented according to the cycle limited by the counting timing of the reference address counter, including the maximum reading time length supported by the number of taps and the cycle of reading a single data, and then the read-write control module is triggered to read the data to be filtered from the first folded read address obtained from each decrement operation to the filtering calculation module. The read-write control module obtains a first folded read address for each decrement operation, and reads the data to be filtered in the corresponding first folded read address from the data cache space, which are X7, X6 and X5 in the seventh row box respectively. At this time, the number of decrement operations is 2, which is equal to half of the difference between the number of taps of the FIR filter (value 5) and the value 1, and the data to be filtered in the three first folded read addresses are obtained, which belong to the data to be filtered in the three consecutive addresses. At the same time, each time the read-write control module receives a second folded read address obtained by a self-add operation from within the read-write control module, the data to be filtered in the corresponding second folded read address is read from the data cache space, which are X3 and X4 in the seventh row box, respectively. At this time, the number of self-add operations is 1, which is equal to the difference between half of the difference between the number of taps of the FIR filter (value 5) and the value 1 and the value 1, and the data to be filtered in the two second folded read addresses is obtained, which belongs to the data to be filtered in two consecutive addresses, and the data reading stops. Therefore, in the fourth filtering cycle, the data to be filtered read in sequence are X7, X3, X6, X4 and X5, among which X7 is the first data to be filtered read and X5 is the last data to be filtered read; at this time, the data to be filtered in the first folded read address and the data to be filtered in the second folded read address have satisfied the filtering calculation of the number of taps matching of the FIR filter.

[0085] Furthermore, in the fifth filtering cycle, starting from the initial address 3, the first folding read address is decremented according to the system clock cycle limited by the number of taps of the FIR filter. The read-write control module obtains a first folding read address each time it decrements, and then reads the corresponding first folding read address from the data cache space. The data to be filtered are X9, X8, and X7 in the ninth row of the box. At this time, the data in the seventh row of the box is shifted two squares to the right. However, the number of decrement operations occurring in the fifth filtering cycle is 2, which is equal to half of the difference between the number of taps of the FIR filter (value 5) and the value 1. The data to be filtered in the three first folding read addresses are also the data to be filtered in the three consecutive addresses. Therefore, in the fifth filtering cycle, the data to be filtered read in sequence are X9, X5, X8, X6, and X7, where X9 is the first data to be filtered read and X7 is the last data to be filtered read.

[0086] It is worth noting that Figure 3 In the fourth filtering cycle and the fifth filtering cycle, the arrangement order of the squares in the seventh row and the ninth row of the box corresponding to the seventh row only represents the order in which the filtered data are read, and does not represent the actual storage order in the data cache space; similarly, Figure 3 The arrangement order of the squares in the even-numbered rows does not represent the storage order of the internal filter coefficients in the filter coefficient memory, but only represents the reading order of the filter coefficients and corresponds to the reading order of the data to be filtered in the previous row.

[0087] As a filtering calculation embodiment of an FIR filter with a tap number of 5, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address matched by the FIR filter, and perform a self-increment operation on the starting storage address once every two system clock cycles, which may be under the control of the read-write control module or driven by the built-in counter, so that the address corresponding to the starting storage address performs a self-increment operation every two system clock cycles, which is synchronized with the timing of the self-decrement operation performed by the first folding address counter, or synchronized with the timing of the self-increment operation performed by the second folding address counter; the filter coefficient memory then reads the corresponding stored filter coefficients to the filtering calculation module in sequence according to the storage address obtained by self-increment, until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half the difference between the number of taps of the FIR filter and the value 1, and then the latest stored address is read out to the filtering calculation module. The storage address is recorded as the intermediate calculation storage address, at which point the filtered data and filter coefficients required for processing within the filtering cycle have been read. Specifically, the address counter set within the filter coefficient memory or the address counter designed within the read-write control module increments the address corresponding to the starting storage address by one every two system clock cycles and generates the corresponding address. The address counter can be synchronized with the counting timing of the reference address counter, the second folding address counter, and the first folding address counter or maintain a fixed delay, and can change with the storage address configured to change simultaneously with the first folding read address and the second folding read address read successively within a folding address read cycle. The filter coefficient in the storage address and the filtered data in the first folding read address and the second folding read address within the folding address read cycle are read successively into the filtering calculation module within the same folding address read cycle, forming a set of calculation items that are first added and then multiplied, that is, the sum of the filtered data in the first folding read address and the second folding read address is multiplied by the filter coefficient. In the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, the address corresponding to the storage address is incremented by 1. In this embodiment, there is no need to perform a self-decrement operation on the starting storage address. When the amount of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, there is no need to perform a loopback traversal of the storage address, thereby saving read operations. It should be noted that the starting storage address is predetermined and can be configured by a register.

[0088] Based on the above embodiment, the filtering calculation module is used to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, first control the to-be-filtered data in the first folding read address output by the data cache space to be added with the to-be-filtered data in the second folding read address output by the data cache space in each folding address read cycle; then multiply the result of the addition with the filter coefficients in the same reading order (synchronously changing counting timing) output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this process in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address, then multiply the filter coefficients in the intermediate calculation storage address with the to-be-filtered data in the first folding read address output by the data cache space in the same reading order, and then input the multiplication result into the adder for accumulation processing, to obtain the processed filtering result in the corresponding filtering cycle, thereby completing one filtering calculation, that is, completing the filtering calculation in one filtering cycle. In each filtering cycle, when the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter, the number of multiplication operations performed within the filtering calculation module is equal to half the sum of the number of taps of the FIR filter and the value 1, and is implemented by time-sharing multiplexing of a multiplier, that is, a multiplier performs a multiplication operation once during each folding address read cycle. In this embodiment, the filtering calculation module includes an adder and a multiplier. In this embodiment, the sum of the to-be-filtered data in the first folding read address and the to-be-filtered data in the second folding read address is input into the multiplier, and the filter coefficients read in the same cycle are also input into the multiplier to participate in a multiplication operation. The result of the multiplication in the cycle is then transmitted to the adder for accumulation calculation. Therefore, in this embodiment, the same multiplier resources are used in the filtering calculation module to implement the multiplication operation of the newly input to-be-filtered data and the same set of filter coefficients in different filtering cycles, thereby improving the reuse rate of the multiplier resources under the conditions of different types of filter reading data.

[0089] Corresponding to Figure 3In the fourth filtering cycle, X7 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) are a group of folding data, which are added together to obtain the first folding value. At the same time, the filter coefficient h1 is read from the filter coefficient memory; then, X6 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X4 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) are another group of folding data, which are added together to obtain the second folding value. At the same time, the filter coefficient h2 is read from the filter coefficient memory; then, the filter coefficient h3 in the intermediate calculation storage address is read from the filter coefficient memory. Generally, the filter coefficient in the intermediate calculation storage address is set to a fixed parameter, which is applicable to any FIR filter with an odd number of taps. For these folded data, the filtering calculation module outputs the filter coefficients at the corresponding positions from the filter coefficient memory for multiplication to perform folding calculation. Specifically, the filtering result y6 obtained by the folding calculation is equal to: the product of the sum of X7 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) and the filter coefficient h1 read for the first time, the product of the sum of X6 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X4 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) and the filter coefficient h2 read for the second time, and the sum of X5 (the data to be filtered in the first folding read address read for the third time, that is, the data to be filtered read for the fifth time) and the filter coefficient h3 read for the third time.

[0090] As an implementation method of an FIR filter with an even number of taps, Figure 2 As shown, the read-write control module includes a pre-address counter and a read address selector; when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the working principle of the read address selector, the pre-address counter and the reference address counter is the same as that of the aforementioned embodiment 1 of the FIR filter with an odd number of taps, and will not be repeated here. Figure 4 In the example, different data flow characteristics due to the difference in the number of taps include:

[0091] exist Figure 4In an embodiment, the transposition enable count threshold of the FIR filter is set to 6, which is equal to the number of taps of the FIR filter. For a filtering calculation, when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the reference address may be Figure 4 The initial address of the first filter cycle (filter cycle with serial number 1) is 2, the reference address of the second filter cycle (filter cycle with serial number 2) is 4, and the reference address of the third filter cycle (filter cycle with serial number 3) is 0. At this time, 6 data to be filtered have been written, and the order from the latest written to the first written is X6, X5, X4, X3, X2 and X1.

[0092] exist Figure 4 In the embodiment of the present invention, when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, that is, when the number of data to be filtered written into the data cache space is less than or equal to 6, the reference address is Figure 4 The initial address of the first filtering cycle (filtering cycle with serial number 1) is 2, and the reference address of the second filtering cycle (filtering cycle with serial number 2) is 4, which has reached the difference between the number of taps of the FIR filter and the value 2. If the reference address counter continues to perform self-increment operation on the currently obtained reference address (count value), the new reference address generated becomes the value 6. Under the premise that the initial count value set in the reference address counter is configured as the value 0, the number of addresses traversed is already 7, which exceeds the number of taps of the FIR filter. Therefore, the reference address in the third filtering cycle (filtering cycle with serial number 3) is the value 0. Then, after the third filtering cycle (filtering cycle with serial number 3), 6 data to be filtered have been written, and the ones written from the newest to the first are X6, X5, X4, X3, X2 and X1.

[0093] In a second embodiment of an FIR filter with an even number of taps, to perform a filtering calculation, still in the implementation scenario where the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, either under the control of the read / write control module or driven by a counter built into the filter coefficient memory, start from a starting storage address that matches the FIR filter, perform a self-increment operation on the starting storage address according to the system clock cycle, and then sequentially read the corresponding stored filter coefficients to the filtering calculation module according to the storage address obtained by the self-increment. Specifically, the obtained storage address is incremented by one in each system clock cycle. Then, within the same system clock cycle, the address offset step length of the storage address is equal to the address offset step length of the aforementioned pre-read address, and the address offset is maintained at the same system clock source until the address offset of the storage address obtained by the self-increment relative to the starting storage address is equal to half the difference between the number of taps of the FIR filter and the value 2. It should be noted that, within a filtering cycle, the order in which the filter coefficients required for the same filtering calculation are read is the same as the order in which the data to be filtered are read. Then, the filter coefficient memory records the latest storage address as the intermediate calculation storage address. It is worth noting that this embodiment needs to continuously read two identical filter coefficients from the same intermediate calculation storage address to the filter calculation module. Then, the intermediate calculation storage address is decremented, and the corresponding stored filter coefficients are read out to the filter calculation module in sequence according to the storage address obtained by self-decrement, until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter and the value 2. This is repeated in sequence until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle (corresponding to the start of the current filtering calculation) is equal to the number of data to be filtered participating in the filtering calculation in the current filtering cycle, which may vary depending on the actual number of filtering calculations performed or the filtering cycle in which it is located. It should be noted that, in the process of performing a self-increment operation on the starting storage address, each time the self-increment operation is performed, the address corresponding to the trigger storage address automatically increases by 1; in the process of performing a self-decrement operation on the intermediate calculation storage address, each time the self-decrement operation is performed, the address corresponding to the trigger storage address automatically decreases by 1; wherein, the intermediate calculation storage address is set in the filter coefficient memory, and is the address with the largest sequence among the storage addresses of the filter coefficient, that is, the tail address of the address interval storing the corresponding filter coefficient.

[0094] exist Figure 4In the third filtering cycle, starting from the address position with the initial address being the value 0, from left to right, the data in the fifth row of boxes are sequentially the data to be filtered in the pre-read address after the self-decrement operation read from the data cache space by the read-write control module. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address position is the pre-read address obtained by the earlier self-decrement; the data in the squares closer to the right are read later, and the corresponding address position is the pre-read address obtained by the later self-decrement. Preferably, the data in one square is read in each system clock cycle.Similarly, in the third filtering cycle, the data in the sixth row of boxes are the filter coefficients in the storage address after the self-addition operation read out from the filter coefficient memory, starting from the address position corresponding to the square h1, that is, the starting storage address corresponding to the FIR filter. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address positions are the storage addresses obtained by self-addition earlier; the data in the squares closer to the right are read later, and the corresponding address positions are the storage addresses obtained by self-addition later, until the self-addition reaches the square h3 on the left. Grid (the first filter coefficient read from left to right), at this time, the address position corresponding to the grid h3 on the left relative to the address position corresponding to the grid h1 has an address offset equal to 2, which is equal to half of the difference between the number of taps of the FIR filter (value 6) and the value 2 (equal to the value 2). The filter coefficient memory configures the address position corresponding to the grid h3 as an intermediate calculation storage address. In this embodiment, the intermediate calculation storage address is read twice continuously, which can be read according to the system clock cycle to obtain two identical filter coefficients h3; then starting from the grid h3, The intermediate calculation storage address is decremented until it reaches the grid h1. At this time, the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter (value 6) and the value 2 (equal to the value 2). At this time, in the sixth row of boxes, the filter coefficients h1, h2, h3, h3, h2 and h1 read from left to right correspond to the to-be-filtered data X6, X5, X4, X3, X2 and X1 participating in the filtering calculation in the fifth row of boxes, among which X6 is the to-be-filtered data in the pre-read address read out first. X1 is the data to be filtered in the last read-out front read address; then the number of filter coefficients read from the filter coefficient memory within the third filtering cycle satisfies the number of data to be filtered participating in the filtering calculation within the third filtering cycle, and also makes the filter coefficients in the storage address obtained by the self-addition operation before obtaining the intermediate calculation storage address and the filter coefficients in the storage address obtained by the self-subtraction operation after obtaining the intermediate calculation storage address constitute the symmetrical filter coefficients of the FIR filter, thereby achieving a symmetrical filtering result in the current filtering calculation (within the third filtering cycle).

[0095] On the basis of the above embodiment, the filtering calculation module is used to control the multiplication of the data to be filtered output by the data cache space and the filter coefficients in the same reading order output by the filter coefficient memory when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, and input the result into the adder for accumulation processing to obtain a filtering result after processing within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by a multiplier in time-sharing multiplexing, minimizing the multiplier resources; wherein, under the premise that the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the number of multiplication operations within a filtering cycle is equal to the number of data to be filtered or the number of filter coefficients required for the current filtering calculation, but does not exceed the number of taps of the FIR filter. The filtering calculation module includes an adder and a multiplier, which constitute a calculation method of performing multiplication first and then performing addition. Corresponding to Figure 4 , the filtering result y4 obtained in the third filtering cycle is equal to the sum of the product of X6 and h1, the product of X5 and h2, the product of X4 and h3, the product of X3 and h3, the product of X2 and h2, and the product of X1 and h1, then the number of multiplication operations in the third filtering cycle is equal to 6. The transpose enable count threshold of the FIR filter is equal to the number of taps of the FIR filter.

[0096] As a third embodiment of an FIR filter with an even number of taps, this embodiment is based on the fact that the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter. The read-write control module includes a first folding address counter; when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the first folding address counter is configured to decrement the first folding read address within each filtering cycle to generate a new first folding read address, thereby triggering the read-write control module to read the to-be-filtered data from the data cache space at the first folding read address after each decrement operation, until the number of decrement operations reaches a first preset folding sampling number. However, new to-be-filtered data is still allowed to be written into the data cache space, but this new to-be-filtered data is not counted as to-be-filtered data required for the current filtering calculation, but is instead recorded as to-be-filtered data required for the next filtering calculation. The change in the count value generated by each decrement operation of the first folding address counter is 1, i.e., each decrement operation of the first folding address counter decreases the corresponding count value by 1.

[0097] Before the read-write control module determines to configure the reference address generated by the reference address counter as the first folding read address, which is equivalent to configuring the reference address as the starting address of the first folding read address (the first first folding read address that needs to be read in the corresponding filtering cycle or participating in the corresponding filtering calculation), the read-write control module is used to update the filtering target address to the reference address when it is determined that the reference address is equal to the filtering starting address, and then configure the updated reference address as the starting address of the first folding read address, so that the first folding read address can be deducted from a reasonable address offset value during the self-decrement operation to obtain the data to be filtered in the valid address obtained by the self-decrement operation, thereby avoiding obtaining invalid data and losing data associated with the current filtering cycle or the current filtering calculation.

[0098] It should be noted that the first folding address counter performs a self-decrement operation on the first folding read address once every two consecutive system clock cycles to obtain a new first folding read address, which is also consistent with the counting timing of the reference address counter, and these two consecutive system clock cycles are recorded as the folding address read cycle, wherein the first folding address counter performs a self-increment operation, and its count value increases by a value of 1; the second folding address counter is used to perform a self-increment operation once in the folding address read cycle to obtain a new second folding read address within every two consecutive system clock cycles, wherein the second folding address counter performs a self-decrement operation, and its count value decreases by a value of 1 relative to the previous count value. Therefore, when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, under the control of the read-write control module, within a folding address read cycle, the data to be filtered in the first folding read address is first read to the filter calculation module, and then the data to be filtered in the second folding read address is read to the filter calculation module. It can also be that the data to be filtered in the first folding read address is read to the filter calculation module while the data to be filtered in the second folding read address is read to the filter calculation module; the reading is repeated until the data to be filtered of the first folding read address and the data to be filtered of the second folding read address within the current filtering cycle are read, which is equivalent to: when the transposition enable count threshold of the FIR filter is the number of taps of the FIR filter, the number of data to be filtered read within a filtering cycle (including the number of data to be filtered in the first folding read address and the number of data to be filtered in the second folding read address) is equal to the number of taps of the FIR filter.

[0099] On the other hand, the read / write control module includes a second folding address counter; when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the second folding address counter is further configured to perform a self-increment operation on the second folding read address within each filtering cycle to generate a new second folding read address, thereby triggering the read / write control module to read the to-be-filtered data in the second folding read address after each self-increment operation from the data cache space, until the number of self-increment operations reaches a second preset folding sampling number, while still allowing new to-be-filtered data to be written into the data cache space. However, the new to-be-filtered data is not counted as to-be-filtered data required for the current filtering calculation, but is recorded as to-be-filtered data required for the next filtering calculation. The change in the count value generated by each self-increment operation of the second folding address counter is a value of 1, i.e., each time the second folding address counter performs a self-increment operation, the corresponding count value generated increases by a value of 1 relative to the previous count value.

[0100] Before the read-write control module determines to configure the reference address as the second folding read address, which is equivalent to configuring the sum of the reference address and the value 1 as the starting address of the second folding read address (the first second folding read address that needs to be read in the corresponding filtering cycle or participating in the corresponding filtering calculation), the read-write control module is used to, when it is determined that the reference address generated by the reference address counter in the current filtering calculation or the current filtering cycle is equal to the filtering target address, update the filtering starting address to the reference address by the second folding address counter, and then configure the sum of the reference address and the value 1 as the starting address of the second folding read address, so as to avoid overlap with the starting address of the first folding read address, avoid reading the same data to be filtered, and also facilitate the second folding read address to add a reasonable address offset value during the self-increment operation, obtain the data to be filtered in the valid address obtained by the self-increment operation, avoid obtaining invalid data and losing data associated with the current filtering cycle or the current filtering calculation. Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address, wherein the change value of the count value generated by the second folding address counter self-increasing once is a value of 1, so that the second folding read address is increased by a value of 1 in one self-increment operation relative to the previous self-increment operation, so as to realize a comprehensive data reading operation in an address offset direction different from the first folding read address. Then, the process of the second folding address counter performing a self-increment operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is self-added to the filtering target address, updating the filtering starting address to the second folding read address in the next system clock cycle, so that the second folding read address can realize address loop traversal within the address range limited by the number of taps of the FIR filter, which can not only traverse to the latest written data to be filtered, but also reduce the allocation amount of the cache address, and then insert it into the uncovered area of ​​the first folding read address to realize loop traversal of the read address, and completely traverse the address range limited by the number of taps of the FIR filter without overlap within the same filtering cycle.

[0101] It should be noted that, at the reading timing corresponding to the number of taps of the FIR filter, or at the counting timing corresponding to the reference address counter, the second folding address counter is used to perform a self-increment operation on the second folding read address once every two consecutive system clock cycles to obtain a new second folding read address, and these two consecutive system clock cycles are recorded as the counting cycle of the second folding read address; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, under the control of the read-write control module, within the folding address read cycle (equivalent to two consecutive system clock cycles), the data to be filtered in the first folding read address is first read to the filter calculation module, and then the data to be filtered in the second folding read address is read to the filter calculation module, or the data to be filtered in the first folding read address and the data to be filtered in the second folding read address are read synchronously; the reading is repeated until the number of data to be filtered read within a filtering cycle is equal to the number of data to be filtered written to participate in the current filtering calculation, which is equivalent to the sum of the number of data to be filtered at the first folding read address and the number of data to be filtered at the second folding read address defined within the current filtering cycle. In this embodiment, in each folding address reading cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read relative to the filtering target address, so as to realize folding calculation of the data to be filtered at the second folding read address input into the filtering calculation module within one filtering cycle and the data to be filtered at the first folding read address symmetrical in address position.

[0102] Within a filtering cycle or a filtering calculation, if the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter, then when the amount of data to be filtered in the write data buffer space is greater than the number of taps of the FIR filter, the second preset folding sampling number is equal to the first preset folding sampling number. In this case, the first preset folding sampling number or the first preset folding sampling number is equal to half the number of taps of the FIR filter, so that the second folding read address is first incremented to obtain an intermediate address position within the current filtering cycle, or the first folding read address is first decremented to obtain an intermediate address position within the current filtering cycle, or the first folding read address and the second folding read address simultaneously reach an intermediate address position within the current filtering cycle, wherein the intermediate address position is the address position obtained by the second folding address counter last incrementing the second folding read address or the address position obtained by the first folding address counter last decrementing the first folding read address within the same filtering cycle. The intermediate address positions may be two adjacent address positions, corresponding to the count status of the first folding address counter and the count status of the second folding address counter, respectively.

[0103] As an embodiment of an FIR filter with a tap number equal to 6, the reference address corresponds to Figure 4 The initial address of the reference address counter, in this embodiment, the count value of the reference address counter in each filtering cycle is configured as the reference address in each filtering cycle as the updated reference address; the reference address in the first filtering cycle is 0, which is the initial count value of the reference address counter. Figure 4 In the embodiment, each time a filtering calculation is started, it is recorded as entering a filtering cycle, and the reference address counter counts once, and each count is plus two and counted once, and the change value generated by the count value is a value of 2, which is equivalent to the change value of the count value being a value of 2. In this embodiment, each time two new data to be filtered are written to the data cache space, a reading and filtering calculation is performed. Therefore, in the first filtering cycle, two data to be filtered, X2 and X1, are written, wherein X1 is written first and X2 is written later, then the reference address counter counts once, and the reference address is updated from the value 0 (initial count value) to the value 2, corresponding to Figure 4 After the first filtering calculation is completed and the filtering result y0 is obtained, that is, after one filtering cycle, in the second filtering cycle, the data in the first row of boxes are shifted two coefficient positions to the right, becoming the data in the third row of boxes. Compared with the data in the first row of boxes, two new data are added to occupy the two leftmost grids. At this time, the filtering calculation module begins a new filtering calculation, and the reference address counter counts up by two. The reference address counter increases the reference address in the first filtering cycle by 2, and the reference address in the second filtering cycle is 4.

[0104] After completing the second filtering calculation and obtaining the filtering result y2, in the third filtering cycle, the data in the third row of boxes are shifted two coefficient positions to the right as a whole and become the data in the fifth row of boxes. Two new data are added relative to the data in the third row of boxes to occupy the two leftmost grids. At this time, the filtering calculation module starts a new filtering calculation (the third filtering calculation). At this time, a total of 6 data to be filtered are written. It can be seen from the updating principle of the reference address disclosed in the first embodiment of the FIR filter with an even number of taps that the reference address counter does not continue to count by two. Since the address offset value of the reference address of the third filtering cycle relative to the reference address in the first filtering cycle is equal to the difference between the number of taps of the FIR filter and the value 2, the reference address counter has counted 6 address units, so the filtering starting address is configured as the reference address of the fourth filtering cycle, which is equal to the value 0, corresponding to Figure 3 The initial address of the fourth filtering cycle in the filter; returning the filtering starting address, so that the latest written data to be filtered can be read in time, because every time the number of data written into the data cache space reaches the number of taps of the FIR filter, the subsequently written data will overwrite the first written data and occupy its cache address, and then repeat the above filtering calculation process. Among them, the filtering starting address is the value 0. It should be noted that the filtering starting address is an address pre-configured in the data cache space. As the address with the smallest order among the addresses participating in the reading operation in each filtering cycle, the filtering starting address is configured as the value 0. Therefore, in the same window of extracted data, the base address of the second filtering cycle is offset to the left by two address units relative to the base address of the first filtering cycle, so that the base address of the third filtering cycle is the value 0.

[0105] After completing the third filtering calculation and obtaining the filtering result y4, in the fourth filtering cycle, the data in the fifth row of boxes are shifted two coefficient bits to the right as a whole and become the data in the seventh row of boxes. Two new data are added relative to the data in the fifth row of boxes to occupy the two leftmost grids. At this time, the number of data to be filtered in the write data cache space is greater than the transpose enable count threshold of the FIR filter, that is, the number of data to be filtered in the write data cache space is greater than 6 (the number of taps of the FIR filter is equal to 6, and the number of taps of the FIR filter is equal to the transpose enable count threshold of the FIR filter). At this time, the filtering calculation module starts a new filtering calculation (the fourth filtering calculation), and the reference address counter is counted by two once, and the reference address of the fourth filtering cycle obtained is the value 2.

[0106] After completing the fourth filtering calculation and obtaining the filtering result y6, in the fifth filtering cycle, the data in the seventh row of boxes are shifted to the right by two coefficient positions as a whole, becoming the data in the ninth row of boxes. Two new data are added to occupy the two leftmost grids relative to the data in the seventh row of boxes. At this time, the number of data to be filtered in the write data cache space is greater than the transpose enable count threshold of the FIR filter, that is, the number of data to be filtered in the write data cache space is greater than 6. At this time, the filtering calculation module starts a new filtering calculation (the fifth filtering calculation) to obtain the filtering result y8, and the reference address counter is counted by two once, and the reference address of the fifth filtering cycle is 4. It should be noted that Figure 4 The initial address disclosed in is the first operation address required for the filtering calculation module to perform filtering calculation or folding calculation, and is also the address of the first data involved in the calculation in each filtering cycle.

[0107] Corresponding to Figure 4 In the window of the extracted data, the fourth filtering cycle is as follows Figure 2 The post-read address fir_raddr_after at the output end of the read address selector shown in the figure (for specific sources, refer to the connection mode and working principle of the read address selector and the address adder in the fourth embodiment of the FIR filter with an odd number of taps) is equivalent to the first folded read address and the second folded read address being transmitted in sequence. The read-write control module first reads the 8th input data X8 (the data at the first folded read address) and the 3rd input data X3 (the data at the second folded read address) to form a first pair of added parameters and sends them to the filtering calculation module; then reads the 7th input data X7 (the data at the first folded read address) and the 4th input data X4 (the data at the second folded read address) to form a first pair of added parameters and sends them to the filtering calculation module; The sixth input data X6 (the data at the first folded read address) and the fifth input data X5 (the data at the second folded read address) are read and sent to the filtering calculation module to complete reading the data to be filtered of the first folded read address and the data to be filtered of the second folded read address defined in the current filtering cycle, wherein the address where the first input data X1 and the address where the second input data X2 are located have been covered and are not within the window for extracting data, the address where the first input data X1 is located is covered by the seventh input data X8, and the address where the second input data X2 is located is covered by the eighth input data X8.

[0108] As a data extraction embodiment of an FIR filter with a tap number of 6, the transpose enable count threshold of the FIR filter is equal to the tap number of the FIR filter; Figure 4In the fourth filtering cycle, starting from the initial address 1, the first folded read address is decremented according to the cycle limited by the counting timing of the reference address counter, including the maximum reading time length supported by the number of taps and the cycle for reading a single data, and then the read-write control module is triggered to read the data to be filtered from the first folded read address obtained from each decrement operation to the filtering calculation module. The read-write control module obtains a new first folded read address for each decrement operation, and reads the data to be filtered in the corresponding first folded read address from the data cache space, which are X8, X7 and X6 in the seventh row box respectively. At this time, the number of decrement operations is 2, which is equal to half of the difference between the number of taps of the FIR filter (value 6) and the value 2, and the data to be filtered in the 3 first folded read addresses are obtained. At the same time, each time the read-write control module receives a second folded read address obtained by a self-add operation from within the read-write control module, it reads the corresponding data to be filtered from the second folded read address from the data cache space, which are X3, X4, and X5 in the seventh row box, respectively. At this time, the number of self-add operations is 2, which is equal to half the difference between the number of taps of the FIR filter (value 6) and the value 2. Then, the data to be filtered in the three second folded read addresses is obtained, and data reading stops. Therefore, in the fourth filtering cycle, the data to be filtered read in sequence are X8, X3, X7, X4, X6, and X5, among which X8 is the first data to be filtered read, and X5 is the last data to be filtered read. At this time, the data to be filtered read from the first folded read address and the data to be filtered read from the second folded read address have satisfied the filtering calculation of the number of taps matching the FIR filter.

[0109] Furthermore, in the fifth filtering cycle, starting from the initial address 4, the first folded read address is decremented according to the system clock cycle limited by the number of taps of the FIR filter. The read-write control module obtains a first folded read address for each decrement operation. The data to be filtered in the first folded read address read from the data cache space are X10, X9, and X8 in the ninth row box, respectively. At this time, the data in the seventh row box is shifted two squares to the right, but the number of decrement operations occurring in the fifth filtering cycle is 2, which is equal to half the difference between the number of taps of the FIR filter (value 6) and the value 2, and the data to be filtered in the three first folded read addresses are obtained. Therefore, in the fifth filtering cycle, the data to be filtered read successively are X10, X5, X9, X6, X8, and X7, wherein X9 is the first data to be filtered read and X7 is the last data to be filtered read.

[0110] It is worth noting that Figure 4In the fourth filtering cycle and the fifth filtering cycle, the arrangement order of the squares in the seventh row and the ninth row of the box corresponding to the seventh row only represents the order in which the filtered data are read, and does not represent the actual storage order in the data cache space; similarly, Figure 3 The arrangement order of the squares in the even-numbered rows does not represent the storage order of the internal filter coefficients in the filter coefficient memory, but only represents the reading order of the filter coefficients and corresponds to the reading order of the data to be filtered in the previous row.

[0111] As a filtering calculation embodiment of an FIR filter with a tap number of 6, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address matched by the FIR filter, and perform a self-increment operation on the starting storage address once every two system clock cycles, which may be under the control of the read-write control module or driven by the built-in counter, so that the address corresponding to the starting storage address performs a self-increment operation every two system clock cycles, which is synchronized with the timing of the self-decrement operation performed by the first folding address counter, or synchronized with the timing of the self-increment operation performed by the second folding address counter; the filter coefficient memory then reads the corresponding stored filter coefficients to the filtering calculation module in sequence according to the storage address obtained by self-increment, until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half the difference between the number of taps of the FIR filter and the value 2, and then the latest obtained The storage address is recorded as the intermediate calculation storage address, at which point the filtered data and filter coefficients required for processing within the filtering cycle have been read. Specifically, the address counter set within the filter coefficient memory or the address counter designed within the read-write control module increments the address corresponding to the starting storage address by one every two system clock cycles and generates the corresponding address. The address counter can be synchronized with the counting timing of the reference address counter, the second folding address counter, and the first folding address counter or maintain a fixed delay, and can change with the storage address configured to change simultaneously with the first folding read address and the second folding read address read successively within a folding address read cycle. The filter coefficient in the storage address and the filtered data in the first folding read address and the second folding read address within the folding address read cycle are read into the filtering calculation module within the same folding address read cycle, forming a set of calculation items that are first added and then multiplied, that is, the sum of the filtered data in the first folding read address and the second folding read address is multiplied by the filter coefficient. In the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, the address corresponding to the storage address is incremented by 1. In this embodiment, there is no need to perform a self-decrement operation on the starting storage address. When the amount of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, there is no need to perform a loopback traversal of the storage address, thereby saving read operations. It should be noted that the starting storage address is predetermined and can be configured by a register.

[0112] Based on the above embodiment, the filtering calculation module is used to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, first control the to-be-filtered data in the first folding read address output by the data cache space to be added with the to-be-filtered data in the second folding read address output by the data cache space in each folding address read cycle; then multiply the result of the addition with the filter coefficients in the same reading order (synchronously changing counting timing) output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this process in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address, then multiply the filter coefficients in the intermediate calculation storage address with the to-be-filtered data in the first folding read address output by the data cache space in the same reading order, and then input the multiplication result into the adder for accumulation processing, to obtain the processed filtering result in the corresponding filtering cycle, thereby completing one filtering calculation, that is, completing the filtering calculation in one filtering cycle. In each filtering cycle, when the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter, the number of multiplication operations performed within the filtering calculation module is equal to half the number of taps of the FIR filter, and is implemented by time-sharing multiplexing of a multiplier, that is, a multiplier performs a multiplication operation once during each folding address read cycle. The filtering calculation module includes an adder and a multiplier. In this embodiment, the sum of the to-be-filtered data in the first folding read address and the to-be-filtered data in the second folding read address is input into the multiplier, and the filter coefficients read in the same cycle are also input into the multiplier to participate in a multiplication operation. The result of the multiplication in the cycle is then transmitted to the adder for accumulation calculation. Therefore, in this embodiment, the same multiplier resources are used in the filtering calculation module to implement multiplication operations of newly input to-be-filtered data with the same set of filter coefficients in different filtering cycles, thereby improving the reuse rate of multiplier resources under the conditions of different types of filter reading data.

[0113] Corresponding to Figure 4In the fourth filtering cycle, X8 (the data to be filtered in the first folding read address read for the first time, i.e., the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, i.e., the data to be filtered read for the second time) are a set of folding data, which are added together to obtain the first folding value. In the same folding address reading cycle, the filter coefficient h1 is read from the filter coefficient memory; then, X7 (the data to be filtered in the first folding read address read for the second time, i.e., the data to be filtered read for the third time) and X4 (the data to be filtered in the second folding read address read for the second time, i.e., the data to be filtered read for the fourth time) are another set of The folded data are added to obtain the second folded value. Within the same folded address reading cycle, the filter coefficient h2 is read from the filter coefficient memory; then, X6 (the data to be filtered in the first folded read address read for the third time, that is, the data to be filtered read for the fifth time) and X5 (the data to be filtered in the second folded read address read for the third time, that is, the data to be filtered read for the sixth time) are another set of folded data. The filter coefficient h3 in the intermediate calculation storage address is read from the filter coefficient memory. Generally, the filter coefficient in the intermediate calculation storage address is set to a fixed parameter, which is applicable to any FIR filter with an odd number of taps.

[0114] For these folded data, the filtering calculation module outputs the filter coefficients at the corresponding positions from the filter coefficient memory for multiplication to perform folding calculation. Specifically, the filtering result y6 obtained by the folding calculation is equal to: the product of the sum of X8 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) and the filter coefficient h1 read for the first time, the product of the sum of X7 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X4 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) and the filter coefficient h2 read for the second time, and the product of the sum of X6 (the data to be filtered in the first folding read address read for the third time, that is, the data to be filtered read for the fifth time) and X5 (the data to be filtered in the second folding read address read for the third time, that is, the data to be filtered read for the sixth time) and the filter coefficient h3 read for the third time.

[0115] It should be noted that the i in Xi can be used to represent its read address; when the second folding address counter is incremented once (a self-increment operation is performed on the second folding read address), the data to be filtered in the second folding read address changes from Xi to X(i+1). For example, when i=1, before the self-increment operation is performed, the data to be filtered X1 in the second folding read address 1 is read, and after the self-increment operation is performed, the data to be filtered X2 in the second folding read address 2 is read. Similarly, when the first folding address counter is decremented once (a self-decrement operation is performed on the first folding read address), the data to be filtered in the first folding read address changes from X(i+3)i to X(i+2). For example, when i=1, before the self-decrement operation is performed, the data to be filtered X4 in the first folding read address 4 is read, and after the self-decrement operation is performed, the data to be filtered X3 in the first folding read address 3 is read.

[0116] In summary, the present invention divides the filtering calculation stage adapted to the input number of the data to be filtered according to the relationship between the number of data to be filtered written into the data cache space and the transposition enable counting threshold of the FIR filter, and adopts different counting methods in different filtering calculation stages to generate read addresses adapted to the filtering calculation of first addition and then multiplication or first multiplication and then addition under the current data amount, so as to meet the correlation between the data to be filtered participating in the filtering calculation under different data input amounts. The read address generated by the counting of the present invention supports loop changes within the address range limited by the number of taps, so that the continuity of the data transmission to be filtered can be ensured by overwriting the old address with new data. On the other hand, the change of the read address as the counting starting point in each filtering calculation or each filtering cycle is related to the decimation rate or interpolation rate of the FIR filter, so that the self-addition operation of the read address in the same filtering cycle and / or the self-decrement operation of the read address in the same filtering cycle executes the filtering calculation within the filtering cycle, which can support the automatic counting and periodic filtering calculation requirements of FIR filters of different orders except half-band filters, and simultaneously extract valid data and filter to obtain valid filtering results from the real-time input data to be filtered.

[0117] It should be noted that the self-increment operation of the counter disclosed in the present invention is an addition counting operation of the counter, including but not limited to adding one or adding two. Each time the counter performs a self-increment operation, its count value increases by a certain value, and the count values ​​before and after the change are configured as addresses; the self-decrement operation of the counter is a subtraction counting operation of the counter. Each time the counter performs a self-decrement operation, its count value decreases by a certain value; therefore, the self-increment operation and the self-decrement operation of a counter generate addresses along different directions respectively.

[0118] It is worth noting that, in any of the aforementioned embodiments, the count value of the relevant counter is used to generate an address, and the numerical value 0, the numerical value 1, the count value and the numerical values ​​related thereto can be used to represent the serial number of the actual storage address of the corresponding input and output data in the data cache space or the filter coefficient memory. In order to simplify the description, any embodiment of the present invention simplifies the address indicated by the count value, numerical value, sum value or difference value to directly use the count value, numerical value, sum value or difference value to represent it.

[0119] Based on the above embodiment, an embodiment of writing the filtered data into the data cache space is further disclosed, wherein the read / write control module is configured to control the writing of the filtered data input externally into the data cache space according to the system clock cycle, specifically, writing one filtered data into the data cache space in each system clock cycle, so that the above embodiment has an implementation condition for determining the relationship between the number of filtered data written into the data cache space and the transposition enable count threshold of the FIR filter. In this embodiment, the read / write control module is configured to write one filtered data into the data cache space in the current system clock cycle and read one filtered data into the next system clock cycle. Optionally, the read / write control module sequentially reads the filtered data written into the data cache space according to the reference address generated by the reference address counter, the pre-read address generated by the pre-read address counter, the first folding read address generated by the first folding address counter, and the second folding read address generated by the second folding address counter, wherein the reference address, the pre-read address, the first folding read address, and the second folding read address all overlap with the previously determined write address.

[0120] Furthermore, an incremental counter is provided inside the read-write control module, and the read-write control module is used to control the incremental counter to add an offset to the current cache address each time a data to be filtered is written, so as to obtain the cache address of the next data to be filtered to be written, that is, the incremental counter is allowed to count by one according to the system clock cycle from the cache first address until the cache address (count value) generated by the count is equal to the difference between the number of taps of the FIR filter and the value 1 relative to the cache first address. Then, the cache first address is updated to the current cache address. , so that the subsequently written data to be filtered overwrites the data to be filtered first stored in the cache first address, and determines that a round of continuous cache address traversal of the data cache space is completed, that is, a loop traversal is completed. At this time, it is determined that the number of system clock cycles that have passed since writing a data to be filtered to the cache first address is equal to the number of taps of the FIR filter; wherein, the continuous cache address is composed of address units whose number is the number of taps of the FIR filter, so as to meet the number of input data required for filtering calculation under the number of taps of the FIR filter.

[0121] Specifically, the read-write control module is further configured to, after completing a round of traversal of continuous cache addresses, if new data to be filtered is continued to be written to the continuous cache addresses according to the system clock cycle control, set the incremental counter to an incremental initial value, and starting from the cache first address, each time a data to be filtered is written, overwrite the data to be filtered originally stored in the cache address with the currently written data to be filtered, and control the incremental counter to add an offset to the current cache address, that is, the incremental counter adds one and configures the obtained count value as a new cache address, thereby obtaining the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache first address is equal to the difference between the number of taps of the FIR filter and the value 1, update the cache first address to the currently obtained cache address, and adjust the count value of the incremental counter to the incremental initial value; it should be noted that the incremental initial value set by the incremental counter represents the address order of the cache first address in the data cache space; each count value generated by the incremental counter represents the address order of the cache addresses written in the corresponding system clock cycle in the data cache space.

[0122] It should be noted that, in view of the implementation process of the above modules of the present invention, an overall system structure is formed in a specific application, such as; Figure 3 Take a 5-tap FIR filter as an example. Figure 4 The example of a 6-tap FIR filter is given above. By analogy, the design of an N-tap filter is the same and falls within the scope of protection of the present invention.

[0123] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made based on the spirit and essence of the present invention are intended to be covered by the scope of protection of the present invention.

Claims

1. An FIR filter with automatic counting function, characterized in that: The FIR filter includes a read-write control module, a filter calculation module, a data buffer space and a filter coefficient memory; The read / write control module is used to control the writing of the filtered data input to the FIR filter into the data cache space, and to count and generate the read address; a read / write control module, configured to sequentially read the data to be filtered from the data cache space using a read address generated by counting according to a relationship between the amount of data to be filtered written into the data cache space and a transposition enable count threshold of the FIR filter, and transmit the read data to be filtered to the filter calculation module; a filter coefficient memory, configured to output the required filter coefficients to the filter calculation module in sequence according to the order in which the read-write control module reads the data to be filtered from the data cache space after the read-write control module starts reading the data to be filtered from the data cache space; A filtering calculation module is used to control the filtering calculation of the data to be filtered output by the data cache space and the filter coefficients output by the filter coefficient memory, wherein, when the filtering calculation module performs a filtering calculation, the read-write control module continues to control the new data to be filtered input to the FIR filter to be written into the data cache space but does not participate in the filtering calculation; The filtering calculation method is to match the size relationship between the amount of the to-be-filtered data written into the data cache space and the transposition enable count threshold of the FIR filter; The read-write control module also includes a reference address counter; The reference address counter is configured to perform a self-increment operation each time two pieces of data to be filtered are written into the data cache space, and generate a reference address, triggering the read / write control module to read the data to be filtered from the data cache space using the reference address, wherein the reference address is the first read address that needs to be traversed in the data cache space to start the current filtering calculation; the change in the count value generated by one self-increment operation of the reference address counter is a value of 2; When the filtering calculation module outputs a filtering result, it is determined that the FIR filter has passed a filtering cycle since the two to-be-filtered data were written, and that only one filtering calculation is completed within one filtering cycle; wherein the decimation rate of the FIR filter is 2 times; Wherein, while performing a filtering calculation in a current filtering cycle, it is allowed to continue writing new data to be filtered into the data cache space to start the next filtering cycle, so as to achieve a partially overlapping timing interval between two adjacent filtering cycles.

2. The FIR filter according to claim 1, wherein The FIR filter is also provided with a system clock source for counting and generating system clock cycles; The time taken to write one piece of data to be filtered is configured as one system clock cycle, and the time taken to read one piece of data to be filtered is configured as one system clock cycle; The amount of the data to be filtered written into the data cache space is equal to the amount of the data to be filtered sampled from the outside by the FIR filter.

3. The FIR filter according to claim 2, wherein: When the amount of to-be-filtered data written into the data cache space is represented by a change in the count value of the reference address counter, the transposition enable count threshold of the FIR filter is represented by the number of taps of the FIR filter.

4. The FIR filter according to claim 2, wherein: The method of sequentially reading the data to be filtered from the data cache space using a read address according to a relationship between the amount of the data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, and transmitting the read data to be filtered to the filtering calculation module includes: When the read-write control module determines that the amount of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the read-write control module is configured to read the to-be-filtered data in the pre-read address from the data cache space and transmit the data to the filtering calculation module; wherein the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; The pre-read address is obtained by counting from a corresponding reference address in each filtering cycle; the reference address in a filtering cycle is the first pre-read address involved in the reading operation in the filtering cycle.

5. The FIR filter according to claim 4, wherein: The read-write control module includes a pre-address counter and a read address selector; When the amount of the data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the read address selector selects the pre-address counter to generate the pre-address and outputs it to the data cache space to read the data to be filtered in the corresponding address; The pre-address counter is configured to, when the amount of to-be-filtered data in the write data cache space is less than or equal to the transposition enable count threshold of the FIR filter, perform a self-decrement operation once per system clock cycle, starting from the reference address within the current filtering cycle, and then trigger the read-write control module to read the to-be-filtered data from the pre-address read address obtained by each self-decrement operation, and then transmit the data to the filtering calculation module in sequence; wherein, each time the pre-address counter is decremented once, the change in the count value generated is a value of 1, and a pre-address read address is obtained after each self-decrement operation; An initial count value of the pre-address counter in each filtering cycle is the reference address generated by the reference address counter in a corresponding filtering cycle.

6. The FIR filter according to claim 5, wherein: When the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address set by the FIR filter, perform a self-addition operation on the starting storage address, and then output the filter coefficients in the storage address obtained by the self-addition to the filtering calculation module, until the address offset of the storage address obtained by the self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1, then record the latest storage address as the intermediate calculation storage address, perform a self-decrement operation on the intermediate calculation storage address, and then output the filter coefficients in the storage address obtained by the self-decrement to the filtering calculation module, until the address offset of the storage address obtained by the self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter and the value 1, and repeat in sequence until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered participating in the filtering calculation in the current filtering cycle; wherein the number of taps of the FIR filter is an odd number; In the process of performing the self-increment operation on the starting storage address, the storage address increases by 1 each time the self-increment operation is performed; in the process of performing the self-decrement operation on the intermediate calculation storage address, the storage address decreases by 1 each time the self-decrement operation is performed.

7. The FIR filter according to claim 5, wherein: When the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address matched by the FIR filter, perform a self-increment operation on the starting storage address, and then output the filter coefficient from the storage address obtained by the self-increment to the filtering calculation module until the address offset of the storage address obtained by the self-increment relative to the starting storage address is equal to half of the difference between the number of taps of the FIR filter and the value 2, then record the latest storage address as the intermediate calculation storage address, perform a self-decrement operation on the intermediate calculation storage address, and then output the filter coefficient from the storage address obtained by the self-decrement to the filtering calculation module until the address offset of the storage address obtained by the self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the FIR filter and the value 2, and repeat in sequence until the number of filter coefficients read from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered participating in the filtering calculation in the current filtering cycle; wherein the number of taps of the FIR filter is an even number; and the filtering calculation module continuously reads two identical filter coefficients from the intermediate calculation storage address; Among them, during the process of performing the self-increment operation on the starting storage address, the address indicated by the storage address increases by 1 each time the self-increment operation is performed; during the process of performing the self-decrement operation on the intermediate calculation storage address, the address indicated by the storage address decreases by 1 each time the self-decrement operation is performed.

8. The FIR filter according to claim 6 or 7, characterized in that: The filtering calculation module is used to control the data to be filtered output by the data cache space and the filter coefficients in the same reading order output by the filter coefficient memory to perform a multiplication operation when the amount of the data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold of the FIR filter, and input the result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; Among them, the multiplication operation in each filtering cycle is realized by time-sharing multiplexing of a multiplier; Wherein, the filtering calculation module includes an adder and a multiplier.

9. The FIR filter according to claim 2, wherein: The method of sequentially reading the data to be filtered from the data cache space using a read address according to a relationship between the amount of the data to be filtered written into the data cache space and the transposition enable count threshold of the FIR filter, and transmitting the read data to be filtered to the filtering calculation module includes: When the read-write control module determines that the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the read-write control module is configured to configure the reference address generated by the reference address counter as the first folding read address according to the counting timing of the reference address counter, and configure the sum of the reference address and the value 1 as the second folding read address; The read / write control module is further configured to configure a sum of the first folded read address and the second folded read address as a post-read address, and read the data to be filtered in the post-read address from the data cache space according to the counting timing of the reference address counter, and transmit the data to be filtered to the filtering calculation module; The transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter.

10. The FIR filter according to claim 9, wherein: The read-write control module includes a first folding address counter and a second folding address counter; When the amount of to-be-filtered data written into the data cache space is greater than a transposition enable count threshold of the FIR filter, the first folding address counter is configured to perform a self-decrement operation on the first folding read address in each filtering cycle to generate a new first folding read address, so as to trigger the read / write control module to read the to-be-filtered data from the first folding read address obtained by each self-decrement operation, until the number of self-decrement operations reaches a first preset folding sampling number, while still allowing new to-be-filtered data to be written into the data cache space; When the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the second folding address counter is also used to perform a self-addition operation on the second folding read address within each filtering cycle to generate a new second folding read address to trigger the read-write control module to read the data to be filtered from the second folding read address obtained by each self-addition operation until the number of self-addition operations reaches the second preset folding sampling number, but new data to be filtered is still allowed to be written into the data cache space.

11. The FIR filter according to claim 10, wherein: The first folding address counter is configured to perform a decrement operation on the first folding read address every two system clock cycles to obtain a new first folding read address, and record these two system clock cycles as a folding address read cycle; When the amount of the to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, under the control of the read-write control module, within a folding address read cycle, the to-be-filtered data in the first folding read address is read to the filter calculation module, and the to-be-filtered data in the second folding read address is read to the filter calculation module; The second folding address counter is used to perform a self-increment operation during the folding address read cycle to obtain a new second folding read address every two system clock cycles.

12. The FIR filter according to claim 11, wherein: The read-write control module also includes an address adder and a read address selector; an address adder for adding, within the folding address read cycle, a second folding read address generated by the second folding address counter and a first folding read address generated by the first folding address counter to generate a post read address within the folding address read cycle; When the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the read address selector selects the post-read address generated by the address adder and outputs it to the data cache space, so as to read the two data to be filtered in the corresponding address within the folded address read cycle.

13. The FIR filter according to claim 10, wherein: When the amount of to-be-filtered data in the write data cache space is greater than the transposition enable count threshold of the FIR filter, before the read-write control module determines to configure the reference address as the first folding read address, if the read-write control module determines that the reference address is equal to the filtering start address, the filtering target address is updated to the reference address, and the updated reference address is configured as the start address of the first folding read address. Then, the first folding address counter is used to perform a self-decrement operation on the first folding read address starting from the start address of the first folding read address; wherein, the change in the count value generated by one self-decrement operation of the first folding address counter is a value of 1; When the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold of the FIR filter, before the read-write control module determines to configure the reference address as the second folding read address, if the read-write control module determines that the reference address is equal to the filtering target address, the filtering starting address is updated to the reference address, and then the sum of the updated reference address and the value 1 is configured as the starting address of the second folding read address. Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address, wherein the change in the count value generated by the self-increment operation of the second folding address counter is a value of 1.

14. The FIR filter according to claim 13, wherein: The process of the first folding address counter performing a self-decrement operation on the first folding read address includes: configuring the starting address of the first folding read address as the first folding read address, and whenever the first folding read address is decremented to the filtering starting address, updating the filtering target address to the first folding read address in the next system clock cycle, so that the first folding read address implements address loop traversal within the address range limited by the number of taps of the FIR filter; and then the first folding address counter continues to perform a self-decrement operation on the first folding read address; The process of the second folding address counter performing a self-increment operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is self-incremented to the filtering target address, updating the filtering starting address to the second folding read address in the next system clock cycle, so that the second folding read address realizes address loop traversal within the address range limited by the number of taps of the FIR filter; then the second folding address counter continues to perform a self-increment operation on the second folding read address.

15. The FIR filter according to claim 2 or 14, characterized in that: When the count value of the reference address counter is the difference between the number of taps of the FIR filter and the value 2, the read-write control module updates the filter starting address to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the filter starting address to the reference address; When the count value of the reference address counter is the difference between the number of taps of the FIR filter and the numerical value 1, the read-write control module updates the sum of the filter starting address and the numerical value 1 to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the sum of the filter starting address and the numerical value 1 to the reference address.

16. The FIR filter according to claim 15, wherein: In each folding address read cycle, an address offset of a first folding read address corresponding to a first folding read address read relative to the filtering start address is equal to an address offset of a second folding read address corresponding to a second folding read address read; The filtering target address is an address pre-configured in the data cache space, and is the address with the largest order among the addresses participating in the read operation in each filtering cycle; The filtering starting point address is an address pre-configured in the data cache space, and is the smallest address in the order of the addresses read in each filtering cycle; The difference between the filtering target address and the filtering starting address is equal to the difference between the number of taps of the FIR filter and a value of 1.

17. The FIR filter according to claim 10, wherein: The number of taps of the FIR filter is an odd number; In one filtering cycle or one filtering calculation, when the second preset folding sampling number is greater than the first preset folding sampling number, the first folding read address stops changing ahead of the second folding read address; In a filtering cycle or a filtering calculation, when the second preset folding sampling number is less than the first preset folding sampling number, the second folding read address stops changing in advance of the first folding read address.

18. The FIR filter according to claim 10, wherein: When the number of taps of the FIR filter is an even number, the second preset folding sampling number is equal to the first preset folding sampling number.

19. The FIR filter according to claim 12, wherein: When the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, within each filtering cycle, start from the starting storage address matched by the FIR filter and perform a self-addition operation on the starting storage address once every two system clock cycles, so that the address corresponding to the starting storage address performs a self-addition operation once every two system clock cycles, and then sequentially read the filter coefficients in the storage address obtained by the self-addition operation from the filter coefficient memory to the filtering calculation module; When the number of taps of the FIR filter is an odd number, the address offset of the storage address obtained by the self-addition operation relative to the starting storage address is equal to half the difference between the number of taps of the FIR filter and the value 1, and then the most recently obtained storage address is recorded as the intermediate calculation storage address; In the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, a storage address is generated, and the change value of the storage address generated by two adjacent self-increment operations is a value of 1.

20. The FIR filter according to claim 19, wherein: The filtering calculation module is used to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, first control the to-be-filtered data in the first folding read address output by the data cache space to be added with the to-be-filtered data in the second folding read address output by the data cache space in each folding address read cycle; then perform a multiplication operation on the result of the addition with the filter coefficients in the same reading order output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this process in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address; wherein, in each filtering cycle, the multiplication operation is implemented by time-sharing multiplexing of a multiplier; the filtering calculation module includes an adder and a multiplier; the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; When the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, if the number of taps of the FIR filter is an odd number, the filter coefficient in the intermediate calculation storage address is multiplied by the data to be filtered in the first folded read address output by the data cache space in the same reading order, and the multiplication result is input into the adder for accumulation processing to obtain the processed filtering result within the corresponding filtering period.

21. The FIR filter according to claim 12, wherein: When the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, the filter coefficient memory is used to, within each filtering cycle, start from the starting storage address matched by the FIR filter and perform a self-addition operation on the starting storage address once every two system clock cycles, so that the address corresponding to the starting storage address performs a self-addition operation once every two system clock cycles, and then sequentially read the filter coefficients in the storage address obtained by the self-addition operation from the filter coefficient memory to the filtering calculation module; When the number of taps of the FIR filter is an even number, the address offset of the storage address obtained by the self-addition operation relative to the starting storage address is equal to half the difference between the number of taps of the FIR filter and the value 2, and then the most recently obtained storage address is recorded as the intermediate calculation storage address; In the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, a storage address is generated, and the change value of the storage address generated by two adjacent self-increment operations is a value of 1.

22. The FIR filter according to claim 19, wherein: The filtering calculation module is used to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold of the FIR filter, first control the to-be-filtered data in the first folding read address output by the data cache space to be added with the to-be-filtered data in the second folding read address output by the data cache space in each folding address read cycle; then perform a multiplication operation on the result of the addition with the filter coefficients in the same reading order output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this process in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address; wherein, in each filtering cycle, the multiplication operation is implemented by time-sharing multiplexing of a multiplier; the filtering calculation module includes an adder and a multiplier; the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; When the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, if the number of taps of the FIR filter is an even number, the data cache space is controlled to multiply the sum of the data to be filtered in the first folding read address and the data to be filtered in the second folding read address output within the same folding address read cycle with the filter coefficient in the intermediate calculation storage address, and then the multiplication result is input into the adder for accumulation processing to obtain the processed filtering result within the corresponding filtering cycle.

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