A latch resistant to soft errors

Abstract

The present invention provides a soft error resistant latch, which is composed of four pairs of NMOS and PMOS gates of inverters connected to each other to form an interlocking loop, four transmission gates, and a dual-input Mueller C unit. When the clock signal CLK is at a high level, the transmission gate is turned on, and when an error flip occurs at any storage node, the error signal is not stored. The dual-input Mueller C unit is turned off to prevent the output from being affected while reducing dynamic power consumption. When the clock signal CLK is at a low level, the latch is in a latching mode, the first to third transmission gates are turned off, the fourth transmission gate is turned on, and nodes S2 and S4 are used as inputs of the dual-input Mueller C unit to reach the output end, and data is continuously and stably transmitted from the output end. The present invention enables the latch to have the ability to resist single-particle flips through a special internal storage node feedback structure, and has a very low delay by using high-speed transmission gate technology. While ensuring excellent single-particle resistance, the circuit performance is greatly improved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a soft error resistant latch. Background Art

[0002] As a commonly used module in digital circuits, latches are very important sequential logic units in standard cell libraries. In harsh radiation environments, when particles are incident on sensitive nodes inside storage cells, the generated carriers may be collected by the source-drain diffusion region, causing the voltage of the affected nodes to be disturbed. If the injected charge exceeds the critical charge of this sensitive node, the value stored on the node will flip, directly affecting the logic function of the integrated circuit, so it is necessary to reinforce it against single particle flips.

[0003] Traditional latches are easily affected by single-particle upsets and errors occur. For example, triple-mode redundant registers can tolerate single-particle upsets that occur in any single common latch path, but this also makes the area, power consumption and delay very large, and the performance is not ideal.

[0004] Therefore, it is necessary to propose a new soft error-resistant latch to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a soft error resistant latch for solving the single event upset and soft error problems of the conventional latch in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a soft error resistant latch, comprising at least:

[0007] First to fourth inverters; first to fourth transmission gates; a dual-input Mueller C cell;

[0008] The first to fourth inverters are respectively formed by connecting an NMOS and a PMOS in series, wherein the first inverter is formed by connecting the drain of the first PMOS to the drain of the first NMOS; the second inverter is formed by connecting the drain of the second PMOS to the drain of the second NMOS; the third inverter is formed by connecting the drain of the third PMOS to the drain of the third NMOS; the fourth inverter is formed by connecting the drain of the fourth PMOS to the drain of the fourth NMOS;

[0009] A node S1 at which the drain of the first PMOS and the drain of the first NMOS are connected is connected to the gate of the second PMOS, the gate of the fourth NMOS and the data output end of the first transmission gate;

[0010] A node S2 at which the drain of the second PMOS and the drain of the second NMOS are connected is connected to the gate of the first NMOS, the gate of the third NMOS and the first input terminal of the dual-input Mueller C unit;

[0011] A node S3 at which the drain of the third PMOS is connected to the drain of the third NMOS is connected to the gate of the second NMOS, the data output terminal of the second transmission gate, and the gate of the fourth PMOS;

[0012] A node S4 at which the drain of the fourth PMOS and the drain of the fourth NMOS are connected is connected to the gate of the third PMOS, the gate of the first PMOS and the second input terminal of the dual-input Mueller C unit;

[0013] The dual-input Mueller C unit is composed of a fifth and a sixth PMOS and a fifth and a sixth NMOS, wherein the fifth and the sixth PMOS are connected in series end to end, the fifth and the sixth NMOS are connected in series end to end, and the drain of the sixth PMOS is connected to the drain of the sixth NMOS, and the connection node M is connected to the data input terminal of the fourth transmission gate;

[0014] The data input terminals of the first to third transmission gates are connected to each other; the data output terminal of the third transmission gate is connected to the output terminal of the fourth transmission gate, and the output terminal serves as the output node Q of the latch.

[0015] Preferably, the drain of the fifth PMOS is connected to the source of the sixth PMOS; the source of the sixth NMOS is connected to the drain of the fifth NMOS.

[0016] Preferably, sources of the first to fifth NMOS are grounded.

[0017] Preferably, the gate of the fifth PMOS is connected to the gate of the fifth NMOS, and the node connected thereto serves as the first input terminal of the dual-input Mueller C unit; the gate of the sixth PMOS is connected to the gate of the sixth NMOS, and the node connected thereto serves as the second input terminal of the dual-input Mueller C unit.

[0018] Preferably, sources of the first to fifth PMOS are connected to a power supply voltage.

[0019] Preferably, the first to fourth transmission gates are respectively provided with a first and a second clock terminal, and the first clock terminal of the first to third transmission gates and the second clock terminal of the fourth transmission gate are connected to the same clock signal CLK; the second clock terminal of the first to third transmission gates and the first clock terminal of the fourth transmission gate are connected to a clock signal CLKB which is inverted to the clock signal CLK.

[0020] Preferably, when the clock signal CLK is at a high level and the clock signal CLKB is at a low level, the latch is in a transmission mode, the first to third transmission gates are turned on, and the input signal D reaches the nodes S1 and S3 through the data input terminals of the first and second transmission gates; the input signal D reaches the output node Q through the third transmission gate.

[0021] Preferably, when the clock signal CLK is at a low level and the clock signal CLKB is at a high level, the latch is in a latching mode, the first to third transmission gates are closed, the fourth transmission gate is opened, the node S2 and the node S4 serve as inputs of the dual-input Mueller C unit, pass through the node M, and then reach the output terminal Q through the fourth transmission gate, and data is continuously and stably transmitted from the output terminal Q.

[0022] As described above, the soft error resistant latch of the present invention has the following beneficial effects: the soft error resistant latch proposed in the present invention has the ability to resist single particle upset through a special internal storage node feedback structure. By using high-speed transmission gate technology, the proposed latch has a very low delay. While ensuring excellent single particle resistance capability, the circuit performance is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of a latch circuit for resisting soft errors in the present invention;

[0024] Figure 2 Shown is a simulation waveform diagram of the soft error-resistant latch in the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] See also Figure 1 to Figure 2 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] The present invention provides a latch resistant to soft errors, such as Figure 1 As shown, Figure 1The figure shows a schematic diagram of a latch circuit for resisting soft errors in the present invention, wherein the latch at least comprises:

[0028] First to fourth inverters; first to fourth transmission gates; a dual-input Mueller C cell;

[0029] The first to fourth inverters are respectively formed by connecting an NMOS and a PMOS in series, wherein the first inverter is formed by connecting the drain of the first PMOS (P1) to the drain of the first NMOS (N1); the second inverter is formed by connecting the drain of the second PMOS (P2) to the drain of the second NMOS (N2); the third inverter is formed by connecting the drain of the third PMOS (P3) to the drain of the third NMOS (N3); the fourth inverter is formed by connecting the drain of the fourth PMOS (P4) to the drain of the fourth NMOS (N4);

[0030] A node S1 at which the drain of the first PMOS (P1) and the drain of the first NMOS (N1) are connected is connected to the gate of the second PMOS (P2), the gate of the fourth NMOS (N4) and the data output terminal of the first transmission gate TG1;

[0031] A node S2 at which the drain of the second PMOS (P2) and the drain of the second NMOS (N2) are connected is connected to the gate of the first NMOS (N1), the gate of the third NMOS (N3) and the first input terminal of the dual-input Mueller C unit;

[0032] A node S3 at which the drain of the third PMOS (P3) and the drain of the third NMOS (N3) are connected is connected to the gate of the second NMOS (N2), the data output terminal of the second transmission gate TG2, and the gate of the fourth PMOS (P4);

[0033] A node S4 at which the drain of the fourth PMOS (P4) and the drain of the fourth NMOS (N4) are connected is connected to the gate of the third PMOS (P3), the gate of the first PMOS (P1) and the second input terminal of the dual-input Mueller C unit;

[0034] The dual-input Mueller C unit is composed of a fifth and a sixth PMOS and a fifth and a sixth NMOS, wherein the fifth and the sixth PMOS are connected in series end to end, and the fifth and the sixth NMOS are connected in series end to end, and the drain of the sixth PMOS (P6) is connected to the drain of the sixth NMOS (N6), and the node M of the connection is connected to the data input terminal of the fourth transmission gate TG4;

[0035] The data input terminals D of the first to third transmission gates (TG1-TG3) are connected to each other; the data output terminal of the third transmission gate TG3 is connected to the output terminal of the fourth transmission gate TG4, which serves as the output node Q of the latch.

[0036] In the present invention, the drain of the fifth PMOS (P5) is connected to the source of the sixth PMOS (P6); the source of the sixth NMOS (N6) is connected to the drain of the fifth NMOS (N5). The sources of the first to fifth NMOS are grounded.

[0037] The present invention further comprises that the gate of the fifth PMOS (P5) of this embodiment is connected to the gate of the fifth NMOS (N5), and the node to which they are connected serves as the first input terminal of the dual-input Mueller C unit; the gate of the sixth PMOS (P6) is connected to the gate of the sixth NMOS (N6), and the node to which they are connected serves as the second input terminal of the dual-input Mueller C unit.

[0038] Furthermore, in the present invention, sources of the first to fifth PMOS in this embodiment are connected to a power supply voltage.

[0039] The present invention further comprises that the first to fourth transmission gates of the present embodiment are respectively provided with a first and a second clock terminal, and the first clock terminal of the first to third transmission gates and the second clock terminal of the fourth transmission gate are connected to the same clock signal CLK; the second clock terminal of the first to third transmission gates and the first clock terminal of the fourth transmission gate are connected to a clock signal CLKB which is inverted to the clock signal CLK.

[0040] The present invention further discloses that, in this embodiment, when the clock signal CLK is at a high level and the clock signal CLKB is at a low level, the latch is in a transmission mode, the first to third transmission gates are turned on, and the input signal D reaches the nodes S1 and S3 through the data input terminals of the first and second transmission gates; the input signal D reaches the output node Q through the third transmission gate.

[0041] In the present invention, when the clock signal CLK is at a high level and the clock signal CLKB is at a low level, for the nodes S1-S4, since the transmission gate is in an open state, when an error flip occurs at any storage node, the error signal will not be stored, because data is continuously transmitted to the input terminal D, and the error is quickly refreshed and will not be latched. The dual-input Mueller C unit is turned off to prevent the output from being affected while reducing dynamic power consumption. Compared with the traditional latch input signal D to the output node, it needs to pass through a transmission gate and two inverters. Due to the use of a high-speed transmission gate structure, the delay of the high-speed single-particle flip self-recovery latch is greatly reduced.

[0042] In the present invention, when the clock signal CLK is at a low level and the clock signal CLKB is at a high level, the latch is in latch mode, the first to third transmission gates are closed, the fourth transmission gate is opened, the node S2 and the node S4 serve as inputs of the dual-input Mueller C unit, pass through the node M, and reach the output terminal Q through the fourth transmission gate, and data is continuously and stably transmitted from the output terminal Q.

[0043] When the latch is in latch mode, there are two situations:

[0044] The first case: Assuming that the data "0" is stored at this time, there are nodes S1 = 0, S2 = 1, S3 = 0, S4 = 1, and Q = 0. If the node S1 flips and the logic value changes from "0" to "1", the second PMOS (P2) is turned off and the fourth NMOS (N4) is turned on. Since the node S3 is not affected, the second NMOS (N2) remains off and the fourth PMOS (P4) remains on. Node S2 still remains "1"; and for node S4, the fourth PMOS (P4) and the fourth NMOS (N4) are turned on at the same time, in an uncertain state, but since the turning on of N4 is caused by the interference pulse, as the interference pulse weakens, the P4 tube will pull the state of node S4 up to "1". At the same time, the P1 tube is turned off, and the N1 tube pulls the value of node S1 down to "0", and the node S1 returns to its original correct logic value. During the process of node S1 recovering to the correct state, due to the shielding effect of the clock-controlled dual-input Mueller C unit, the output Q remains unchanged. As node S1 recovers to the correct logic value, the dual-input Mueller C unit resumes output and the circuit returns to normal. If node S2 flips and the logic value changes from "1" to "0", N1 and N3 tubes are turned off. Since node S4 is not affected, P3 and P1 tubes remain closed. Nodes S1 and S3 are both in high-impedance state and the logic state remains unchanged, so P2 is still turned on, N2 is turned off, and node S2 is pulled up to "1" and restored to the original correct logic value. During the process of node S2 recovering to the correct state, due to the shielding effect of the clock-controlled two-input Mueller C unit, the output Q remains unchanged. As node S2 recovers to the correct logic value, the Mueller C unit resumes output and the circuit returns to normal. Similarly, if the internal storage nodes S3 and S4 flip, they can also recover to the correct logic value.

[0045] The second case: Assuming that the data "1" is stored, then S1=1, S2=0, S3=1, S4=0, Q=1. If node S1 flips and the logic value changes from "1" to "0", the P2 tube is turned on and the N4 tube is turned off. Since node S3 is not affected, the P4 tube remains off and the N2 tube is turned on. Node S4 still remains "0"; as for node S2, the P2 tube and the N2 tube are turned on at the same time and are in an uncertain state, but since the opening of P2 is caused by the interference pulse, as the interference pulse weakens, the N2 tube will pull the state of node S1 to "0". At this time, the N1 tube is turned off, and the P1 tube pulls the value of node S1 up to "1", and node S1 returns to its original correct logic value. In the process of node S1 returning to the correct state, due to the shielding effect of the two-input Mueller C unit controlled by the clock, the output Q remains unchanged. As node S1 returns to the correct logic value, the Mueller C unit resumes output and the circuit returns to normal. If node S2 flips and the logic value changes from "0" to "1", N1 and N3 tubes are turned on. Since node S4 is not affected, P1 and P3 tubes remain turned on. At this time, nodes S1 and S3 are in an uncertain state, but since the opening of N1 and N3 is caused by the interference pulse, as the interference pulse weakens, P1P3 tubes will pull the state of node S1S3 up to "1". At this time, P2 tube is closed and N2 tube is turned on, pulling the value of node S2 down to "0" and restoring to the original correct logic value. In the process of node S2 recovering to the correct state, due to the shielding effect of the two-input Mueller C unit controlled by the clock, the output Q remains unchanged. As node S2 recovers to the correct logic value, the Mueller C unit resumes output and the circuit returns to normal. The situation of nodes S3 and S4 is similar. If a flip occurs, the correct logic value can also be restored.

[0046] Assuming that a soft error occurs at node Q and the logic value changes, since the clock-controlled dual-input Mueller C unit is in the on state, the correct logic values ​​on the storage nodes S2 and S4 will refresh the error signal of node Q through the dual-input Mueller C unit, and node Q will recover to the correct logic value.

[0047] Based on the above analysis, it can be concluded that no matter which node the soft error occurs on, it will be restored to the correct logic level after the feedback logic of the internal redundant storage node. Therefore, the high-speed single-particle upset self-recovery latch resistant to soft errors proposed in the present invention has a single-particle upset self-recovery function.

[0048] like Figure 2 As shown, Figure 2The figure shows the simulation waveform of the soft error-resistant latch in the present invention. It can be seen that when any node of the latch is disturbed and flipped, the output signal Q can remain correct and the flipped node can be restored to the correct logic state. Therefore, the latch can resist single-particle flipping and has the ability of self-recovery.

[0049] In summary, the present invention proposes a soft error resistant latch, which has the ability to resist single particle upset through a special internal storage node feedback structure. By using high-speed transmission gate technology, the proposed latch has very low delay, and while ensuring excellent single particle resistance, the circuit performance is greatly improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A soft error resistant latch, characterized in that: At least: First to fourth inverters; first to fourth transmission gates; a dual-input Mueller C cell; The first to fourth inverters are respectively formed by connecting an NMOS and a PMOS in series, wherein the first inverter is formed by connecting the drain of the first PMOS to the drain of the first NMOS; the second inverter is formed by connecting the drain of the second PMOS to the drain of the second NMOS; the third inverter is formed by connecting the drain of the third PMOS to the drain of the third NMOS; the fourth inverter is formed by connecting the drain of the fourth PMOS to the drain of the fourth NMOS; A node S1 at which the drain of the first PMOS and the drain of the first NMOS are connected is connected to the gate of the second PMOS, the gate of the fourth NMOS and the data output end of the first transmission gate; A node S2 at which the drain of the second PMOS and the drain of the second NMOS are connected is connected to the gate of the first NMOS, the gate of the third NMOS and the first input terminal of the dual-input Mueller C unit; A node S3 at which the drain of the third PMOS is connected to the drain of the third NMOS is connected to the gate of the second NMOS, the data output terminal of the second transmission gate, and the gate of the fourth PMOS; A node S4 at which the drain of the fourth PMOS and the drain of the fourth NMOS are connected is connected to the gate of the third PMOS, the gate of the first PMOS and the second input terminal of the dual-input Mueller C unit; The dual-input Mueller C unit is composed of a fifth and a sixth PMOS and a fifth and a sixth NMOS, wherein the fifth and the sixth PMOS are connected in series end to end, the fifth and the sixth NMOS are connected in series end to end, and the drain of the sixth PMOS is connected to the drain of the sixth NMOS, and the connection node M is connected to the data input terminal of the fourth transmission gate; The data input terminals of the first to third transmission gates are connected to each other; the data output terminal of the third transmission gate is connected to the output terminal of the fourth transmission gate, and the output terminal serves as the output node Q of the latch.

2. The soft error resistant latch according to claim 1, characterized in that: The drain of the fifth PMOS is connected to the source of the sixth PMOS; the source of the sixth NMOS is connected to the drain of the fifth NMOS.

3. The soft error resistant latch according to claim 2, characterized in that: Sources of the first to fifth NMOSs are grounded.

4. The soft error resistant latch according to claim 1, characterized in that: The gate of the fifth PMOS is connected to the gate of the fifth NMOS, and the node connected thereto serves as the first input terminal of the dual-input Mueller C unit; the gate of the sixth PMOS is connected to the gate of the sixth NMOS, and the node connected thereto serves as the second input terminal of the dual-input Mueller C unit.

5. The soft error resistant latch according to claim 1, characterized in that: Sources of the first to fifth PMOSs are connected to a power supply voltage.

6. The soft error resistant latch according to claim 1, characterized in that: The first to fourth transmission gates are respectively provided with first and second clock terminals, and the first clock terminals of the first to third transmission gates and the second clock terminal of the fourth transmission gate are connected to the same clock signal CLK; The second clock terminals of the first to third transmission gates and the first clock terminal of the fourth transmission gate are connected to a clock signal CLKB which is inversely proportional to the clock signal CLK.

7. The soft error resistant latch according to claim 6, characterized in that: When the clock signal CLK is at a high level and the clock signal CLKB is at a low level, the latch is in a transmission mode, the first to third transmission gates are turned on, and the input signal D reaches the nodes S1 and S3 through the data input terminals of the first and second transmission gates; the input signal D reaches the output node Q through the third transmission gate.

8. The soft error resistant latch according to claim 6, characterized in that: When the clock signal CLK is at a low level and the clock signal CLKB is at a high level, the latch is in latch mode, the first to third transmission gates are closed, the fourth transmission gate is opened, the node S2 and the node S4 serve as the input of the dual-input Mueller C unit, pass through the node M, and reach the output terminal Q through the fourth transmission gate, and data is continuously and stably transmitted from the output terminal Q.

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