Control of semiconductor devices

Abstract

The present invention relates to the control of semiconductor devices, in particular MOS devices, in order to reduce RTS / flicker noise. A circuit (100) comprises a first MOS device (103, 104) and a bias controller (107). The circuit is capable of at least one first circuit state (P RO ) and the second circuit state (P RST ) operation, in the first circuit state, the first MOS device is active to contribute to a first signal (Sout), and in the second circuit state, the first MOS device does not contribute to the first signal. The bias controller is operable to control the voltage at one or more terminals of the first MOS device to apply a pre-bias voltage (Vout) during instances of the second circuit state. PB1 、V PB2 ). The pre-bias is applied to set an occupied state of charge carrier traps within the first MOS device to limit noise during subsequent operation in the first circuit state. In an embodiment, the bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Description

Technical Field

[0001] The field of representative embodiments of the present disclosure relates to methods, apparatus, and / or implementations related to or relating to the control of semiconductor devices, particularly the control and / or operation of MOS devices such as transistors. Background Art

[0002] Semiconductor devices such as MOS transistors are used in a variety of applications. A known problem with such devices is random telegraph signal (RTS) noise generated by traps in the semiconductor material. Crystal dislocations or similar defects (e.g., at layer interfaces or due to body defects) may form traps in the semiconductor material (e.g., gate dielectric) of a MOS device. Such traps can capture charge carriers, i.e., electrons or holes, which can then be released spontaneously. Capturing or releasing charge carriers changes the gate charge, which will affect the threshold voltage or conductivity of the channel below. Therefore, overtime capture and release of charge carriers can introduce noise components into the output of the MOS device. The term RTS noise is generally used to refer to the noise contribution from individual traps capturing or releasing charge carriers. The term flicker noise is sometimes used to refer to the body effect of traps, for example, which is actually the sum of the effects of all traps in a semiconductor device.

[0003] The impact of RTS noise is generally greater for MOS transistors with smaller gate areas and / or manufactured with smaller semiconductor process node geometries. The effect of trapped charge will generally be proportionally greater for MOS devices with smaller gate areas. Moreover, manufacturing using smaller process node sizes can result in greater stress than manufacturing processes with larger feature sizes, which can mean that defects are more of a problem.

[0004] Conventionally, semiconductor manufacturing processes with relatively small process node sizes are primarily used to implement circuits for pure digital processing, where the nature of the digital processing may be largely unaffected by RTS noise. However, increasingly, it may be desirable to implement at least some analog or mixed signal circuits using MOS transistors with such relatively small process node sizes. Summary of the invention

[0005] Embodiments of the present disclosure are directed to semiconductor devices and operations thereof that mitigate at least some of the problems of RTS noise and / or flicker noise.

[0006] According to one aspect of the present disclosure, a circuit is provided, the circuit comprising a first MOS device and a bias controller, wherein:

[0007] The circuit is configured to be operable in a first circuit state in which the first MOS device is active to facilitate a first signal and in a second circuit state in which the first MOS device does not facilitate the first signal;

[0008] the bias controller being configured to be operable to control a voltage at one or more terminals of the first MOS device to apply a pre-bias to the first MOS device during an instance of the second circuit state, wherein the pre-bias is applied to set an occupancy state of charge carrier traps within the first MOS device to limit noise from the first MOS device during subsequent operation of the first circuit state; and

[0009] The bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

[0010] In some examples, the one or more operating conditions may include operating conditions that affect kinetics of charge carrier capture by the charge carrier trap within the first MOS device. In some examples, one of the one or more operating conditions may include temperature. The bias controller may be configured to receive an indication of temperature from a temperature sensor.

[0011] In some examples, the one or more operating conditions may include an indication of monitored noise. In some examples, the indication of monitored noise may be determined from a feedback signal derived from the first signal. In some examples, the indication of monitored noise may be determined from one or more test signals derived from a test module including at least one test MOS device.

[0012] In some examples, one of the one or more operating conditions may include an operating mode for a system including the circuit. In some examples, the system may operate in a plurality of different modes, and the different modes may have different requirements for at least one of: noise performance or signal quality; power consumption; and operating rate.

[0013] The bias controller may be configured to control the amplitude of the bias voltage applied to the first MOS device as a parameter of the pre-bias. The bias controller may be configured to control the duration of the bias voltage applied to the first MOS device as a parameter of the pre-bias. The bias controller may be configured to control the duration between consecutive applications of the pre-bias to the first MOS device as a parameter of the pre-bias. The bias controller may be configured to control the shape of the waveform of the bias voltage applied to the first MOS device as a parameter of the pre-bias.

[0014] In some examples, the first signal is an analog signal.

[0015] In some examples, the circuit can be configured to operate in a sequence of states that includes at least one instance of the second circuit state, regardless of whether a pre-bias voltage is applied during the instance of the second circuit state.

[0016] The bias controller may additionally be configured to be operable to control a voltage at one or more terminals of at least one additional MOS device to pre-bias the at least one additional MOS device.

[0017] The bias controller may include a processor configured to receive an indication of at least one operating condition and determine the at least one parameter of the pre-bias voltage to be applied. The bias controller may include a voltage controller for controlling at least one voltage applied to a terminal of the first MOS device based on the determined at least one parameter.

[0018] In some examples, the circuit may be one of: a sensor circuit; a digital-to-analog converter circuit, an analog-to-digital converter circuit; and an analog memory cell circuit.

[0019] On the other hand, a circuit is provided, comprising a first MOS device and a bias controller, wherein: the bias controller is configured to be operable to control a voltage at one or more terminals of the first MOS device to apply a pre-bias to the first MOS device, wherein the pre-bias is applied to set an occupancy state of charge carrier traps within the first MOS device to limit noise from the first MOS device during subsequent operation; and the bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

[0020] Yet another aspect relates to a bias controller for controlling a bias voltage applied to a first MOS device of a circuit, the bias controller being operable to apply a pre-bias to the first MOS device so as to set a defined occupancy state of a charge carrier trap within the first MOS device, wherein the bias controller dynamically adjusts the applied pre-bias in response to one or more operating conditions.

[0021] Any of the various features of the various implementations discussed herein may be implemented with any or more of the other described features in any and all suitable combinations, unless explicitly stated to the contrary. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to better understand the examples of the present disclosure, and to more clearly show how the examples may be implemented, reference will now be made, by way of example only, to the following drawings, in which:

[0023] Figure 1 One example of a pixel sensor circuit having a bias controller for applying a selectively variable pre-bias voltage is shown;

[0024] Figure 2 An example of a bias controller is shown;

[0025] Figure 3 An example of a current-mode DAC with a bias controller is shown;

[0026] Figure 4 An example of a sampling ADC with a bias controller is shown; and

[0027] Figure 5 An example of an analog memory cell circuit with a bias controller is shown. DETAILED DESCRIPTION

[0028] The following description sets forth example embodiments according to the present disclosure. Additional example embodiments and implementations will be apparent to those of ordinary skill in the art. In addition, those of ordinary skill in the art will recognize that various equivalent technologies may be applied in place of or in conjunction with the embodiments discussed below, and all such equivalents should be deemed to be encompassed in the present disclosure.

[0029] Embodiments of the present disclosure relate to apparatus and methods for control of semiconductor devices, particularly MOS devices (such as MOS transistors), which at least mitigate the problem of RTS / flicker noise. Embodiments also relate to circuits including MOS devices and control thereof. In some examples, the circuits may be circuits involving generation and processing of one or more analog signals, i.e., analog or mixed signal circuits, but the principles may be applied to any circuit in which RTS noise is a problem, including digital processing circuits.

[0030] As discussed above, MOS devices may be subject to RTS or flicker noise during use. If such RTS or flicker noise occurs when the circuit is in a first state in which the MOS device is active to contribute to the signal of interest, any RTS or flicker noise from the MOS device may appear in the signal of interest.

[0031] In embodiments of the present disclosure, voltages at one or more terminals of a MOS device may be controlled prior to the circuit operating in a first state to apply a bias voltage (referred to herein as a pre-bias) to the MOS device in order to set a desired fill state or occupancy of charge carrier traps of the MOS device, e.g., to cause the traps to be filled. The pre-bias is applied in order to reduce the amount of RTS noise during subsequent operation in the first state when the MOS device is active to contribute to a signal of interest.

[0032] As will be appreciated by those skilled in the art, there will be a time constant associated with the occupancy of a trap, e.g., if the trap is filled, there will be a time constant associated with the release of the associated charge carrier. The time constant involved in the carrier release of RTS noise is typically a fraction of a second. Therefore, if it is possible to ensure that all traps are in a given state, e.g., all traps are filled, and then all processing or readout is performed within a small fraction of the release time constant, the probability of RTS noise affecting the output is greatly reduced. The occupied state of the trap can be set by appropriately biasing the MOSFET, e.g., the trap can be filled, e.g., so that the surface is in an accumulation or even depletion state rather than the normal inversion state, but not applying enough voltage on the dielectric to cause significant tunneling current. Therefore, if a pre-bias is applied that sets a particular occupied state of the trap (e.g., tends to cause substantially all traps to be filled), the amount of RTS noise will be reduced for a period of time in subsequent operation, which in some cases may be on the order of a fraction of a second. Therefore, before the circuit operates in the first state where the MOS devices are active to contribute signals of interest and thus noise is problematic, a pre-bias is applied to set the occupied or filled state of the traps to reduce RTS or flicker noise when operating in the first state.

[0033] The pre-bias voltage will generally be applied when the MOS device is not active to contribute to the signal of interest. Thus, the pre-bias voltage may be applied during at least a portion of the time when the circuit is in a second circuit state in which the MOS device is not used to contribute to the signal of interest and during which a bias voltage may be applied to one or more terminals of the MOS device.

[0034] There are many circuits where during normal operation the circuit can be controlled to operate in different states in a periodic or cyclic manner, for example based on a defined sampling rate, and the states can include a first state in which the MOS device is active to contribute to the signal of interest and a second state in which the MOS device does not contribute to the signal of interest. For such circuits, a pre-bias can be applied during at least a portion of the time that the circuit is in the second state.

[0035] For example, some sensor circuits or analog-to-digital converters (ADCs) may involve a sensing phase in which a charge / voltage is formed at a sampling node in response to an associated input, and a subsequent processing or readout phase in which the charge / voltage at the sampling node is sampled or processed. In some examples, there may additionally be a reset phase to reset the sampling node before the next sensing phase. The processing circuit may include a MOS device that is actively in a processing or readout phase, which produces an output signal of interest, and a pre-bias may be applied prior to the processing phase, such as during a sensing or reset phase, depending on the type of circuit. Similarly, some digital-to-analog converters (DACs) that use MOS devices to generate analog outputs based on digital inputs may also involve a short return-to-zero phase between consecutive sampling cycles to reduce transients, and a pre-bias may be applied during the return-to-zero phase.

[0036] Figure 1 One example of a circuit is shown that includes MOS devices and operates in a sequence of circuit states or phases to generate an analog output signal. Figure 1 The circuit in the example is a pixel sensor circuit 100 for a photodetector. Figure 1 An active pixel sensor circuit is shown that includes a pinned photodiode and four transistors, which, as will be appreciated by those skilled in the art, is a known type of pixel circuit for photosensor arrays. Figure 1 Some example waveforms are also shown to illustrate the timing of the various operating phases.

[0037] Figure 1 A photodiode 101 is shown, which is configured as a pinned photodiode and is coupled to a sampling node 102. The sampling node is coupled to the gate of a MOS transistor 103, which together with a MOS transistor 104 provides a source follower buffer. At least during readout, with a suitable control voltage V C The gate of transistor 104 is driven to provide the desired source follower behavior. Pixel select transistor 105 allows the pixel to be selectively connected to a row / column bus circuit (not shown) to provide an output signal Sout for readout. Reset transistor 106 is provided to enable the photodiode / pixel to be reset.

[0038] As will be appreciated by those skilled in the art, such a pixel sensing circuit 100 may operate in a sequence of states or phases. RST During this period, the reset transistor is enabled so that the voltage at the sampling node 102 is set equal to the reset voltage V R (less than the threshold voltage of reset transistor 106 for soft reset). Reset transistor 196 is then turned off and the circuit enters the sensing phase P SENDuring this period, light incident on the pinned photodiode causes a change in charge and a change in voltage at the sampling node due to self-integration of the pinned photodiode 101. At the end of the sensing phase, the select transistor 105 can be enabled to provide readout of the pixel. Since the sampling node is coupled to the gate of the transistor 103 of the source follower, the voltage at this phase determines the output of the source follower, which is provided as the output signal Sout via the select transistor 105.

[0039] Those skilled in the art will understand that reference Figure 1 The circuit and operation described are merely one example, and there are alternative circuits and / or operating methods that may be implemented.

[0040] The circuit 100 also includes a bias controller 107 for applying a selectively variable pre-bias to at least one of the MOS devices to mitigate RTS noise during the readout phase. Thus, a pre-bias is applied to at least one of the MOS devices that contributes to the output signal Sout during the readout phase. Figure 1 The bias controller 107 is shown to apply a pre-bias voltage to one or both of the source follower transistors 103 and 104, since it is these transistors that are used during the readout phase P. RO During this period, an output signal Sout is generated. In some embodiments, a pre-bias voltage may be additionally or alternatively applied to the select transistor 105. As described above, RTS noise has a proportionally greater effect on transistors with smaller gate areas, and therefore it may be advantageous to pre-bias a smaller MOS device of the circuit that contributes to the output signal, which in this example may be transistors 103 and / or 104.

[0041] As discussed above, a pre-bias is applied to promote a desired occupancy of traps within a MOS device, such as causing all traps to be filled or traps to be drained. Pre-bias conditions may be defined to set the filling of traps in a MOS device structure by draining traps or filling traps or to set some other similar temporary atomic-level structural change in a MOS structure so as to reduce the likelihood that traps in the MOS structure will randomly fill or drain during subsequent operations in a readout phase. Thus, a pre-bias may be applied such that at the end of the pre-bias, substantially all traps are expected to be in a desired occupied state, such as filled or drained.

[0042] A pre-bias voltage may be applied to bias the MOS device so as to cause the MOS device to move out of an inversion state (which may be the normal operating state) and into an accumulation or depletion state. The pre-bias voltage may generally be applied so as to avoid generating any significant tunneling current.

[0043] The pre-bias may be applied by applying a suitably controlled bias voltage to one or more of the terminals of the MOS device. Thus, a control voltage may be applied to one or more of the gate terminal, the body terminal, the source terminal or the drain terminal, respectively.

[0044] Thus, in addition to the bias condition of the MOS device that would be applied in normal operation, the circuit may be configured to operate with the MOS device under another bias condition. The additional bias condition is used to pre-bias the MOS device prior to processing or readout operations to reduce time-dependent corruption of the associated output by flicker or telegraph noise during processing or readout operations. The pre-bias condition may be defined to set the filling of traps in the MOS structure by emptying the traps or filling the traps or other similar temporary atomic-level structural changes in the MOS structure to reduce the likelihood that traps in the MOS structure will randomly fill or empty during subsequent use.

[0045] The pre-bias condition may correspond to an accumulation mode or, alternatively, a depletion mode of a MOS device. For NMOS, accumulation generally corresponds to a negative gate voltage. Additionally, advantageously, the substrate may be slightly forward biased relative to the source or particles, or at least not reverse biased. Thus, the pre-bias condition may involve applying a gate voltage or body voltage that is different from that of a read operation.

[0046] G S B Pre-bias -VN +VP +VP

[0047] Table 1

[0048] Table 1 shows examples of voltages applied to the terminals of an NMOS device to drive it to the accumulation state.

[0049] In this example, in the pre-biased state, the control gate terminal G takes a sufficiently negative value to cause the NMOS to enter the accumulation state, or at least to leave the inversion state and enter the depletion state, but the negative value is not enough to cause a significant tunneling current. Preferably, the substrate is at the same voltage as the source or drain, or slightly more positive than the default ground potential, so as to also force the transistor into the accumulation state. Therefore, electrons can tunnel into the gate oxide layer or other gate dielectric to fill the oxide layer traps.

[0050] exist Figure 1 In the example of FIG. 1 , during the reset phase, the sampling node and thus the gate terminal of transistor 103 is typically connected to a defined reset voltage V via reset transistor 106. R Therefore, a suitable pre-bias voltage may be applied to one or more of the source terminal or the body terminal of transistor 103 (at Figure 1 In general, V PB1 denoted), relative to the defined reset voltage V RThe desired bias voltage is achieved on the MOS device, or the reset voltage itself can be controlled to a voltage suitable for applying the desired pre-bias voltage in the initial part of the reset phase, and then RST The rest of the pixel is reset to a defined reset level. For transistor 104, a control voltage may be applied to, for example, a source terminal or a bulk terminal, but additionally or alternatively, a gate voltage V may also be appropriately controlled. C , this is Figure 1 In general, V PB2 It should be noted that V PB1 and V PB2 The illustrative waveforms of the signals are purely to illustrate the principles of the relevant timing and do not imply anything about the magnitude or polarity of the applied pre-bias voltage, and it will be appreciated that the voltages applied to transistors 103 and 104 may be different from each other.

[0051] Figure 1 shows that the reset phase P RST The pre-bias voltage is applied during at least a portion of the sensing phase P. During this phase, the pixel circuit does not output an output signal, and the source follower transistors 103 and 104 are originally inactive. Therefore, applying the bias voltage during this period does not interfere with the operation of the pixel circuit. SEN and the subsequent readout phase P RO The duration of P is generally relatively short and may be shorter than the time constant associated with the trap for capturing or releasing a charge carrier. RST The filling level of the trap of the MOS device can be set during the readout phase P RO Reduce noise during the process.

[0052] for Figure 1 In an example of , a suitable pre-bias may additionally or alternatively be applied to one or more MOS devices during at least a portion of the sensing phase. In this example, there is no output signal during the sensing (or charge integration) phase, and therefore, a pre-bias may be applied to one or more MOS devices (e.g., MOS device 104).

[0053] Of course, it will be understood that for a conventional pixel circuit having the same basic structure as the pixel circuit 100 shown in FIG. 100, the voltages at the various terminals of the transistors 103 and 104 may be maintained at a defined voltage during the reset phase. However, for a conventional pixel circuit, the voltages at the various terminals of the transistors 103 and 104 may not be defined during the reset phase. RST During the period of time, the relevant voltages at the terminals at the transistors 103 and 104 are set in order to set a specific occupation of the traps of the relevant MOS devices, for example to cause all the traps to be filled. Figure 1In the case where a pre-bias is applied during a reset phase (part of the reset phase in question), then the applied pre-bias voltage is a variation of the voltage originally used for the remainder of the associated phase during which the pre-bias was applied.

[0054] In an embodiment of the present disclosure, the applied pre-bias voltage is selectively controlled based on at least one operating condition or system parameter in use. Therefore, the bias controller 107 is configured to selectively change the applied pre-bias voltage based on one or more operating conditions of the circuit. That is, in use, at least one characteristic or parameter of the applied pre-bias voltage can be dynamically adjusted according to at least one operating condition of the circuit.

[0055] Although applying a pre-bias voltage may be advantageous for noise reasons, applying a pre-bias voltage to a MOS device may be disadvantageous in other respects.

[0056] For example, applying a relatively high pre-bias voltage to a MOS device may be detrimental to the lifetime and / or reliability of the MOS device. Applying a relatively high bias voltage may cause premature aging or degradation of the semiconductor material of the MOS device.

[0057] In at least some implementations, applying a pre-bias may increase power consumption of the circuit compared to operation without applying a pre-bias, and the power consumption may be greater for higher magnitudes and / or durations of the pre-bias. For many applications, particularly for battery powered devices, power consumption and power efficiency in general may be important considerations.

[0058] In some implementations, the time taken to apply the appropriate pre-bias voltage may result in some additional delay in the operation of the associated circuits. Figure 1 It is shown that only during the reset phase P RST The pre-bias may be applied during a portion of the reset phase, but if applying a suitable pre-bias during the reset phase requires a longer duration than would otherwise be the case, this may reduce the effective maximum sampling rate. In some other circuit implementations, applying a suitable pre-bias may require introducing a dedicated pre-bias phase into the circuit operation sequence, thereby affecting latency.

[0059] Various factors can affect the trap dynamics, such as temperature. Thus, the magnitude or duration of the pre-bias required to achieve a desired fill state for the trap may vary in use. Likewise, the time constant for release may vary, and thus the internal characteristics between successive applications of pre-bias to achieve a particular noise performance may vary in use. The amount of RTS noise itself may vary with some operating conditions, and thus the amount of bias required to achieve a desired noise performance may vary. Additionally, different levels of noise performance may be acceptable depending on the operating mode of the device.

[0060] Thus, the pre-bias voltage required for one set of operating conditions may be greater than the pre-bias voltage required for a different set of operating conditions.

[0061] In an embodiment of the present disclosure, therefore, the bias controller is configured to selectively change the applied pre-bias voltage based at least on the operating conditions of the circuit. One or more parameters of the applied pre-bias voltage can be dynamically changed by the bias controller based on the relevant operating conditions so as to apply a pre-bias voltage suitable for the relevant operating conditions.

[0062] like Figure 1 As shown, therefore, the bias controller may receive a signal OC indicative of at least one operating condition of the circuit and may adjust parameters of the pre-bias accordingly.

[0063] The bias controller 107 may be responsive to one or more of a variety of different operating conditions, which may be functional or environmental, and may be operable to adjust one or more of a range of parameters of the pre-bias.

[0064] Figure 2 One example of the bias controller 107 is generally shown to illustrate only some examples of how the bias controller 107 may control one or more parameters or characteristics of the pre-bias in response to various operating conditions.

[0065] At least one operating condition may include at least one parameter, such as temperature, that affects trap dynamics (i.e., affects the capture and release of charge carriers from the trap) and therefore has an impact on at least one of: the pre-bias required to achieve a particular occupied state of the trap; the time constant for release; and / or the expected RTS noise level. Additionally or alternatively, at least one operating condition may include at least one parameter indicative of the monitored noise performance or SNR. Additionally or alternatively, at least one operating condition may include an operating mode of a host system or device that, for example, sets a desired noise or accuracy performance, power consumption level, or operating rate.

[0066] Figure 2 In the example shown, the bias controller 107 includes a processor 201 and a voltage controller 202 and optionally a memory 203. The processor 201 receives an indication of one or more operating states and determines appropriate parameters for any pre-bias to be applied, possibly by retrieving stored parameters from the memory 203 (which may be, for example, a lookup table or the like) and / or by implementing a system model or applying an algorithm that may be stored in the memory 203. In some applications, the processor may be configured to execute program code stored in the memory 203 and the bias controller may be programmed in use.

[0067] If a pre-bias voltage is to be applied, the processor 201 may control the voltage controller 202 to supply an appropriate pre-bias voltage V at an appropriate time.PB . Figure 2 A single output is shown for clarity, but as discussed above, if applying a pre-bias involves applying different voltages to different terminals of one or more MOS devices, the voltage controller 202 is operable to supply different voltages to the relevant device terminals.

[0068] In some examples, the relevant operating condition may be temperature, and thus, the bias controller 107 may receive at least one indication of temperature T as an indication of the operating condition. The received indication T may be an indication of temperature from at least one temperature sensor 204 (which may be integrated with the circuit 100 to provide an indication of the temperature of at least a portion of the circuit or chip) or an off-chip temperature sensor of a host device.

[0069] Trap dynamics vary with temperature, such as the time constants associated with the capture and release of charge carriers. Thus, the magnitude and / or duration of the pre-bias voltage applied to achieve a desired occupied state may vary with temperature. Thus, processor 201 may receive an indication of the temperature and set an appropriate magnitude and / or duration of the pre-bias voltage to be applied during an instance of pre-biasing. Thus, returning to reference Figure 1 , for the relevant temperature, the duration of the pre-bias applied and / or the magnitude of the bias voltage applied across the MOS device during instances of the reset phase may be varied appropriately, for example within a specified range.

[0070] In some cases, other aspects of how the bias voltage is applied may also have an effect. In some cases, the trap dynamics may be sensitive to the ramp rate of the voltage applied during the pre-bias operation. Therefore, the ramp rate of the applied pre-bias or the appropriate characteristics of the waveform of the bias voltage may be controllably adapted in operation.

[0071] As described above, temperature will affect the time constant associated with the capture and release of charge carriers from traps within the MOS device. Therefore, after applying an appropriate pre-bias, the duration in which the RTS noise is significantly reduced may vary with temperature. Therefore, the time between successive applications of the pre-bias may additionally or alternatively be controlled. For example, returning to reference Figure 1 , in some implementations, the time constant associated with trap release and capture can be on the order of several operating cycles of the pixel circuit under at least some operating conditions. That is, if a suitable pre-bias is applied in one reset phase, the benefit of reduced RTS noise can persist over a period that includes the next readout phase and one or more subsequent readout phases. To achieve desired noise performance, it may not be necessary to apply a pre-bias during every instance of the reset phase, but rather only in some instances of the reset phase, with the interval between consecutive applications of the pre-bias being selectively controlled by the processor 201.

[0072] Therefore, the processor 201 can control the voltage controller 202 to selectively control the pre-bias voltage V to be applied. PB The voltage controller 202 may include any suitable controller for providing relevant voltage control. For example, in some implementations, only the timing of the pre-bias voltage may be selectively controlled, i.e., the amplitude of the applied pre-bias voltage may be fixed. In this case, the voltage controller may be simply implemented by a switch to selectively connect to a defined voltage at the appropriate time. If control of the voltage amplitude and / or ramp rate is required, the voltage controller may include a suitable variable output voltage generator or regulator or a voltage DAC, etc. It will also be understood that various aspects of the voltage controller may be implemented by different components, i.e., the variable power supply may be controllable to change the amplitude of the pre-bias voltage and some other switch control used to control the timing.

[0073] To ensure that the pre-bias voltage is applied at the appropriate time in the operation of circuit 100, the processor may receive some clock or timing signal, such as a signal PHASE that indicates various stages of operation of the circuit.

[0074] Temperature is one environmental factor that affects trap dynamics, but any other operating condition that affects trap dynamics can also be considered in a similar manner and used to control the parameters of the applied pre-bias.

[0075] Additionally or alternatively, in some embodiments, processor 201 may controllably vary parameters of the applied pre-bias voltage based on an indication of the level of RTS or flicker noise or SNR (signal-to-noise ratio).

[0076] In some implementations, a signal derived from the output signal Sout from the circuit 100 may be analyzed to determine the extent of any RTS noise. Thus, the bias controller 107 may be arranged to selectively control the applied pre-bias based at least in part on feedback from the output signal. Thus, the processor 201 may receive a feedback signal FB derived from the output signal Sout as an indication of an operating condition.

[0077] In some cases, the feedback signal FB may be a version of the output signal Sout, for example, a version of Sout converted into a digital form. Figure 1In the pixel circuit shown, the analog output signal Sout from the pixel may typically be converted to a digital signal at some point downstream, and thus the digital version of Sout may be tapped and supplied to the processor 201 as the feedback signal FB. In this case, the processor 201 may be configured to process the feedback signal to determine at least one noise metric. There are various ways in which the signal may be processed to determine an indication of noise, such as providing an estimate of the amount of RTS noise or a general indication of the SNR, and the processor may employ any one or more of such analysis techniques.

[0078] In some arrangements, the feedback signal FB may be merely an indication of a noise metric determined by some other module. Figure 1 In the example of an active pixel sensor of FIG. 1 , the pixel circuit 100 shown will typically be only one of many pixels. In some cases, it may not be practical to analyze the noise in the signal from each individual pixel individually, and / or a better indication of the noise may be obtained by analyzing the output signals from multiple pixels together. In this case, the pre-bias parameters of a group of pixels may be controlled based on an indication of the noise determined from the output signals of one or more of the pixels in the group, and thus, the feedback signal FB may be the determined indication of the noise.

[0079] In some implementations, the determination of noise may additionally or alternatively be derived from a test module 205 that may be integrated with the circuit 100, i.e., formed on the same chip as the circuit. The test module may be implemented as a test MOS device that is the same or similar to those MOS devices to which the pre-bias is applied, and in some cases may include at least one virtual circuit, in this case a virtual pixel circuit similar to the actual pixel circuit 100, but in which the input of the source follower is controlled to one or more predefined reference levels. The output signal from the test module may be analyzed based on the known input to determine an indication of an RTS signal. In some examples, a constant level of input may be applied to the MOS device during the test phase, and the output may be monitored to detect any step changes in the level that indicate RTS noise.

[0080] In some cases, the various signals generated by the test module may be analyzed by the processor 201 of the pre-bias controller 107, and thus, the input N from the test module may include the various test signals generated to be used as an indication of the operating condition. However, in some cases, the analysis may be performed as part of the test module 205, and the indication N supplied to the bias controller 107 may be a determined noise level, etc. In some cases, a pre-bias may be applied to one or more MOS devices of the test module, and the one pre-bias supplied may match the pre-bias supplied to the MOS devices of the actual circuit 100, and / or different pre-biases may be applied at different times and / or to different MOS devices.

[0081] Thus, the processor 201 may receive an indication of the monitored noise or SNR as an indication of an operating condition, which may include an indication of the feedback signal FB and / or the noise N from the test module. Based on the indication of the current noise level, the processor may selectively control any one or more of the parameters of the applied pre-bias, as discussed above, such as the magnitude of the applied pre-bias, the duration of the applied pre-bias, the interval between successive applications of the pre-bias, and / or the form of the pre-bias waveform, such as the ramp rate. In this case, the parameters may be controlled to vary to maintain the noise metric at a minimum or below a defined threshold, or to maintain a specific minimum SNR.

[0082] For some implementations, it may be possible that under certain conditions, the desired noise performance may be achieved without applying any pre-bias, in which case the processor 201 may control the voltage controller so that no pre-bias is applied unless the monitored noise performance is no longer within acceptable limits, for example because the noise performance has deteriorated or higher noise performance is required. Thus, a parameter of the pre-bias that is selectively controlled by the bias controller 107 may be whether any pre-bias is applied at all. This may be viewed as a timing parameter, as the processor 201 controls the voltage generator 202 so that pre-bias is applied only at certain times when it is determined in operation that some pre-bias is required.

[0083] In some implementations, the operating condition may include an indication of an operating mode MODE, such as an operating mode of the circuit or host device. In some cases, the operating mode may determine the operating requirements, such as in terms of quality performance or power consumption, and thus the processor may control any pre-bias applied accordingly.

[0084] For example, for Figure 1 In an example of, a pre-bias may be applied to MOS devices of pixel circuits of an image sensing array, and the operating modes may include, for example, different accuracy or noise performance modes.

[0085] The first mode may correspond to a relatively high performance mode, and the second mode may correspond to a lower performance mode, such that a greater amount of RTS noise is acceptable in the second mode than in the first mode. The processor 201 may receive an indication as to whether the device is operating in the first mode or the second mode, and control the pre-bias accordingly. In some examples, the bias controller may be operable to apply a pre-bias when the device is operating in the first mode, and but not to apply a pre-bias when the device is operating in the second mode. Optionally, the controller may be operable to apply a pre-bias in the second mode, but the interval between consecutive applications of the pre-bias may be larger in the second mode than in the first mode, and / or at least one of the permissible voltage amplitude and duration of the pre-bias may be lower in the second mode than in the first mode. In some examples, different thresholds for acceptable noise levels to be monitored may be set in the first and second modes.

[0086] Additionally or alternatively, one mode may correspond to a low power mode in which no pre-bias is applied to save power, or the maximum amplitude, duration, or interval of the applied pre-bias is limited, and another mode may correspond to a higher power mode in which a pre-bias is applied that may have a greater amplitude, duration, or repetition frequency than in the low power mode.

[0087] In some examples, the indication of the operating condition or mode can be an indication of a desired operating rate for the system, such as a desired sampling rate. In some operating modes, a faster sampling rate may be required, which may limit the duration for which the pre-bias is applied and / or the frequency with which the pre-bias may be applied. Thus, the processor may be configured to set the duration and / or repetition interval of the pre-bias to allow for the desired operating speed. In some cases, the voltage amplitude or ramp rate may also vary with duration so that any pre-bias applied sets the desired trap occupancy.

[0088] Thus, in general, the bias controller 107 receives one or more indications of operating conditions, such as one or more of: an indication of an environmental condition, such as temperature T; an indication of noise or signal quality, such as a feedback signal FB indicating the noise or SNR of the output signal or an indication of noise N from a test module; or an indication of a system operating mode, such as quality, power consumption, or a desired operating rate, and selectively controls parameters or characteristics of a pre-bias voltage that may be applied to one or more MOS devices. The parameters of the applied pre-bias voltage may include one or more of: the magnitude of the pre-bias voltage, the timing (i.e., duration) of the pre-bias voltage, and / or the interval between applications (i.e., the duty cycle of the pre-bias voltage); and waveform characteristics. For some operating conditions, the bias controller may not apply any pre-bias voltage.

[0089] References to the control Figure 1 The pre-biasing of the MOS devices of the described pixel sensor circuit describes Figure 2 However, it will be understood that the pixel sensor circuit 100 may include only one pixel of a larger pixel array, and each pixel may have a bias controller 107, such as reference Figure 2 As described, one bias controller 107 may be configured to selectively control respective pre-bias voltages applied to a group of more than one pixel circuits.

[0090] The bias controller for dynamically changing the pre-bias voltage applied to a MOS device to reduce RTS noise may also be advantageously implemented in a variety of other applications.

[0091] For example, Figure 3 A circuit 300 is shown, which in this example is a current-mode DAC (digital-to-analog converter) circuit 300. The circuit comprises a current-mode DAC 301 comprising a plurality of current sources 302. 1 To 302 n , the plurality of current sources can be selectively enabled or disabled to generate a defined current. 1 To 302 n The currents can be weighted relative to each other.

[0092] The current-mode DAC 301 receives a digital input signal at a given sampling rate and selects a set of current sources 302 based on the input data samples (e.g., D1, D2, etc.). 1 To 302 n In the output stage P OP During this time, therefore, the selected current source is active to contribute to the output signal Sout, and the output switch 303 is closed.

[0093] At the end of each sampling period, if the digital sample value changes, the various current sources 302 may be activated or deactivated. 1 To 302 n After such a change, the current at the output may take some time to stabilize due to switching the various current sources on and off. This can cause current transients or spikes in the output signal and a form of distortion known as inter-symbol interference. To avoid this problem, the DAC may implement a return-to-zero method in which the output switch 303 is switched in and out of the return-to-zero phase P at the end of each sampling period when the digital code value changes and the associated current sources are activated and deactivated. RTZ This prevents any transients caused by changes in the digital code value from being output, thereby reducing distortion in the output signal Sout.

[0094] As will be appreciated, current source 302 1 To 302 nThis can be implemented using MOS devices, for example, configured as current mirrors with different weights. In embodiments of the present disclosure, a pre-bias voltage can be advantageously applied to the MOS device of the current source, wherein the pre-bias voltage can be selectively controlled in use based on one or more operating conditions of the DAC circuit. Therefore, Figure 3 The illustrated DAC circuit 300 may therefore include a bias controller 107 that receives an indication of one or more operating conditions OC and dynamically changes one or more parameters of an applied pre-bias.

[0095] Figure 4 Another example of a circuit 400 is shown that may include a bias controller 107 to dynamically control a parameter of a pre-bias voltage applied to one or more MOS devices of the circuit. Figure 4 An example of is a sampling type DAC (digital analog converter) having a first switch 401 and a second switch 402. In the sensing phase P SEN In the readout phase P, the first switch is closed and the second switch 402 is open to charge the sampling capacitor based on the input signal Sin. RO In the example, the first switch is opened and the second switch is closed to connect the sampling capacitor to the input of the comparator 404, which compares the voltage to one or more defined reference voltages V REF Make a comparison.

[0096] As will be appreciated by those skilled in the art, the comparator 404 will typically include MOS transistors, and a pre-bias may be applied to at least some of these transistors, such as the input transistor pair of the comparator and one or more load devices. In embodiments of the present disclosure, a pre-bias may be advantageously applied to the MOS devices of the current source, wherein the pre-bias may be selectively controlled in use based on one or more operating conditions of the DAC circuit. Thus, Figure 3 The illustrated DAC circuit 300 may therefore include a bias controller 107 that receives an indication of one or more operating conditions OC and dynamically changes one or more parameters of an applied pre-bias.

[0097] Figure 5 Yet another example of a circuit 500 is shown, which may include a bias controller 107 to dynamically control the parameters of a pre-bias applied to one or more MOS devices of the circuit. The circuit 500 is an analog memory cell circuit. In some examples, the circuit may form part of an analog computing system.

[0098] Circuit 500 includes a memory cell 501 that can be programmed to exhibit a desired current or conductance, such as a transconductance, in operation. The memory cell may include a non-volatile MOS transistor, such as a flash or SONOS structure.

[0099] In this example, memory cell 500 includes a select transistor 502 in series with a floating gate transistor 503. The floating gate transistor 503 has a gate terminal G connected to a control gate. However, the channel of the transistor is covered by an intermediate floating gate structure. The state and conductivity of the MOS channel depends on the charge stored on the floating gate and the voltage V applied on the control gate. CON The charge on the floating gate can be changed by applying a positive or negative voltage on the control gate relative to the source of the transistor, where these voltages are large enough to cause significant tunneling current through the gate dielectric. Figure 5 An NMOS floating gate transistor and a single series NMOS select transistor are shown, but variations including PMOS transistors or zero or more select transistors electrostatically coupled to the floating gate or other electrodes may be used.

[0100] In the memory write or programming phase, the select transistor 502 can be turned off to isolate the floating gate transistor, and a suitably high amplitude voltage can be applied as the voltage V of the control gate. CON , in order to program the floating gate transistor. The effective threshold voltage of the device can be programmed, and therefore, in the subsequent read phase, when the control gate voltage V CON When set to a lower nominal voltage, a desired current, conductance, or transconductance can be obtained.

[0101] Once programmed, in the read phase, the select transistor can be turned on to connect the drain of the floating gate transistor to the reference voltage VR, and the gate control voltage V CON Can be set to a lower amplitude.

[0102] In some cases, the control gate voltage V CON can be set to a constant predefined value, in which case the output current I OUT The output current I OUT It may be buffered by buffer 504 to provide an output signal.

[0103] However, in some implementations, the gate controls V CON The output current I can be controllably changed according to some input data. For example, during the read phase, the control electrode voltage can be modulated as a PWM waveform to change between two defined signal levels at a duty cycle that depends on the input data. OUTThe total output current also depends on the duty cycle of the control voltage, and during the entire read phase, the total output current also depends on the duty cycle of the control voltage. Therefore, the output current integrated during the read cycle has a value that depends on the product of the stored transconductance value and the input data value. Therefore, the memory cell can be used as part of an analog computing system to perform multiplication between some input data and a stored value (e.g., a weight value).

[0104] In some implementations, a cross-point array may be formed in which a plurality of memory cells are arranged in rows and columns. In some examples, a group of memory cells (e.g., a column of memory cells) may be arranged to store a vector of weight values. During the same read phase, different input data values ​​that together form a data input vector may be applied to corresponding memory cells in different rows of a column. The output currents from all memory cells during the read phase may be combined and integrated by the buffer 504 to provide an output that is effectively the dot product of the weight vector and the input data vector. The same data vector may be applied to different columns of memory cells to determine the dot product of the same date vector and different vectors of weight values.

[0105] Thus, the memory cell circuit may form part of a dot product engine such as may be used in neuromorphic computing, for example as part of a neural network.

[0106] During the read phase, RTS noise may affect the transconductance of the floating gate transistor and thus corrupt the weight value. In embodiments of the present disclosure, a pre-bias voltage may be advantageously applied to the floating gate MOS device of the current source, wherein the pre-bias voltage may be selectively controlled in use based on one or more operating conditions of the memory cell circuit. Thus, Figure 5 The illustrated memory cell circuit 300 may therefore include a bias controller 107 that receives an indication of one or more operating conditions OC and dynamically changes one or more parameters of an applied pre-bias.

[0107] Thus, operation of the memory cell may also include a pre-bias phase, where an appropriate pre-bias is applied prior to an instance of the read phase.

[0108] exist Figure 3 , Figure 4 or Figure 5 The bias controller 107 shown in any of the examples of FIG. 1 can generally be used with reference to FIG. Figure 2The bias controller 107 may operate in the same manner as discussed above, and may receive an indication of an operating condition that affects trap dynamics, such as temperature, an indication of noise from a feedback signal or a test module, or some indication of an operating mode that sets a desired accuracy / signal quality or noise performance, power consumption, or sampling or processing rate. The bias controller 107 may control one or more parameters of the applied pre-bias, such as amplitude, duration, repetition frequency, ramp rate or other waveform characteristics and / or whether any pre-bias is applied at all for some operating conditions.

[0109] Thus, a dynamic bias controller according to various embodiments can apply an appropriate pre-bias to the MOS devices of a circuit in response to operating conditions so as to reduce RTS or flicker noise to a desired level without applying a bias greater than required, which may be detrimental to the life of the circuit and / or wasteful or increase power unnecessarily delays.

[0110] Circuits according to embodiments of the present invention may be implemented as integrated circuits. Integrated circuits may be manufactured using a manufacturing process with a relatively small process node geometry. Embodiments may advantageously be implemented as part of an analog or mixed signal circuit.

[0111] Embodiments may be incorporated into a host electronic device, which may be, for example, a portable device and / or a device operable with battery power. The host device may be a communication device (such as a mobile phone or smartphone or the like), a computing device (such as a notebook, laptop or tablet computing device), a wearable device (such as a smart watch). The host device may optionally be an accessory device for use with any such communication, computing or wearable device.

[0112] The skilled person will recognize that some aspects of the above-described apparatus and methods may be embodied as processor control code, for example, on a non-volatile carrier medium such as a disk, CD-ROM or DVD-ROM, a programmed memory such as a read-only memory (firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications, the embodiments will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit), or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode, or, for example, code for setting up or controlling an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device such as a reprogrammable logic gate array. Similarly, the code may include code for a hardware description language such as Verilog TMThe code may be distributed among multiple coupled components that communicate with each other. Where appropriate, embodiments may also be implemented using code running on a field (re)programmable analog array or similar device to configure analog hardware.

[0113] It should be noted that the above-mentioned embodiments are illustrative rather than restrictive of the present invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may perform the functions of several units recited in the claims. Any reference numerals or labels in the claims should not be construed as limiting the scope of the claims.

Claims

1. A circuit comprising a first MOS device and a bias controller, wherein: The circuit is configured to be operable in a first circuit state in which the first MOS device is active to facilitate a first signal and in a second circuit state in which the first MOS device does not facilitate the first signal; the bias controller being configured to be operable to control a voltage at one or more terminals of the first MOS device to apply a pre-bias to the first MOS device during an instance of the second circuit state, wherein the pre-bias is applied to set an occupancy state of charge carrier traps within the first MOS device to limit noise from the first MOS device during subsequent operation in the first circuit state; and The bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

2. The circuit of claim 1, wherein the one or more operating conditions include operating conditions that affect kinetics of charge carrier capture by the charge carrier trap within the first MOS device.

3. A circuit as claimed in claim 1 or claim 2, wherein one of the one or more operating conditions comprises temperature, and the bias controller is configured to receive an indication of the temperature from a temperature sensor.

4. A circuit as claimed in claim 1 or claim 2, wherein one of the one or more operating conditions comprises an indication of monitored noise.

5. The circuit of claim 4, wherein the indication of the monitored noise is determined from a feedback signal derived from the first signal.

6. The circuit of claim 4, wherein the indication of the monitored noise is determined from one or more test signals obtained from a test module including at least one test MOS device.

7. The circuit of claim 1 or claim 2, wherein one of the one or more operating conditions comprises an operating mode for a system including the circuit.

8. The circuit of claim 7, wherein the system is capable of operating in a plurality of different modes, and wherein the different modes have different requirements on at least one of: noise performance or signal quality; power consumption; and operating rate.

9. The circuit of claim 1 or claim 2, wherein the bias controller is configured to control the amplitude of the bias voltage applied to the first MOS device as a parameter of the pre-bias.

10. The circuit of claim 1 or claim 2, wherein the bias controller is configured to control a duration of a bias voltage applied to the first MOS device as a parameter of the pre-bias.

11. The circuit of claim 1 or claim 2, wherein the bias voltage controller is configured to control a duration between successive applications of the pre-bias voltage to the first MOS device as a parameter of the pre-bias voltage.

12. The circuit of claim 1 or claim 2, wherein the bias controller is configured to control a shape of a waveform of a bias voltage applied to the first MOS device as a parameter of the pre-bias.

13. A circuit as claimed in claim 1 or claim 2, wherein the first signal is an analog signal.

14. A circuit as claimed in claim 1 or claim 2, wherein the circuit is configured to operate in a sequence of states, the sequence of states including at least one instance of the second circuit state, whether or not a pre-bias is applied during an instance of the second circuit state.

15. The circuit of claim 1 or claim 2, wherein the bias controller is configured to be operable to control a voltage at one or more terminals of at least one additional MOS device to apply a pre-bias to the at least one additional MOS device.

16. A circuit as claimed in claim 1 or claim 2, wherein the bias voltage controller comprises a processor configured to receive an indication of at least one operating condition and to determine the at least one parameter of the pre-bias voltage to be applied.

17. The circuit of claim 16, wherein the bias controller comprises a voltage controller for controlling at least one voltage applied to a terminal of the first MOS device based on the determined at least one parameter.

18. The circuit of claim 1 or claim 2, wherein the circuit is one of: a sensor circuit; a digital-to-analog converter circuit, an analog-to-digital converter circuit; and an analog memory cell circuit.

19. A circuit comprising a first MOS device and a bias controller, wherein: the bias controller being configured to be operable to control a voltage at one or more terminals of the first MOS device to apply a pre-bias voltage to the first MOS device, wherein the pre-bias voltage is applied to set an occupation state of charge carrier traps within the first MOS device to limit noise from the first MOS device during subsequent operation; and The bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

20. A bias controller for controlling a bias voltage applied to a first MOS device of a circuit, the bias controller being operable to apply a pre-bias to the first MOS device so as to set a defined occupancy state of a charge carrier trap within the first MOS device, wherein the bias controller dynamically adjusts the applied pre-bias in response to one or more operating conditions.

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