Method and system for controlling a multi-core DSP radar reconnaissance jamming system

Abstract

The application provides a control method and system of a multi-core DSP radar reconnaissance jamming system, and the method comprises the following steps: a multi-core DSP is pre-configured, and different cores process data communication, jamming noise calculation, radar signal data caching, and sorting result calculation during radar jamming and radar reconnaissance; during radar jamming, a first core calculates jamming parameters according to obtained control instructions, then a second core calculates jamming noise according to the type of the jamming parameters, finally the first core issues the jamming parameters and / or the jamming noise to configure corresponding jammers and start the jammers; during radar reconnaissance, the first core determines target frequencies according to obtained frequency sweeping commands to obtain radar signal data at the target frequencies, then a third core caches the radar signal data, a fourth core performs sorting calculation on the cached radar signal data to obtain sorting results, and finally the first core reports the sorting results; and the application realizes serial / parallel reconnaissance and jamming, and improves the real-time performance and stability of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radar signal processing, in particular to a control method and system of a multi-core DSP radar reconnaissance jamming system. BACKGROUND

[0002] The real-time requirement of radar signal processing is very high, and the radar reconnaissance jamming system needs to complete radar reconnaissance and jamming simultaneously or in time-sharing, that is, both reconnaissance and jamming are realized, and reconnaissance is realized before jamming. Since the reconnaissance algorithm and the interference noise generation algorithm need to consume a large amount of time for calculation, when the reconnaissance algorithm and the interference noise generation algorithm need to be used for calculation at the same time, the real-time calculation requirement of the processor is very high. The processor in the prior art cannot meet the real-time requirement of the system, resulting in that most of the existing devices cannot perform radar reconnaissance and jamming in parallel, and the system performance is low.

[0003] The multi-core processing chip TMS320C6678 of TI can be used for multi-core task design and distribution, and how to apply the multi-core DSP chip to the radar reconnaissance jamming system to improve the overall performance of the radar reconnaissance jamming system is a problem worth exploring. SUMMARY

[0004] The technical problem to be solved by the present application is that, in view of the technical problems existing in the prior art, the present application provides a control method and system of a multi-core DSP radar reconnaissance jamming system, which divides tasks for different cores of the multi-core DSP, and improves the real-time performance and stability of the radar reconnaissance jamming system.

[0005] To solve the above technical problems, the technical solution provided by the present application is as follows:

[0006] A control method of a multi-core DSP radar reconnaissance jamming system, comprising the following steps:

[0007] The multi-core DSP is pre-configured, and different cores are used to process data communication, interference noise calculation, radar signal data caching, and sorting result calculation during radar jamming and radar reconnaissance;

[0008] When radar jamming is performed, a first core is used to obtain a control instruction, interference parameters are calculated according to the control instruction, then a second core is used to calculate interference noise according to the type of the interference parameters, and finally the first core is used to issue the interference parameters and / or the interference noise to configure a corresponding jammer and start the jammer;

[0009] When radar reconnaissance is performed, the first core is used to obtain a frequency sweeping command, a target frequency is determined according to the frequency sweeping command to obtain radar signal data at the target frequency, then a third core is used to cache the radar signal data, a fourth core is used to perform sorting calculation on the cached radar signal data to obtain a sorting result, and finally the first core is used to report the sorting result.

[0010] Further, the step of performing radar jamming specifically comprises:

[0011] SA1) the core 0 obtains a control instruction, if the control instruction is a start instruction, the transceiving channel of the radar reconnaissance jamming system is opened, and the corresponding jamming parameters are calculated according to the jamming type in the start instruction;

[0012] SA2) if the jamming noise does not need to be configured, the core 0 issues the jamming parameters to configure the corresponding jammer and start the jammer; otherwise, the core 0 sends the corresponding inter-core interrupt to the core 1 according to the jamming type in the start instruction, the core 1 calculates the jamming noise according to the inter-core interrupt, and the core 0 issues the corresponding jamming noise after obtaining the corresponding jamming noise from the core 1 to configure the corresponding jammer and start the jammer.

[0013] Further, the step SA1) further includes a processing step when the control instruction is a stop instruction, specifically including: if the control instruction is a stop instruction, the core 0 closes the sending channel of the radar reconnaissance jamming system and controls the jammer to stop working.

[0014] Further, the step SA1) further includes a processing step when the control instruction is a no-jamming instruction, specifically including: if the control instruction is a no-jamming instruction, the core 0 opens the transceiving channel of the radar reconnaissance jamming system and controls the jammer to work without jamming.

[0015] Further, the step SA2) in which the core 1 calculates the jamming noise according to the inter-core interrupt specifically includes:

[0016] SA21) the core 1 receives the inter-core interrupt, judges the jamming type according to the interrupt source ID, if it is a suppression jamming, step SA22) is executed, if it is a deception jamming, step SA23) is executed;

[0017] SA22) the core 1 sends a suppression jamming calculation semaphore, then calculates the suppression jamming noise and saves the calculation result, and finally sends an inter-core interrupt to the core 0;

[0018] SA23) the core 1 sends a deception jamming calculation semaphore, then calculates the deception jamming noise and saves the calculation result, and finally sends an inter-core interrupt to the core 0.

[0019] Further, the step SA2) further includes: the core 0 generates corresponding scene parameters according to the working parameters of the jammer and the jamming parameters, and saves the scene parameters in the corresponding scene library of the Flash through the EMIF interface; the step SA2) further includes:

[0020] SB1) the core 0 obtains a scene scheduling instruction, and calculates the starting address of the scene parameters in the Flash according to the scene serial number in the scene scheduling instruction;

[0021] SB2) core 0 reads corresponding scene parameter data from the start address in the Flash, and if the scene parameter is correct, the jammer is started according to the scene parameter and timing is performed;

[0022] SB3) if the timing time is greater than the working time set in the working parameter, core 0 controls the jammer to stop working.

[0023] Further, the step of radar reconnaissance specifically comprises:

[0024] SC1) core 0 acquires a sweep command, if the target frequency in the sweep command is a fixed value, step SC2) is performed, if the target frequency in the sweep command is an interval, step SC3) is performed;

[0025] SC2) core 0 opens the transceiver channel of the radar reconnaissance jamming system, issues a reconnaissance command to acquire radar signal data at the target frequency, core 3 caches the radar signal data, core 2 sorts and calculates the cached radar signal data, obtains sorting results and saves them, and core 0 reports the sorting results;

[0026] SC3) core 0 sets a starting target frequency and a step according to the target frequency interval, determines the next target frequency from the starting target frequency in turn with the step, then opens the transceiver channel of the radar reconnaissance jamming system, and issues a reconnaissance command to acquire radar signal data at each target frequency, core 3 caches the radar signal data, core 2 sorts and calculates the cached radar signal data, obtains sorting results and saves them, and core 0 reports the sorting results.

[0027] Further, core 3 caches the radar signal data in steps SC2) and SC3) specifically comprises: core 3 receives radar signal data, and saves the radar signal data in the corresponding position in the cache space according to the ID number of the radar signal data.

[0028] Further, core 2 sorts and calculates the cached radar signal data in steps SC2) and SC3) specifically comprises:

[0029] Core 2 receives an external SRIO interrupt notification, obtains a corresponding data address and data length according to the SRIO interrupt, takes out the corresponding data from the data address according to the data length, and then stores it in the cache space;

[0030] Core 2 calls the sorting algorithm interface of the radar reconnaissance jamming system, and performs radar pulse signal detection, measurement and sorting on the corresponding data in the cache space in turn, completes envelope detection, parameter measurement, signal sorting and radar source identification, and obtains sorting results;

[0031] After core 2 stores the sorting algorithm results in the shared memory, it sends an inter-core interrupt to core 0.

[0032] The application further provides a multi-core DSP radar reconnaissance jamming system, comprising:

[0033] The core 0 of the DSP chip is used for realizing bottom interface driver initialization, communication with the outside and result reporting, and radio frequency module logic control, the core 1 of the DSP chip is used for realizing interference noise calculation and calculation result saving, the core 2 of the DSP chip is used for acquiring radar signal data, jointly processing multiple parameters through sorting algorithm, identifying the number and characteristics of the radiation source and saving the sorting result, and the core 3 of the DSP chip is used for receiving and saving external data.

[0034] The system further comprises an FPGA chip, a DDR, a Flash, a PHY chip, a gigabit network interface, an SRIO interface and a radio frequency module, the DSP chip is connected with the radio frequency module through the SRIO interface and the FPGA chip in sequence, and is connected with an external host computer through the PHY chip and the gigabit network interface in sequence, and the DSP chip is further connected with the DDR and the Flash respectively.

[0035] Compared with the prior art, the application has the advantages that:

[0036] 1. In the method of the application, the functions of different cores of the multi-core DSP are pre-configured, so that the different cores of the multi-core DSP respectively process data communication, interference noise calculation, radar signal data caching and sorting result calculation when radar reconnaissance and radar jamming are performed, so that the radar reconnaissance and radar jamming are simultaneously or separately performed, the system performance is improved, and the real-time performance and stability requirements of the radar reconnaissance and jamming system are met.

[0037] 2. The system of the application has high integration, the different processing cores of the DSP chip respectively process external communication and result reporting, interference noise calculation and calculation result saving, radar signal data acquisition and sorting result saving through sorting algorithm, and external data receiving and saving when radar jamming and radar reconnaissance are performed, so that the whole machine has high integration and strong real-time performance, can perform parallel calculation of radar reconnaissance and radar jamming, and overcomes the problems of single function and poor real-time performance of the prior art. DETAILED DESCRIPTION

[0038] Figure 1 Fig. 1 is a structural framework schematic diagram of the multi-core DSP radar reconnaissance jamming system of the embodiment of the application.

[0039] Figure 2 Fig. 4 is a flow chart of the control method of the embodiment of the application.

[0040] Figure 3 Fig. 5 is an interference parameter calculation flow chart of the embodiment of the application.

[0041] Figure 4The interference noise calculation flow chart for core 1 of the embodiment of the present application.

[0042] Figure 5 The different scene mode calling flow chart for the embodiment of the present application.

[0043] Figure 6 The radar reconnaissance flow chart for the embodiment of the present application.

[0044] Figure 7 The FPGA sends the SRIO interrupt algorithm data flow chart for the embodiment of the present application. DETAILED DESCRIPTION

[0045] The present application is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present application is not limited thereby.

[0046] As shown in Figure 1 the present embodiment, a multi-core DSP radar reconnaissance jamming system is designed, which comprises a DSP chip, an FPGA chip, a DDR, a Flash, a PHY chip, a gigabit network interface, an SRIO interface and a radio frequency module. The DSP chip is connected with the radio frequency module through the SRIO interface and the FPGA chip in sequence, and is connected with an external host computer through the PHY chip and the gigabit network interface in sequence. The DSP chip is also connected with the DDR and the Flash respectively. The system adopts a multi-core DSP architecture. The DSP chip calculates interference noise data according to interference parameters set by the host computer and sends the data to the FPGA to generate corresponding noise jamming signals, so as to realize various types of jamming on corresponding radars. The FPGA is used to process radar signals and control the radio frequency module, so as to complete full-band scanning of radar signals and sorting of radar signals based on PDW.

[0047] In the present embodiment, the DSP chip adopts a TMS320C6678 multi-core processing chip developed by TI. Four cores in the TMS320C6678 processor are configured to process data communication, interference noise calculation, radar signal data caching and sorting result calculation during radar jamming and radar reconnaissance. Specifically, core 0 of the TMS320C6678 multi-core processing chip is used to realize initialization of a bottom interface driver, communication with the outside and result reporting, and logic control of the radio frequency module. Core 1 of the TMS320C6678 multi-core processing chip is used to realize interference noise calculation and calculation result saving. Core 2 of the TMS320C6678 multi-core processing chip is used to acquire radar signal data, jointly process multiple parameters through a sorting algorithm, identify the number and characteristics of radiation sources and save the sorting results. Core 3 of the TMS320C6678 multi-core processing chip is used to receive and save external data.

[0048] Through the above structure, the multi-core DSP radar reconnaissance jamming system of the embodiment has high integration, strong real-time performance, can perform parallel calculation of radar reconnaissance and radar jamming, and overcomes the problems of single function and poor real-time performance of existing devices.

[0049] As shown in Figure 2 , the main work of core 0 in the embodiment is to realize communication with the outside, data analysis, result reporting, and logic control, and the specific function division is as follows:

[0050] a. Realize Ethernet communication with the host computer;

[0051] b. Realize calculation and delivery of suppression jamming parameters;

[0052] c. Realize calculation and delivery of deception jamming parameters;

[0053] d. Realize delivery of deception and suppression jamming noise calculation results;

[0054] e. Realize radar signal sweep frequency control and reconnaissance analysis result reporting;

[0055] f. Realize logic control of different scene mode manual and automatic calling.

[0056] As shown in Figure 2 , the main work of core 1 in the embodiment is to realize interference noise calculation and result saving, and the specific function division is as follows:

[0057] a. Since core 1 only performs algorithm calculation, in order to improve calculation speed, L1 program and data cache are started;

[0058] b. Receive the deception and suppression jamming inter-core interrupt sent by core 0;

[0059] c. According to the inter-core interrupt, respectively perform deception and suppression jamming noise calculation;

[0060] d. Send the inter-core interrupt to core 0 to complete noise calculation.

[0061] As shown in Figure 2 , the main work of core 2 in the embodiment is to realize sorting algorithm calculation and result saving, and the specific function division is as follows:

[0062] a. Receive the SRIO interrupt and PDW data sent by the FPGA, and perform preliminary calculation;

[0063] b. Send the processed data into the sorting algorithm interface for calculation;

[0064] c. After storing the sorting algorithm results in the shared memory, send the inter-core interrupt to core 0 to complete the sorting algorithm calculation.

[0065] The sorting algorithm realizes radar pulse signal detection, measurement and sorting, completes envelope detection, parameter measurement, signal sorting and radar source identification functions of the signal, and uploads the pulse signal parameter measurement results.

[0066] As shown in Figure 2 The main work of the core 3 in the embodiment is to realize the serial port data receiving interrupt and serial port data saving, and the specific function division is as follows:

[0067] a. Receive the serial port SRIO interrupt and serial port data sent by the FPGA;

[0068] b. According to the ID number and data in the serial port data of the radio frequency module, store them in different buffers respectively.

[0069] As shown in Figure 3 The steps of the multi-core DSP radar reconnaissance jamming system of the embodiment for radar jamming specifically include:

[0070] SA1) Core 0 acquires a control instruction, if the control instruction is a start instruction, starts the frequency synthesis and transceiver component to open the transceiver channel of the radar reconnaissance jamming system, calculates the corresponding jamming parameters according to the jamming type in the start instruction, including the suppression jamming type and / or the deception jamming type, that is, the suppression jamming parameters corresponding to the suppression jamming of this type and the deception jamming parameters corresponding to the deception jamming of this type; The frequency synthesis and transceiver component includes a wideband frequency synthesis component and a wideband transceiver component, wherein the wideband frequency synthesis component mainly realizes the control and self-checking mode of the local oscillator frequency; The wideband transceiver component mainly realizes the control of the transceiver switch, the transceiver channel attenuation and the filter.

[0071] SA2) If no jamming noise needs to be configured, the core 0 sends the jamming parameters to the FPGA, the FPGA configures the corresponding jammer, and starts the jammer; otherwise, the core 0 sends the corresponding inter-core interrupt to the core 1 according to the jamming type in the start instruction, the core 1 calculates the jamming noise according to the inter-core interrupt, and the core 0 sends the corresponding jamming noise to the FPGA after obtaining the corresponding jamming noise from the core 1, and the FPGA configures the corresponding jammer and starts the jammer.

[0072] As shown in Figure 3 The step SA1) of the embodiment further includes the processing step of the control instruction being a stop instruction, specifically including: if the control instruction is a stop instruction, the core 0 closes the frequency synthesis and transceiver component to close the transmission channel of the radar reconnaissance jamming system, and sends a stop working mode to the FPGA, so that the FPGA controls the jammer to stop working.

[0073] As shown in Figure 3As shown, the step SA1) of the embodiment further includes a processing step of controlling the instruction to be a non-interference instruction, specifically including: if the control instruction is a non-interference instruction, the core 0 starts the frequency synthesis and the transceiver component to open the transceiver channel of the radar reconnaissance jamming system, and sends the non-interference working mode to the FPGA, so that the FPGA controls the jammer to work in the non-interference mode.

[0074] As shown in the step SA2) of the embodiment, the core 1 calculates the jamming noise according to the inter-core interrupt, specifically including: Figure 4

[0075] SA21) The core 1 receives the inter-core interrupt, judges the jamming type according to the interrupt source ID, executes the step SA22) if it is suppression jamming, and executes the step SA23) if it is deception jamming;

[0076] SA22) The core 1 sends the suppression jamming calculation semaphore, then calculates the suppression jamming noise and saves the calculation result, and finally sends the inter-core interrupt to the core 0;

[0077] SA23) The core 1 sends the deception jamming calculation semaphore, then calculates the deception jamming noise and saves the calculation result, and finally sends the inter-core interrupt to the core 0.

[0078] In order to reduce the calculation amount in subsequent radar jamming, the step SA2) of the embodiment further includes: the core 0 generates corresponding scene parameters according to the working parameters and the jamming parameters of the jammer, the number of bytes of the working parameters, the suppression jamming parameters and the deception jamming parameters in the scene parameters is less than 1000 bytes, the scene parameters are saved in the Flash corresponding to the scene library through the EMIF interface, each scene library is saved in different blocks of the Flash, so as to facilitate independent erasing and writing of each library.

[0079] In subsequent radar jamming, the existing logic can be automatically or manually called through the Ethernet and the serial port to perform radar jamming, as shown in the step SA2). Figure 5

[0080] SB1) The core 0 obtains the scene scheduling instruction issued through the Ethernet or the serial port, and calculates the starting address of the scene parameters in the Flash according to the scene serial number in the scene scheduling instruction;

[0081] SB2) The core 0 reads the corresponding scene parameter data from the starting address in the Flash, and if the scene parameter is correct, the core 0 starts the jammer to work according to the scene parameter and times;

[0082] SB3) If the timing time is greater than the working time set in the working parameter, the core 0 controls the jammer to stop working.

[0083] As shown in the step SA2) of the embodiment, the core 1 calculates the jamming noise according to the inter-core interrupt, specifically including:​​Figure 6 As shown, the steps of radar reconnaissance performed by the multi-core DSP radar reconnaissance jamming system of the embodiment specifically include:

[0084] SC1) core 0 acquires the sweep command issued by the upper computer, if the target frequency in the sweep command is a constant value, step SC2) is performed, if the target frequency in the sweep command is an interval, step SC3) is performed;

[0085] SC2) core 0 starts the frequency synthesizer and the transceiver component to open the transceiver channel of the radar reconnaissance jamming system, sends a reconnaissance command to the FPGA, the FPGA controls the radio frequency module to acquire radar signal data at the target frequency, core 3 caches the radar signal data, core 2 performs sorting calculation on the cached radar signal data, obtains sorting results and saves them, and core 0 reports the sorting results;

[0086] SC3) core 0 sets the starting target frequency and the step size according to the target frequency interval, determines the next target frequency from the starting target frequency in the step size, then starts the frequency synthesizer and the transceiver component to open the transceiver channel of the radar reconnaissance jamming system, and sends a reconnaissance command to the FPGA, the FPGA controls the radio frequency module to acquire radar signal data at each target frequency, core 3 caches the radar signal data, core 2 performs sorting calculation on the cached radar signal data, obtains sorting results and saves them, and core 0 reports the sorting results.

[0087] In steps SC2) and SC3) of the embodiment, after the FPGA controls the radio frequency module to acquire radar signal data at each target frequency, the radar signal data is sent to the DSP chip through SRIO, and an SRIO interrupt is sent to the DSP chip to notify that the data has arrived. Thereafter, core 3 receives the SRIO interrupt and the radar signal data, and saves the radar signal data in the corresponding position in the cache space according to the ID number of the radar signal data. Then core 2 performs sorting calculation on the cached radar signal data, such as Figure 7 As shown, specifically includes:

[0088] Core 2 receives the external SRIO interrupt notification, acquires the corresponding data address and data length according to the SRIO interrupt, takes out the corresponding data from the data address according to the data length, and then stores it in the cache space;

[0089] Core 2 calls the sorting algorithm interface of the radar reconnaissance jamming system to perform radar pulse signal detection, measurement and sorting on the corresponding data in the cache space in sequence, complete the envelope detection, parameter measurement, signal sorting and radar source identification of the signal, and obtain the sorting results;

[0090] After core 2 stores the sorting algorithm results in the shared memory, it sends an inter-core interrupt to core 0.

[0091] As shown in Figure 6As shown, in the embodiment, when the target frequency is in the interval, 2G-6G sweep frequency and 6G-18G sweep frequency are included, in the 2G-6G sweep frequency mode, the starting target frequency is set to 2.5G, the step length is 0.5G, and the sweep frequency is completed by single increment to 6G; in the 6G-18G sweep frequency mode, the starting target frequency is set to 6.25G, the step length is 0.5G, and the sweep frequency is completed by single increment to 18G. After the sweep frequency is completed, in step SC3), the core 0 reports the sorting result after being screened by a certain condition to obtain the sorting result to be reported.

[0092] According to the above content, the embodiment proposes a control method of a multi-core DSP radar reconnaissance jamming system, including:

[0093] The TMS320C6678 multi-core processing chip is pre-configured, and data communication, interference noise calculation, radar signal data buffering, and sorting result calculation are processed by different cores when radar interference and radar reconnaissance are performed;

[0094] When radar interference is performed, the core 0 obtains a control instruction, calculates interference parameters according to the control instruction, then the core 1 calculates interference noise according to the type of the interference parameters, and finally the core 0 issues the interference parameters and / or interference noise to configure a corresponding jammer and start the jammer;

[0095] When radar reconnaissance is performed, the core 0 obtains a sweep frequency command, determines a target frequency according to the sweep frequency command to obtain radar signal data at the target frequency, then the core 3 buffers the radar signal data, the core 2 sorts and calculates the buffered radar signal data to obtain a sorting result, and finally the core 0 reports the sorting result.

[0096] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application, without departing from the technical solution of the present application, shall fall within the scope of protection of the technical solution of the present application.

Claims

1. A control method of a multi-core DSP radar reconnaissance jamming system, characterized in that, The method comprises the following steps: The multi-core DSP is pre-configured, and different cores process data communication, interference noise calculation, radar signal data caching, and sorting result calculation during radar interference and radar reconnaissance; When radar interference is performed, the core 0 acquires a control instruction, calculates interference parameters according to the control instruction, then the core 1 calculates interference noise according to the type of the interference parameters, and finally the core 0 sends the interference parameters and / or the interference noise to the FPGA to control the FPGA to configure a corresponding jammer and start the jammer to perform radar interference. SA1) The core 0 acquires a control instruction, and if the control instruction is a start instruction, the transceiving channel of the radar reconnaissance jamming system is turned on, and interference parameters corresponding to the interference type in the start instruction are calculated. SA2) If no interference noise needs to be configured, the core 0 sends the interference parameters to the FPGA to configure a corresponding jammer and start the jammer; otherwise, the core 0 sends an inter-core interrupt corresponding to the interference type in the start instruction to the core 1, the core 1 calculates interference noise according to the inter-core interrupt, and the core 0 sends the interference noise obtained from the core 1 to the FPGA to configure a corresponding jammer and start the jammer. When radar reconnaissance is performed, the core 0 acquires a sweep command, determines a target frequency according to the sweep command to control the FPGA to acquire radar signal data at the target frequency, then the core 3 caches the radar signal data, the core 2 performs sorting calculation on the cached radar signal data to obtain sorting results, and finally the core 0 reports the sorting results to perform radar reconnaissance. SC1) The core 0 acquires a sweep command, and if the target frequency in the sweep command is a constant value, step SC2) is performed, or if the target frequency in the sweep command is an interval, step SC3) is performed. SC2) The core 0 turns on the transceiving channel of the radar reconnaissance jamming system, sends a reconnaissance command to the FPGA to acquire radar signal data at the target frequency, the core 3 caches the radar signal data, the core 2 performs sorting calculation on the cached radar signal data to obtain sorting results and save the sorting results, and the core 0 reports the sorting results. SC3) The core 0 sets a starting target frequency and a step size according to the interval of the target frequency, determines a next target frequency from the starting target frequency by the step size, turns on the transceiving channel of the radar reconnaissance jamming system, sends a reconnaissance command to the FPGA to acquire radar signal data at each target frequency, the core 3 caches the radar signal data, the core 2 performs sorting calculation on the cached radar signal data to obtain sorting results and save the sorting results, and the core 0 reports the sorting results.

2. The control method of the multi-core DSP radar reconnaissance jamming system according to claim 1, characterized in that, In step SA1), the processing step of the control instruction being a stop instruction is further included, specifically comprising: if the control instruction is a stop instruction, the core 0 closes the sending channel of the radar reconnaissance jamming system and controls the jammer to stop working.

3. The control method of the multi-core DSP radar reconnaissance jamming system according to claim 1, characterized in that, In step SA1), the processing step of the control instruction being a no-interference instruction is further included, specifically comprising: if the control instruction is a no-interference instruction, the core 0 turns on the transceiving channel of the radar reconnaissance jamming system and controls the jammer to work without interference.

4. The control method of the multi-core DSP radar reconnaissance jamming system according to claim 1, characterized in that, In step SA2), the core 1 calculates interference noise according to the inter-core interrupt specifically comprises: SA21) core 1 receives an inter-core interrupt, judges the interference type according to the interrupt source ID, if it is suppression interference, step SA22) is executed, if it is deception interference, step SA23) is executed; SA22) core 1 sends a suppression interference calculation semaphore, then calculates the suppression interference noise and saves the calculation result, and finally sends an inter-core interrupt to core 0; SA23) core 1 sends a deception interference calculation semaphore, then calculates the deception interference noise and saves the calculation result, and finally sends an inter-core interrupt to core 0.

5. The control method of the multi-core DSP radar reconnaissance jamming system according to claim 1, characterized in that, In step SA2), core 0 generates corresponding scene parameters according to the working parameters and interference parameters of the jammer, and saves the scene parameters in the corresponding scene library of the Flash through the EMIF interface; after step SA2), the following steps are further included: SB1) core 0 acquires a scene scheduling instruction, and calculates the starting address of the scene parameters in the Flash according to the scene serial number in the scene scheduling instruction; SB2) core 0 reads the corresponding scene parameter data from the starting address in the Flash, and if the scene parameters are correct, starts the jammer according to the scene parameters and times; SB3) if the timing time is greater than the working time set in the working parameters, core 0 controls the jammer to stop working.

6. The control method of the multi-core DSP radar reconnaissance jamming system according to claim 1, characterized in that, In steps SC2) and SC3), the buffering of the radar signal data by core 3 specifically includes: core 3 receives the radar signal data, and saves the radar signal data in the corresponding position in the cache space according to the ID number of the radar signal data.

7. The control method of the multi-core DSP radar reconnaissance jamming system according to claim 1, characterized in that, In steps SC2) and SC3), the sorting calculation of the buffered radar signal data by core 2 specifically includes: Core 2 receives an external SRIO interrupt notification, obtains the corresponding data address and data length according to the SRIO interrupt, takes out the corresponding data from the data address according to the data length, and then stores the data in the cache space; Core 2 calls the sorting algorithm interface of the radar reconnaissance jamming system, and sequentially performs radar pulse signal detection, measurement and sorting on the corresponding data in the cache space, completes envelope detection, parameter measurement, signal sorting and radar source identification, and obtains the sorting result; After core 2 stores the sorting algorithm result in the shared memory, it sends an inter-core interrupt to core 0.

8. A multi-core DSP radar reconnaissance jamming system, characterized by, It includes: The core 0 of the DSP chip is used to realize the initialization of the bottom interface driver, communicate with the outside world, report the results, and control the logic of the radio frequency module; the core 1 of the DSP chip is used to realize interference noise calculation and calculation result saving; the core 2 of the DSP chip is used to acquire radar signal data, process multiple parameters through a sorting algorithm, identify the number and characteristics of the radiation sources, and save the sorting result; and the core 3 of the DSP chip is used to receive and save external data; It further includes an FPGA chip, a DDR, a Flash, a PHY chip, a gigabit network interface, an SRIO interface, and a radio frequency module; the DSP is connected with the radio frequency module through the SRIO interface and the FPGA in sequence, and is connected with the external host computer through the PHY chip and the gigabit network interface in sequence; and the DSP is further connected with the DDR and the Flash. When radar jamming is performed, the core 0 obtains a control instruction, calculates jamming parameters according to the control instruction, then the core 1 calculates jamming noise according to the type of the jamming parameters, and finally the core 0 issues the jamming parameters and / or the jamming noise to the FPGA to control the FPGA to configure the corresponding jammer and start the jammer to perform radar jamming. The steps specifically include: SA1) The core 0 obtains a control instruction, if the control instruction is a start instruction, the transceiving channel of the radar reconnaissance jamming system is turned on, and the corresponding jamming parameters are calculated according to the jamming type in the start instruction; SA2) If no jamming noise needs to be configured, the core 0 issues the jamming parameters to the FPGA to configure the corresponding jammer and start the jammer; otherwise, the core 0 sends the corresponding inter-core interrupt to the core 1 according to the jamming type in the start instruction, the core 1 calculates the jamming noise according to the inter-core interrupt, and the core 0 issues the corresponding jamming noise to the FPGA to configure the corresponding jammer and start the jammer after obtaining the jamming noise from the core 1; When radar reconnaissance is performed, the core 0 obtains a sweep command, determines the target frequency according to the sweep command to control the FPGA to obtain radar signal data at the target frequency, then the core 3 caches the radar signal data, the core 2 calculates the sorting result by sorting the cached radar signal data, and finally the core 0 reports the sorting result to perform radar reconnaissance. The steps specifically include: SC1) The core 0 obtains a sweep command, if the target frequency in the sweep command is a constant value, step SC2) is performed, if the target frequency in the sweep command is an interval, step SC3) is performed; SC2) The core 0 turns on the transceiving channel of the radar reconnaissance jamming system, sends a reconnaissance command to the FPGA to obtain radar signal data at the target frequency, the core 3 caches the radar signal data, the core 2 calculates the sorting result by sorting the cached radar signal data, and the core 0 reports the sorting result; SC3) The core 0 sets the starting target frequency and the step according to the interval of the target frequency, then starts the transceiving channel of the radar reconnaissance jamming system, sends a reconnaissance command to the FPGA to obtain radar signal data at each target frequency, the core 3 caches the radar signal data, the core 2 calculates the sorting result by sorting the cached radar signal data, and the core 0 reports the sorting result.

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