A semiconductor chip packaging structure and packaging method

Abstract

The present invention relates to the field of semiconductor packaging technology, and discloses a packaging structure and packaging method for a semiconductor chip. The packaging structure of the semiconductor chip includes a wafer, an insulating structure and a conductive member. A functional area and an electrode are provided on the first surface of the wafer, the electrodes are spaced along the circumference of the functional area, and the electrodes are arranged at an angle away from the side wall of the functional area; the insulating structure covers the first surface and opens a receiving space toward one side of the wafer, the functional area is placed between the receiving space and the first surface, the side wall of the insulating structure is arranged at an angle and is coplanar with the side wall of the electrode away from the functional area, forming a cutting bevel inclined toward the middle of the insulating structure; the conductive member covers the cutting bevel and is electrically connected to the electrode, and the conductive member extends along the outer contour of the insulating structure to the end face of the insulating structure opposite to the wafer. The present invention makes the conductive member a planar structure at the side wall of the chip, reduces the number of inflection points on the conductive member, and ensures the structural strength and durability of the conductive member.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging structure and a packaging method for a semiconductor chip. Background Art

[0002] With the rapid development of the personal consumer electronics industry, smart devices such as laptops are increasingly moving towards portable and functional directions. Therefore, improving the reliability of the chip packaging structure inside the smart device is also an important development direction. In the prior art, the chip packaging structure includes a wafer and an insulating structure covering the wafer. In one type of chip packaging structure, a metal wire layer is covered on the side wall of the insulating structure to conduct the electrical signal of the electrode on the wafer to the upper surface of the insulating structure, which is convenient for connection with the external conductive structure. The electrode is usually arranged at the edge of the wafer. In order to expose the electrode, the insulating structure only covers the middle part of the wafer, so that part of the electrode is exposed and electrically connected to the metal wire layer. However, the insulating structure usually includes two insulating layers, and the coverage area of ​​the two insulating layers decreases from bottom to top, that is, a step surface is generated at the side wall of the insulating structure, so that the metal wire layer covering the side wall of the insulating structure has an inflection point, and the resistance at the inflection point is large, which increases the heat generation on the metal wire layer. Excessive heat reduces the reliability of damaging the chip packaging structure, and also increases the location where stress concentration occurs on the metal wire layer, increases the possibility of fracture of the metal wire layer, and affects the structural strength and durability of the metal wire layer.

[0003] Based on this, there is an urgent need for a semiconductor chip packaging structure and packaging method to solve the above-mentioned problems. Summary of the invention

[0004] The object of the present invention is to provide a packaging structure and packaging method for a semiconductor chip, so that the conductive part is a planar structure at the side wall of the chip, reducing the number of inflection points on the conductive part, reducing the heat generated on the conductive part due to the existence of the inflection points, and also reducing the locations where stress concentration occurs on the conductive part, thereby ensuring the structural strength and durability of the conductive part.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] A semiconductor chip packaging structure, comprising:

[0007] A wafer, wherein a functional area and a plurality of electrodes are provided on a first surface of the wafer, the plurality of electrodes are arranged at intervals along the circumference of the functional area, and the electrodes are arranged obliquely away from the sidewalls of the functional area;

[0008] an insulating structure, covering the first surface and having a receiving space on a side facing the wafer, wherein a cavity is formed between the receiving space and the first surface, wherein the functional area is disposed in the cavity, wherein the sidewall of the insulating structure is inclined, and the sidewall of the insulating structure is coplanar with the sidewall of the electrode away from the functional area and forms a cutting bevel, wherein the cutting bevel is inclined toward the middle of the insulating structure in a direction away from the wafer;

[0009] A conductive member covers the cutting bevel and is electrically connected to the electrode, wherein one end of the conductive member away from the wafer extends along the outer contour of the insulating structure to the end surface of the insulating structure opposite to the wafer.

[0010] As an optional technical solution for a packaging structure of a semiconductor chip, the insulation structure includes a first insulation layer and a second insulation layer, the accommodating space passes through the first insulation layer, and the second insulation layer covers the side of the first insulation layer facing away from the first surface and forms the cavity between the first insulation layer and the first surface.

[0011] As an optional technical solution for a semiconductor chip packaging structure, the semiconductor chip packaging structure also includes an insulating protective layer, which covers the conductive member. A conductive opening is provided on the insulating protective layer, and the conductive member can be exposed through the conductive opening.

[0012] As an optional technical solution for a semiconductor chip packaging structure, the semiconductor chip packaging structure also includes a bump, the bump is located in the conductive opening, the bump protrudes from the insulating protection layer, and the bump is electrically connected to the conductive member.

[0013] As an optional technical solution for the packaging structure of a semiconductor chip, a plurality of electrodes are provided, a plurality of conductive members are provided, the plurality of electrodes are connected to the plurality of conductive members in a one-to-one correspondence, the plurality of conductive members are arranged at intervals, and the insulating structure between two adjacent conductive members is covered with the insulating protective layer.

[0014] As an optional technical solution for the packaging structure of a semiconductor chip, a groove is opened on the first surface, the first end of the groove passes through the side wall of the wafer, the second end of the groove away from the first end extends to the cutting bevel, and the groove wall at the second end is coplanar with the cutting bevel.

[0015] A semiconductor chip packaging method is used to manufacture the semiconductor chip packaging structure as described above, the method comprising:

[0016] S1. Providing a wafer, wherein a functional area and an electrode are provided on a first surface of the wafer;

[0017] S2, making an insulating base layer with a receiving space on the first surface;

[0018] S3, cutting the insulating base layer and the electrode along the cutting area of ​​the wafer to form an insulating structure and a cutting bevel that exposes the electrode;

[0019] S4, making conductive parts;

[0020] S5, cutting the wafer along the cutting area to form a single chip.

[0021] As an optional technical solution for a semiconductor chip packaging method, in step S3, when cutting the insulating base layer and the electrode, the wafer is cut to form a groove on the first surface of the wafer, the first end of the groove passes through the side wall of the wafer, the second end of the groove away from the first end extends to the cutting bevel, and the groove wall at the second end is coplanar with the cutting bevel.

[0022] As an optional technical solution of a semiconductor chip packaging method, after step S4, the method further includes:

[0023] S41, covering the conductive member and the insulating structure with an insulating protective layer;

[0024] S42, opening a conductive opening on the insulating protective layer;

[0025] S43, setting a bump in the conductive opening, wherein the bump is electrically connected to the conductive member.

[0026] As an optional technical solution of a semiconductor chip packaging method, the insulation structure includes a first insulation layer and a second insulation layer;

[0027] Step S2 specifically includes providing the first insulating layer on the first surface, photolithographically forming the accommodation space on the first insulating layer, and covering the first insulating layer with the second insulating layer so that the cavity is enclosed by the first insulating layer, the second insulating layer and the first surface.

[0028] Beneficial effects of the present invention:

[0029] The semiconductor chip packaging structure provided by the present invention comprises a wafer, an insulating structure and a conductive member. The side wall of the insulating structure is coplanar with the side wall of the electrode away from the functional area and forms a cutting bevel, and the conductive member covers the cutting bevel and is electrically connected to the electrode, so that the conductive member at the side wall of the chip covers on a plane, that is, the conductive member is a planar structure at the side wall of the chip, which reduces the number of inflection points on the conductive member, reduces the heat accumulation generated on the conductive member due to the existence of the inflection points, reduces the influence of temperature on the reliability of the chip packaging structure, and the conductive member has fewer inflection points, which also reduces the location of stress concentration on the conductive member, reduces the possibility of the conductive member breaking, ensures the structural strength and durability of the conductive member, and thus ensures that the conductive member can stably conduct the electrical signal of the electrode to the surface of the insulating structure opposite to the wafer, ensures the functionality and service life of the chip, and improves the practicality.

[0030] The semiconductor chip packaging method provided by the present invention is used to manufacture the packaging structure of the semiconductor chip described above. The edges of the insulating base layer and the electrode are cut to form an insulating structure and a cutting bevel that exposes the electrode, so that the conductive member can cover the cutting bevel and be electrically connected to the electrode, which is conducive to the conductive member forming a planar structure at the side wall of the chip, reducing the number of inflection points on the conductive member, reducing the heat accumulation generated on the conductive member due to the existence of the inflection points, and reducing the influence of temperature on the reliability of the chip packaging structure. In addition, the conductive member has fewer inflection points, which also reduces the location of stress concentration on the conductive member, reduces the possibility of the conductive member breaking, and ensures the structural strength and durability of the conductive member, thereby ensuring that the conductive member can stably conduct the electrical signal of the electrode to the surface of the insulating structure opposite to the wafer, ensuring the functionality and service life of the chip, and improving the practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a semiconductor chip packaging structure provided by an embodiment of the present invention;

[0032] Figure 2 It is a flow chart of the main steps of the semiconductor chip packaging method provided by an embodiment of the present invention;

[0033] Figure 3 It is a structural schematic diagram of the semiconductor chip packaging method provided by an embodiment of the present invention after a first insulating layer is provided on a wafer;

[0034] Figure 4 It is a structural schematic diagram of the semiconductor chip packaging method provided by an embodiment of the present invention after a second insulating layer is provided on a wafer;

[0035] Figure 5It is a schematic diagram of the structure after the insulating structure, the electrode and the wafer are cut to form grooves in the semiconductor chip packaging method provided by an embodiment of the present invention;

[0036] Figure 6 It is a structural schematic diagram of a semiconductor chip packaging method provided by an embodiment of the present invention after a conductive member is formed on an insulating structure;

[0037] Figure 7 It is a schematic structural diagram of the semiconductor chip packaging method provided by an embodiment of the present invention after an insulating protection layer is formed on the insulating structure and the conductive member;

[0038] Figure 8 It is a schematic structural diagram of the semiconductor chip packaging method after the bumps are set in the embodiment of the present invention;

[0039] Fig. 9 It is a structural schematic diagram of cutting a wafer in the semiconductor chip packaging method provided by an embodiment of the present invention.

[0040] In the figure:

[0041] 10. Chip; 10a. First chip; 10b. Second chip; 20. Cutting knife;

[0042] 1. Wafer; 11. Functional area; 12. Electrode; 13. Groove; 14. Cutting area; 2. Cavity;

[0043] 3. Insulation structure; 31. First insulation layer; 311. First opening; 32. Second insulation layer;

[0044] 4. Insulation protective layer;

[0045] 5. Conductive member; 51. Inclined conductive portion; 52. Plane conductive portion; 53. Extended conductive portion;

[0046] 6. Bump; 7. Cutting bevel. DETAILED DESCRIPTION

[0047] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0048] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0050] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0051] This embodiment provides a semiconductor chip packaging structure. Specifically, Figure 1 As shown, the packaging structure of the semiconductor chip includes a wafer 1, an insulating structure 3 and a conductive member 5. A functional area 11 and a plurality of electrodes 12 are arranged on the first surface of the wafer 1, and the plurality of electrodes 12 are arranged at intervals from the functional area 11, and the plurality of electrodes 12 are arranged at intervals along the circumference of the functional area 11, and the electrodes 12 are arranged obliquely away from the side wall of the functional area 11; the insulating structure 3 covers the first surface and opens a receiving space on one side facing the wafer 1, and a cavity 2 is formed between the receiving space and the first surface, and the functional area 11 is placed in the cavity 2, and the side wall of the insulating structure 3 is arranged obliquely, and the side wall of the insulating structure 3 is coplanar with the side wall of the electrode 12 away from the functional area 11 and forms a cutting bevel 7, and the cutting bevel 7 is inclined toward the middle of the insulating structure 3 in the direction away from the wafer 1; the conductive member 5 covers the cutting bevel 7 and is electrically connected to the electrode 12, and one end of the conductive member 5 away from the wafer 1 extends along the outer contour of the insulating structure 3 to the end surface of the insulating structure 3 opposite to the wafer 1.

[0052] The semiconductor chip packaging structure provided in this embodiment includes a wafer 1, an insulating structure 3 and a conductive member 5. The side wall of the insulating structure 3 is coplanar with the side wall of the electrode 12 away from the functional area 11 and forms a cutting bevel 7. The conductive member 5 covers the cutting bevel 7 and is electrically connected to the electrode 12, so that the conductive member 5 at the side wall of the chip 10 covers the plane, that is, the conductive member 5 at the side wall of the chip 10 is a planar structure, which reduces the number of inflection points on the conductive member 5, reduces the heat accumulation generated on the conductive member 5 due to the existence of the inflection points, and reduces the influence of temperature on the reliability of the chip packaging structure. In addition, the conductive member 5 has fewer inflection points, which also reduces the location of stress concentration on the conductive member 5, reduces the possibility of the conductive member 5 breaking, and ensures the structural strength and durability of the conductive member 5, thereby ensuring that the conductive member 5 can stably conduct the electrical signal of the electrode 12 to the surface of the insulating structure 3 opposite to the wafer 1, ensuring the functionality and service life of the chip 10, and improving the practicality.

[0053] In this embodiment, the functional area 11 may be an interdigital transducer, the electrode 12 is a pad disposed on the surface of the wafer 1, and the electrode 12 may be an aluminum pad, an aluminum-nickel-gold pad, an aluminum-nickel-palladium-gold pad, etc. In other embodiments, the chip type is not limited, and the type of the functional area 11 is adaptively adjusted according to the chip type, and is not limited here.

[0054] As a preferred solution, the insulating structure 3 includes a first insulating layer 31 and a second insulating layer 32, the accommodation space penetrates the first insulating layer 31, and the second insulating layer 32 covers the side of the first insulating layer 31 away from the first surface and forms a cavity 2 between the first insulating layer 31 and the first surface. It can be understood that the side walls of the first insulating layer 31 and the second insulating layer 32 are both inclined, and the side walls of the first insulating layer 31 and the second insulating layer 32 are coplanar, forming the inclined side walls of the insulating structure 3 together. The insulating structure 3 is set as a two-layer structure, the first insulating layer 31 is first set on the wafer 1, the accommodation space is formed on the first insulating layer 31 by photolithography, and finally the second insulating layer 32 is set on the first insulating layer 31 to form the insulating structure 3, which is conducive to simplifying the molding process of the accommodation space and facilitating production and processing.

[0055] In this embodiment, the first insulating layer 31 and the second insulating layer 32 are both made of photosensitive organic insulating materials. Specifically, the first insulating layer 31 is formed by spin coating a photosensitive organic insulating coating or by laminating a photosensitive organic insulating plate material, and the second insulating layer 32 is formed by laminating a photosensitive organic insulating plate material. Further, the thickness of the first insulating layer 31 is not less than 1 μm, and the thickness of the second insulating layer 32 is not less than 1 μm.

[0056] Preferably, the conductive part 5 includes a planar conductive portion 52 and a bevel conductive portion 51, the planar conductive portion 52 covers the end surface of the insulating structure 3 opposite to the wafer 1, the bevel conductive portion 51 covers the cutting bevel 7 and is electrically connected to the electrode 12, and the planar conductive portion 52 and the bevel conductive portion 51 extend toward each other and are electrically connected.

[0057] Specifically, the conductive member 5 is preferably made of metal and can be formed by magnetron sputtering (Physical Vapor Deposition, PVD), electroplating, photolithography or etching. In this embodiment, the thickness of the conductive member 5 is not less than 0.1 μm.

[0058] Preferably, a groove 13 is provided on the first surface, the first end of the groove 13 passes through the side wall of the wafer 1, the second end of the groove 13 away from the first end extends to the cutting bevel 7, and the groove wall of the second end is coplanar with the cutting bevel 7. The groove 13 is provided on the first surface, and the insulating structure 3 and the electrode 12 can be cut through by one cutting, and the cutting bevel 7 and the groove 13 are formed, thereby ensuring that the electrode 12 can form an inclined side wall, and the inclined side wall on the electrode 12 can be connected to the conductive member 5, ensuring the connection area and connection stability between the conductive member 5 and the electrode 12, thereby ensuring that the conductive member 5 can stably conduct the electricity of the electrode 12 to the top of the insulating structure 3, and ensuring the functionality of the chip 10. In this embodiment, the depth of the groove 13 is not less than 0.1 μm, that is, the height between the first surface of the wafer 1 and the bottom surface of the groove 13 is not less than 0.1 μm, ensuring that the electrode 12 can be cut through, and the specific groove depth can be adaptively adjusted, which is not limited here.

[0059] Furthermore, the conductive member 5 further includes an extended conductive portion 53, and one end of the inclined conductive portion 51 away from the planar conductive portion 52 extends along the cutting inclined surface 7 and the groove wall of the groove 13 to the groove bottom surface of the groove 13, ensuring that the conductive member 5 can be completely connected to the side wall of the electrode 12. Furthermore, the inclined conductive portion 51 extends with an extended conductive portion 53 along the groove bottom surface of the groove 13. Since the conductive member 5 is formed by magnetron sputtering, the extended conductive portion 53 is provided, and the conductive member 5 can also be connected to the wafer 1, so that the packaging structure of the chip 10 is more stable.

[0060] As a preferred solution, the packaging structure of the semiconductor chip also includes an insulating protective layer 4. The insulating protective layer 4 covers the conductive member 5, and a conductive opening is provided on the insulating protective layer 4, through which the conductive member 5 can be exposed. The insulating protective layer 4 is provided to protect the conductive member 5, thereby ensuring the durability of the chip 10, and the conductive member 5 can only be exposed through the conductive opening, thereby determining the connection position between the conductive member 5 and the external cable, thereby avoiding the connection between the external cable and other positions of the conductive member 5. In this embodiment, a conductive opening is provided at the position of the insulating protective layer 4 corresponding to the planar conductive portion 52.

[0061] Furthermore, there are multiple electrodes 12, so there are multiple conductive parts 5 connected to the electrodes 12, and the multiple electrodes 12 are connected to the multiple conductive parts 5 one by one, and the multiple conductive parts 5 are arranged at intervals to achieve insulation between the multiple electrodes 12. The insulating structure 3 between two adjacent conductive parts 5 is also covered with an insulating protective layer 4, so that the insulating protective layer 4 can protect the insulating structure 3 and the conductive part 5 as a whole, further ensuring the protective effect of the insulating protective layer 4, and the insulating protective layer 4 can achieve overall coverage of the insulating structure 3 and the conductive part 5 by one spin coating, which is beneficial to improving the packaging efficiency of the chip 10.

[0062] In this embodiment, the insulating protective layer 4 can be made of a photosensitive organic insulating material, and is specifically formed by spin coating a photosensitive organic insulating coating. In other embodiments, the insulating protective layer 4 can be formed by other methods or other materials, which are not limited here.

[0063] Furthermore, the packaging structure of the semiconductor chip also includes a bump 6, which is located in the conductive opening, the bump 6 protrudes from the insulating protective layer 4, and the bump 6 is electrically connected to the conductive member 5. The bump 6 is provided to further facilitate connection with an external cable, thereby improving practicality. The end of the bump 6 opposite to the conductive member 5 protrudes from the insulating protective layer 4, further facilitating connection with an external cable. The height of the bump 6 is greater than 5 μm, and the specific value can be selected according to the adaptability of the demand, and is not limited here.

[0064] This embodiment also provides a semiconductor chip packaging method for manufacturing the semiconductor chip packaging structure described above. Figure 2 As shown, the method includes:

[0065] S1, providing a wafer 1, wherein a functional area 11 and an electrode 12 are provided on a first surface of the wafer 1;

[0066] S2, making an insulating base layer with a receiving space on the first surface;

[0067] S3, cutting the insulating base layer and the electrode 12 along the cutting area 14 of the wafer 1 to form an insulating structure 3 and a cutting bevel 7 exposing the electrode 12;

[0068] S4, making a conductive member 5;

[0069] S5 , cutting the wafer 1 along the cutting area 14 to form a single chip 10 .

[0070] The semiconductor chip packaging method provided in this embodiment is used to manufacture the packaging structure of the semiconductor chip described above. The edges of the insulating base layer and the electrode 12 are cut to form the insulating structure 3 and the cutting bevel 7 exposing the electrode 12, so that the conductive member 5 can cover the cutting bevel 7 and be electrically connected to the electrode 12, which is conducive to the conductive member 5 forming a planar structure at the side wall of the chip 10, reducing the number of inflection points on the conductive member 5, reducing the heat accumulation generated on the conductive member 5 due to the existence of the inflection points, and reducing the influence of temperature on the reliability of the chip packaging structure. In addition, the conductive member 5 has fewer inflection points, which also reduces the location where stress concentration occurs on the conductive member 5, reduces the possibility of the conductive member 5 breaking, and ensures the structural strength and durability of the conductive member 5, thereby ensuring that the conductive member 5 can stably conduct the electrical signal of the electrode 12 to the surface of the insulating structure 3 opposite to the wafer 1, ensuring the functionality and service life of the chip 10, and improving the practicality.

[0071] like Figure 3-Figure 9 FIG. 1 is a step-by-step process diagram of a semiconductor chip packaging method provided in this embodiment, referring to FIG. Figure 3-Figure 9 , which describes in detail the packaging method of semiconductor chips.

[0072] S1 . Provide a wafer 1 , on the first surface of which a functional area 11 and an electrode 12 are provided.

[0073] Specifically, a plurality of functional areas 11 and a plurality of electrodes 12 are arranged on the wafer 1. A cutting area 14 is also provided on the first surface of the wafer 1, and the cutting area 14 divides the wafer 1 into a plurality of single chips 10, each of which is provided with a functional area 11 and six electrodes 12, and the six electrodes 12 are arranged around the functional area 11 at intervals along the circumferential direction. Figure 3-Figure 8 In the embodiment, a cutting area 14 is provided on the wafer 1, and the wafer 1 is divided into two chips 10, namely a first chip 10a and a second chip 10b. Figure 3-Figure 8 The numbers of the cutting areas 14, the functional areas 11 and the electrodes 12 are only examples and can be adaptively adjusted in other embodiments and are not limited here.

[0074] S2. Make an insulating base layer with a receiving space on the first surface.

[0075] Further, as described above, the insulating structure 3 includes a first insulating layer 31 and a second insulating layer 32, and the insulating structure 3 is formed by cutting the insulating base layer. Therefore, step S2 specifically includes providing the first insulating layer 31 on the first surface, photolithography to form a receiving space on the first insulating layer 31, and covering the second insulating layer 32 on the first insulating layer 31, so that the first insulating layer 31, the second insulating layer 32 and the first surface enclose a cavity 2. The insulating structure 3 is set as a double-layer structure, so as to facilitate photolithography or etching to form a receiving space on the first insulating layer 31.

[0076] Specifically, a first insulating layer 31 is formed on the wafer 1 by spin coating or lamination, and a position on the first insulating layer 31 corresponding to the functional area 11 is photolithographically processed to expose the functional area 11. A first opening 311 is formed at a position on the first insulating layer 31 corresponding to the functional area 11, and the first opening 311 is formed as an accommodating space, and a side wall of the first opening 311 is spaced from the functional area 11. Figure 3 It is a schematic structural diagram after the first insulating layer 31 is provided on the wafer 1 .

[0077] Furthermore, the second insulating layer 32 is formed on the first insulating layer 31 by lamination. At least two second insulating layers 32 are provided, and the second insulating layers 32 are arranged in an array on the first insulating layer 31. The second insulating layers 32 are arranged one by one corresponding to the divided chips 10, and the two adjacent second insulating layers 32 are arranged at intervals. When the insulating structure 3 is subsequently cut to form the cutting bevel 7, the cutting is performed at the interval between the two adjacent second insulating layers 32, and less material is removed, which is convenient for cutting. Moreover, when the second insulating layer 32 is made of different materials from the first insulating layer 31, the second insulating layer 32 may warp after being heated. Compared with covering the first insulating layer 31 with the second insulating layer 32, the above-mentioned structural setting makes the length and width of the second insulating layer 32 smaller, reduces the deflection, reduces the possibility of warping of the chip 10, facilitates the processing of subsequent products, and ensures the qualified rate of the products. Figure 4 It is a schematic structural diagram after the second insulating layer 32 is disposed on the first insulating layer 31 .

[0078] Specifically, Figure 5In the embodiment, a second insulating layer 32 is respectively arranged above the first chip 10a and the second chip 10b, and the two second insulating layers 32 are arranged at intervals. When the insulating base layer is cut to form the cutting bevel 7, for the first chip 10a, the insulating base layer and the electrode 12 are cut along the circumference of the first chip 10a. Similarly, for the second chip 10b, the insulating base layer and the electrode 12 are cut along the circumference of the second chip 10b, so that an inverted trapezoidal groove is formed at the connection between the first chip 10a and the second chip 10b, that is, the cutting bevel 7 at the two adjacent edges of the first chip 10a and the second chip 10b and the groove wall and groove bottom of the groove 13 jointly form the above-mentioned inverted trapezoidal groove, and the cutting bevel 7 and the groove 13 at the other edges of the first chip 10a and the other edges of the second chip 10b are notched. The cross section of the insulating structure 3 on each chip 10 is trapezoidal, and the trapezoidal Little Endian The wafer 1 is arranged opposite to the wafer 1 .

[0079] In other embodiments, the second insulating layer 32 may also be provided as an integral structure, covering the first insulating layer 31 , that is, completely covering the first insulating layer 31 , which is not limited here.

[0080] S3 , cutting the insulating base layer and the electrode 12 along the cutting area 14 of the wafer 1 to form an insulating structure 3 and a cutting bevel 7 exposing the electrode 12 .

[0081] In this embodiment, in step S3, an insulating base layer is first formed on the wafer 1, and then the insulating base layer and the electrode 12 are cut to form a cutting bevel 7 that exposes the electrode 12. Before the cutting operation is performed, the electrode 12 can be protected by the insulating base layer, which reduces the exposure time of the electrode 12. In addition, since the electrode 12 is located at the edge of the wafer 1, cutting the electrode 12 can reduce the width of the electrode 12, so that more of the wafer 1 can be exposed after cutting the electrode 12, which is convenient for subsequent cutting of the wafer 1. Moreover, when cutting the wafer 1, it is also beneficial to remove the excess part of the edge of the wafer 1, which is beneficial to reducing the size of the chip 10, thereby facilitating the miniaturization of the volume of the chip 10 and improving practicality. Figure 5 It is a schematic diagram of the structure of the insulating structure 3, the electrode 12 and the wafer 1 after being cut.

[0082] Specifically, in step S3, when cutting the insulating base layer and the electrode 12, the wafer 1 is cut to form a groove 13 on the first surface of the wafer 1, the first end of the groove 13 passes through the side wall of the wafer 1, the second end of the groove 13 away from the first end extends to the cutting bevel 7, and the groove wall at the second end is coplanar with the cutting bevel 7. When cutting the insulating base layer and the electrode 12, the cutting depth is increased so that the wafer 1 is also cut, ensuring that the insulating structure 3 and the electrode 12 can be cut through by one cut, and the cutting bevel 7 is formed, thereby ensuring that the electrode 12 can form an inclined side wall, and the inclined side walls on the electrode 12 can be connected to the conductive member 5, ensuring the connection area and connection stability between the conductive member 5 and the electrode 12, thereby ensuring that the conductive member 5 can stably conduct the electricity of the electrode 12 to the top of the insulating structure 3, and ensuring the functionality of the chip 10.

[0083] In the prior art, photolithography or etching is usually used to remove the materials on the insulating base layer and the electrode 12 to form a groove structure. During the photolithography or etching process, chemical agents need to be coated on the insulating base layer and the electrode 12, which can easily damage the electrode 12. In this embodiment, laser cutting or a metal blade is used to cut the insulating base layer and the electrode 12, thereby preventing the electrode 12 from being corroded by the chemical agent, protecting the electrode 12, and ensuring the qualified rate of the product.

[0084] S4. Making a conductive member 5.

[0085] Specifically, in step S4, a metal base layer is first formed on the second insulating layer 32 by processes such as PVD sputtering physical vapor deposition, and then a conductive member 5 is formed by photolithography or etching the metal base layer to cover the cutting bevel 7, the groove 13 and the second insulating layer 32 so as to conduct the electrical signal of the electrode 12 to the insulating structure 3. Figure 6 It is a schematic diagram of the structure after the conductive member 5 is provided.

[0086] Specifically, the conductive members 5 at the two opposite edges of the two adjacent chips 10 are arranged opposite to each other and spaced apart. That is, in the inverted trapezoidal groove between the first chip 10a and the second chip 10b, the conductive members 5 are arranged in pairs, each pair of conductive members 5 is arranged opposite to each other, and the extended conductive portions 53 on each pair of conductive members 5 are spaced apart. When the conductive members 5 are subsequently cut to form a single chip 10, the cutting of the conductive members 5 is avoided, the damage to the conductive members 5 caused by the cutting is reduced, and the types of materials that need to be cut are reduced, the demand for cutting equipment is reduced, and the packaging cost is reduced.

[0087] As a preferred solution, after step S4, the following steps are further included:

[0088] S41 , covering the conductive member 5 and the insulating structure 3 with an insulating protective layer 4 .

[0089] Specifically, the insulating protection layer 4 can be made of a photosensitive organic insulating material and formed on the insulating structure 3 and the conductive member 5 by using a process such as spin coating or spray coating. Figure 7 It is a schematic diagram of the structure after the insulating protective layer 4 is provided. Further, the insulating protective layer 4 fills the above-mentioned inverted trapezoidal grooves and gaps.

[0090] S42 , opening a conductive opening on the insulating protection layer 4 .

[0091] Specifically, a photolithography process or the like can be used to form a conductive opening at a position of the insulating protective layer 4 directly opposite to the planar conductive portion 52 on the conductive member 5, so as to facilitate determining the exposed position of the conductive member 5.

[0092] S43 , a bump 6 is arranged in the conductive opening, and the bump 6 is electrically connected to the conductive member 5 .

[0093] Specifically, the bumps 6 are provided to facilitate connection with external cables and improve practicality. Subsequently, the bumps 6 can be provided on the conductive member 5 by printing, ball planting, electroplating, sintering and other processes, which are not limited here. Figure 8 The diagram is a schematic diagram of the structure after the bump 6 is provided.

[0094] S5 , cutting the wafer 1 along the cutting area 14 of the wafer 1 to form a single chip 10 .

[0095] Specifically, mechanical cutting or laser cutting technology may be used to cut the wafer 1 according to the cutting area 14 , so as to form the first chip 10 a and the second chip 10 b into a single chip 10 . Fig. 9 It is a schematic structural diagram of using a cutting knife 20 to cut the wafer 1 .

[0096] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A semiconductor chip packaging structure, characterized in that: include: A wafer (1), wherein a first surface of the wafer (1) is provided with a functional area (11) and a plurality of electrodes (12), the plurality of electrodes (12) are arranged at intervals along the circumference of the functional area (11), and the electrodes (12) are arranged obliquely away from the side wall of the functional area (11); An insulating structure (3), covering the first surface and having a receiving space on a side facing the wafer (1), a cavity (2) being formed between the receiving space and the first surface, the functional area (11) being placed in the cavity (2), the side wall of the insulating structure (3) being arranged obliquely, and the side wall of the insulating structure (3) and the side wall of the electrode (12) away from the functional area (11) being coplanar and forming a cutting bevel (7), the cutting bevel (7) being inclined toward the middle of the insulating structure (3) in a direction away from the wafer (1); a conductive member (5) covering the cutting bevel (7) and electrically connected to the electrode (12), wherein one end of the conductive member (5) away from the wafer (1) extends along the outer contour of the insulating structure (3) to an end surface of the insulating structure (3) opposite to the wafer (1); A groove (13) is provided on the first surface, and the insulating structure (3) and the electrode (12) are cut through in one cut to form the cutting bevel (7) and the groove (13); The insulating structure (3) comprises a first insulating layer (31) and a second insulating layer (32); the accommodating space passes through the first insulating layer (31); the second insulating layer (32) covers a side of the first insulating layer (31) facing away from the first surface and forms the cavity (2) between the first insulating layer (31) and the first surface.

2. The semiconductor chip packaging structure according to claim 1, characterized in that: The semiconductor chip packaging structure further comprises an insulating protective layer (4), wherein the insulating protective layer (4) covers the conductive member (5), and a conductive opening is provided on the insulating protective layer (4), and the conductive member (5) can be exposed through the conductive opening.

3. The semiconductor chip packaging structure according to claim 2, characterized in that: The semiconductor chip packaging structure further comprises a bump (6), wherein the bump (6) is located in the conductive opening, the bump (6) is arranged to protrude from the insulating protection layer (4), and the bump (6) is electrically connected to the conductive member (5).

4. The semiconductor chip packaging structure according to claim 2, characterized in that: A plurality of electrodes (12) are provided, a plurality of conductive members (5) are provided, the plurality of electrodes (12) are connected to the plurality of conductive members (5) in a one-to-one correspondence, the plurality of conductive members (5) are arranged at intervals, and the insulating structure (3) between two adjacent conductive members (5) is covered with the insulating protective layer (4).

5. The semiconductor chip packaging structure according to claim 1, characterized in that: The first end of the groove (13) passes through the side wall of the wafer (1), the second end of the groove (13) away from the first end extends to the cutting bevel (7), and the groove wall of the second end is coplanar with the cutting bevel (7).

6. A method for packaging a semiconductor chip, characterized in that: A method for manufacturing a semiconductor chip packaging structure as claimed in any one of claims 1 to 5, comprising: S1. Providing a wafer (1), wherein a functional area (11) and an electrode (12) are provided on a first surface of the wafer (1); S2, making an insulating base layer with a receiving space on the first surface; S3, cutting the insulating base layer and the electrode (12) along the cutting area (14) of the wafer (1) to form an insulating structure (3) and a cutting bevel (7) exposing the electrode (12); S4, making a conductive member (5); S5, cutting the wafer (1) along the cutting area (14) to form a single chip (10).

7. The semiconductor chip packaging method according to claim 6, characterized in that: In step S3, when cutting the insulating base layer and the electrode (12), the wafer (1) is cut to form a groove (13) on the first surface of the wafer (1), wherein the first end of the groove (13) passes through the side wall of the wafer (1), and the second end of the groove (13) away from the first end extends to the cutting bevel (7), and the groove wall of the second end is coplanar with the cutting bevel (7).

8. The semiconductor chip packaging method according to claim 6, characterized in that: After step S4, the method further includes: S41, covering the conductive member (5) and the insulating structure (3) with an insulating protective layer (4); S42, opening a conductive opening on the insulating protective layer (4); S43, a bump (6) is provided in the conductive opening, wherein the bump (6) is electrically connected to the conductive member (5).

9. The semiconductor chip packaging method according to claim 6, characterized in that: The insulating structure (3) comprises a first insulating layer (31) and a second insulating layer (32); Step S2 specifically comprises providing the first insulating layer (31) on the first surface, photolithographically forming the accommodation space on the first insulating layer (31), and covering the second insulating layer (32) on the first insulating layer (31) so that the cavity (2) is enclosed between the first insulating layer (31), the second insulating layer (32) and the first surface.

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