Peripheral Component Interconnect Express (PCIe) board, cable, verification system and computer

Abstract

The present invention provides a PCIe board for a high-speed peripheral interconnect interface, comprising: a substrate; one or more PCIe slots, each PCIe slot having auxiliary signal pins and a plurality of data path pins; one or more data path connector groups, which are arranged in one-to-one correspondence with the one or more PCIe slots, each data path connector group having one or more data path connectors, and the data path connectors are communicatively connected to at least some of the data path pins in the corresponding PCIe slot in a one-to-one correspondence; an auxiliary signal connector, which is communicatively connected to the auxiliary signal pins of one or more PCIe slots of the PCIe slot. The PCIe board for a high-speed peripheral interconnect interface provided by the present invention can introduce any number of data path pins in the PCIe slots to be expanded into the corresponding data path connectors, and can freely and flexibly use or verify the PCIe ports.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIe communication, and particularly to a PCIe board, a cable, a verification system and a computer for high-speed interconnection of peripherals. Background Art

[0002] At present, the maximum number of data path pins supported by a PCIe port is PCIe X16. In addition, there are also PCIe ports with data path pins such as PCIe X8, PCIe X4, PCIe X2, and PCIe X1. During the design of the central processing unit (CPU) chip, generally, a PCIe X16 port is designed to support multiple ports with various numbers of data path pins such as X8, X4, X2, and X1. That is, an X16 can be configured as an X16 port, or can be configured as 2 X8 ports, or 8 X2 ports, or 16 X1 ports, or a combination of multiple ports with different widths of data path pins, such as a combination of 1 X8 port, 1 X4 port, and 2 X2 ports. Based on this design concept, whether in functional verification or during use, it is necessary to expand a PCIe X16 slot into multiple PCIe slots for use or verification. In the prior art, there are no conditions for flexibly verifying and using multiple ports. Summary of the Invention

[0003] The PCIe board, cable, verification system and computer for high-speed interconnection of peripherals provided by the present invention can independently transmit each data path pin of the PCIe slot to be expanded. During verification and use, any number of data path pins in the PCIe slot to be expanded can be introduced into the corresponding data path connectors, enabling free and flexible use or verification of the PCIe port.

[0004] In a first aspect, the present invention provides a PCIe board for high-speed interconnection of peripherals, including:

[0005] A substrate;

[0006] One or more PCIe slots are provided on the substrate, and each PCIe slot has auxiliary signal pins and multiple data path pins;

[0007] One or more groups of data path connectors are provided on the substrate. One or more groups of data path connectors are provided in one-to-one correspondence with the one or more PCIe slots. Each group of data path connectors has one or more data path connectors, and the data path connectors are communicatively connected to at least some of the data path pins in the corresponding PCIe slot in one-to-one correspondence;

[0008] An auxiliary signal connector is provided on a substrate, and the auxiliary signal connector is communicatively connected to the auxiliary signal pins of more than one PCIe slot of the PCIe slots.

[0009] Optionally, it further includes a power module provided on the substrate; the power module is electrically connected to the more than one PCIe slot for supplying power to the more than one PCIe slot.

[0010] Optionally, the more than one PCIe slot includes one or more than two types of PCIe slots among PCIe X8, PCIe X4 or PCIe X2.

[0011] Optionally, the data path pins communicatively connected to the data path connector are data path pins arranged continuously near the auxiliary signal pins.

[0012] In a second aspect, the present invention provides a PCIe cable for a high-speed peripheral interconnect interface, including:

[0013] A PCIe connector adapted to the PCIe slot to be expanded;

[0014] A data path harness having multiple signal transmission lines, and the multiple signal transmission lines are communicatively connected to the data path pins of the PCIe connector in a one-to-one correspondence;

[0015] An auxiliary signal harness communicatively connected to the auxiliary signal pins of the PCIe connector;

[0016] Multiple data path connectors communicatively connected to the multiple signal transmission lines in the data path harness in a one-to-one correspondence;

[0017] An auxiliary signal connector communicatively connected to the auxiliary signal harness.

[0018] Optionally, the auxiliary signal includes one or more than two types of signals among a clock signal, a reset signal or a system management bus signal.

[0019] In a third aspect, the present invention provides a PCIe verification system for a high-speed peripheral interconnect interface, including:

[0020] A PCIe board for a high-speed peripheral interconnect interface as described in any one of the above;

[0021] A PCIe cable for a high-speed peripheral interconnect interface as described in any one of the above;

[0022] The auxiliary signal connector is communicatively connected to the auxiliary signal connector, and at least some of the data path connectors are communicatively connected to at least some of the data path connector groups to verify the PCIe slots corresponding to the data path connector groups.

[0023] Optionally, it further includes:

[0024] A main board, including a PCIe slot to be expanded and a central processing unit (CPU) base, where the CPU base is communicatively connected to the PCIe slot to be expanded, and the PCIe connector is communicatively connected to the PCIe slot to be expanded.

[0025] In a fourth aspect, the present invention provides a computer, including:

[0026] A chassis;

[0027] A main board, disposed in the chassis and fixedly connected to the chassis; the main board has a PCIe slot to be expanded;

[0028] A peripheral component interconnect express (PCIe) board card as described in any one of the above;

[0029] A peripheral component interconnect express (PCIe) cable as described in any one of the above;

[0030] A PCIe connector is communicatively connected to the PCIe slot to be expanded, the auxiliary signal connector is communicatively connected to the auxiliary signal connector, and at least part of the data path connectors are communicatively connected to at least part of the data path connector groups to expand the PCIe slot to be expanded into multiple PCIe slots.

[0031] Optionally, the PCIe board card of the peripheral component interconnect express interface is spaced apart from the main board, and the PCIe board card of the peripheral component interconnect express interface is disposed in the chassis and fixedly connected to the chassis.

[0032] In the technical solution provided by the present invention, data path connectors are provided on the PCIe board card, and the data path connectors are communicatively connected to the data path pins in the PCIe slot one by one. The PCIe connectors in the PCIe cable are used to divide the pin signals of the PCIe connector into individual pin signals and lead them out. Thus, through any combination of data path connectors, the PCIe slot to be expanded can be expanded into PCIe slots of any specification. Whether it is during the functional verification process of the CPU or during the use of the PCIe slot, the PCIe slot can be freely and flexibly expanded and used. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of a peripheral component interconnect express (PCIe) board card according to an embodiment of the present invention;

[0034] Figure 2 It is a schematic diagram of a peripheral component interconnect express (PCIe) cable according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] The embodiments of the present invention provide a Peripheral Component Interconnect Express (PCIe) board for high-speed interconnection of peripherals, as Figure 1 shown, including:

[0037] A substrate; in some embodiments, the substrate can be prepared from a printed circuit board. The main function of the substrate is to support the slots, data path connectors, and auxiliary signal connectors, and is also used for the wiring between the slots and the data path connectors and the wiring between the slots and the auxiliary signal connectors.

[0038] One or more PCIe slots are provided on the substrate. Each PCIe slot has auxiliary signal pins and a plurality of data path pins; in some embodiments, the PCIe slots can be selected as PCIe slots with any number of data path connection pins. However, in order to save area and component resources, when the PCIe slot to be expanded is X16, an X8 PCIe slot can be provided on the substrate because the X8 PCIe slot can be compatible with any specification below X16, facilitating flexible expansion.

[0039] One or more groups of data path connectors are provided on the substrate. One or more groups of data path connectors are provided in one-to-one correspondence with the one or more PCIe slots. Each group of data path connectors has one or more data path connectors, and the data path connectors are communicatively connected to at least some of the data path pins in the corresponding PCIe slot in one-to-one correspondence; in some embodiments, the data path connectors are formed by leading out some of the data path pins in the PCIe slot and then communicatively connecting with connector devices. When an external signal is connected to the data path connector, a communication connection can be established with the data path pins in the corresponding PCIe slot.

[0040] An auxiliary signal connector is provided on the substrate. The auxiliary signal connector is communicatively connected to the auxiliary signal pins of one or more of the PCIe slots. The auxiliary signal connector is formed by leading out the auxiliary signal pins in the PCIe slot and then connecting them to a connector. Since the transmission of the auxiliary signals of PCIe slots of various specifications is the same, one auxiliary signal connector can be used to connect to multiple PCIe slots.

[0041] In the technical solution provided in this embodiment, a data path connector is set on the PCIe board, and the data path connector is communicatively connected to the data path pins in the PCIe slot one by one. The PCIe connector in the PCIe cable is used to divide the pin signals of the PCIe connector into single pin signals and lead them out. Thus, through any combination of data path connector combinations, the PCIe slot to be expanded can be expanded into a PCIe slot of any specification. Whether it is during the functional verification process of the CPU or during the use of the PCIe slot, the PCIe slot can be freely and flexibly expanded and used.

[0042] As an optional implementation manner, it further includes a power supply module, which is set on the substrate; the power supply module is electrically connected to the one or more PCIe slots to supply power to the one or more PCIe slots. In some embodiments, the power supply module can supply power to multiple PCIe slots. The power supply module is connected to an external power supply, and after processing such as voltage transformation of the external power supply, it supplies power to multiple PCIe slots.

[0043] As an optional implementation manner, the one or more PCIe slots include one or more than two PCIe slots of PCIe X8, PCIe X4 or PCIe X2. In some embodiments, 8 PCIe slots can be set on the substrate. For the convenience of installing the PCIe card, these PCIe slots use X8 connectors. Of course, other width slot connectors can also be selected. The 8 PCIe slots correspond to 8 data path connector groups. Among them, 4 PCIe slots correspond to the X2 data path connector group. For example, each PCIe slot is connected to 2 high-density high-speed card-edge connectors MCIO female connectors, and each MCIO female connector is connected to a data path pin of the corresponding PCIe slot. Among them, 2 PCIe slots correspond to the X4 data path connector group, and each PCIe slot is connected to 4 MCIO female connectors, and each MCIO female connector is connected to a data path pin of the corresponding PCIe slot. Among them, 2 PCIe slots correspond to the X8 data path connector group, and each PCIe slot is connected to 8 MCIO female connectors, and each MCIO female connector is connected to a data path pin of the corresponding PCIe slot. In the above connection method, whether it is the X8 data path connector group, the X4 data path connector group, or the X2 data path connector group, they all correspond to the X8 slot. Of course, the X4 data path connector group can also correspond to the X4 slot, and the X2 data path connector group can correspond to the X2 slot. It is also possible to correspond the X4 data path connector group to the X4 slot and the X2 data path connector group to the X4 slot as well.

[0044] As an alternative embodiment, the data path pins communicatively connected to the data path connector are data path pins arranged continuously near the auxiliary signal pins. In some embodiments, starting from one end close to the auxiliary signal pins, a plurality of data path pins are continuously selected and connected to the data path connector. Thus, when the PCIe connector specification of the PCIe peripheral is smaller than the slot, it can be correctly used when inserted into the slot. For example, when the PCIe slot installed on the substrate is an X8 slot and the accessed signal is an X4 signal, at this time, the connector of the PCIe peripheral is also an X4 connector. Only by selecting the pins according to this embodiment can the PCIe peripheral be correctly supported.

[0045] An embodiment of the present invention provides a PCIe cable for high-speed interconnection of peripherals, such as Figure 2 shown, including:

[0046] A PCIe connector adapted to the PCIe slot to be extended; in some embodiments, the PCIe connector can be, for example, a PCIe gold finger. When the PCIe connector is a X16 connector, it has 16 data path pins.

[0047] A data path harness having a plurality of signal transmission lines, and the plurality of signal transmission lines are communicatively connected to the data path pins of the PCIe connector in one-to-one correspondence; in some embodiments, the number of signal transmission lines should generally correspond to the number of PCIe connectors to facilitate the use or verification of various combination modes of PCIe. However, when the usage or verification requirements are less and only some signals in the X16 connector are needed, a smaller number of signal transmission lines can be selected.

[0048] An auxiliary signal harness communicatively connected to the auxiliary signal pins of the PCIe connector; in some embodiments, the auxiliary signal harness is a signal that plays an auxiliary role during PCIe data transmission, such as a clock signal, a system management bus signal, or a reset signal, etc.

[0049] A plurality of data path connectors communicatively connected to the plurality of signal transmission lines in the data path harness in one-to-one correspondence; in some embodiments, the plurality of data path connectors are respectively connected to the plurality of signal transmission lines, and the plurality of data path connectors do not physically limit each other, and each data path connector can be independently connected to the corresponding position.

[0050] An auxiliary signal connector is communicatively connected to the auxiliary signal harness. In some embodiments, since the transmission of the auxiliary signals of PCIe slots of various specifications is the same, one auxiliary signal connector can be used. During use, the auxiliary signal connector on the PCIe board can expand the auxiliary signal through chips, such as a system management conversion chip SMBUS Switch, a clock buffer chip CLK Buffer, and a general-purpose input / output buffer chip GPIO Buffer, and then connect it to multiple slots.

[0051] In the technical solution provided in this embodiment, a data path connector is provided on the PCIe board, and the data path connector is communicatively connected to the data path pins in the PCIe slot one by one. The PCIe connector in the PCIe cable is used to divide the pin signals of the PCIe connector into individual pin signals and lead them out. Thus, through any combination of data path connectors, the PCIe slot to be expanded can be expanded into a PCIe slot of any specification. Whether it is during the function verification process of the CPU or during the use of the PCIe slot, the PCIe slot can be freely and flexibly expanded and used.

[0052] As an optional implementation manner, the auxiliary signal includes one or more signals among a clock signal, a reset signal, or a system management bus signal.

[0053] In the above embodiments, multiple data path connectors and data path connectors can be of different types according to the supported PCIe rate. For example, in order to support PCIe Gen5, an MCIO gold finger male connector and an MCIO gold finger female connector are selected for connection. For the auxiliary signal, since the auxiliary signal has low requirements for rate, other connectors with lower rates can be selected to reduce costs, or MCIO gold finger connectors can be selected to improve its signal quality.

[0054] The embodiment of the present invention also provides a PCIe verification system for high-speed interconnection of peripherals, including:

[0055] The PCIe board for high-speed interconnection of peripherals as described in any one of the above;

[0056] The PCIe cable for high-speed interconnection of peripherals as described in any one of the above;

[0057] The auxiliary signal connector is communicatively connected to the auxiliary signal connector, and at least some of the data path connectors are communicatively connected to at least some of the data path connector groups to verify the PCIe slot corresponding to the data path connector group.

[0058] As a preferred implementation, the data path connectors corresponding to each slot on the PCIe board and the auxiliary signals are connected as follows. The numbers are as Figure 1 shown. The number of the auxiliary signal connector is MCIO-0. The data path connectors corresponding to each slot are numbered starting from MCIO-1 respectively. For example, the two data path connectors in the data path connector group of X2 are numbered MCIO-1 and MCIO-2 respectively; the four data path connectors in the data path connector group of X4 are numbered MCIO-1, MCIO-2, MCIO-3 and MCIO-4 respectively; the numbers of the data path connectors and the auxiliary signal connectors on the PCIe cable are as Figure 2 shown. The number of the auxiliary signal connector is M-MCIO-0; the 16 data path connectors are numbered from M-MCIO-1 to M-MCIO-16.

[0059] During the test, the connection methods corresponding to the data path connectors and the data path connectors are shown in Table 1 below:

[0060]

[0061] According to the connection method in the above table, the X16 PCIe slot can be expanded into 4 X2 PCIe slots and 2 X4 PCIe slots, so as to test the functions of the corresponding slots.

[0062] In addition, the 16 data path connectors can be inserted into the data path connector groups of two X8 in sequence to expand the X16 PCIe slot into 2 X8 PCIe slots, so as to test the corresponding functions.

[0063] In the technical solution provided in this embodiment, data path connectors are arranged on the PCIe board, and the data path connectors are communicatively connected to the data path pins in the PCIe slot one by one. The PCIe connectors in the PCIe cable are used to divide the pin signals of the PCIe connector into single pin signals and lead them out. Thus, through any combination of data path connectors, the PCIe slot to be expanded can be expanded into PCIe slots of any specification. Whether it is during the function verification process of the CPU or during the use of the PCIe slot, the PCIe slot can be freely and flexibly expanded and used.

[0064] As an alternative embodiment, it further includes: a main board, including a PCIe slot to be expanded and a central processing unit (CPU) socket, where the CPU socket is communicatively connected to the PCIe slot to be expanded, and the PCIe connector is communicatively connected to the PCIe slot to be expanded. In some embodiments, by providing a CPU socket and a PCIe slot to be expanded on the main board, installing the CPU on the CPU socket, and then expanding the PCIe slot to be expanded to a PCIe board card through a PCIe cable, it is possible to test the PCIe signals in the CPU. The main board provides support for the CPU and the PCIe slot to be expanded, and also provides peripheral power supply and signal management functions to ensure the normal progress of the test process.

[0065] An embodiment of the present invention further provides a computer, including:

[0066] A chassis;

[0067] A main board, disposed within the chassis and fixedly connected to the chassis; the main board has a PCIe slot to be expanded;

[0068] A peripheral component interconnect express (PCIe) board card as described in any one of the above;

[0069] A peripheral component interconnect express (PCIe) cable as described in any one of the above;

[0070] A PCIe connector is communicatively connected to the PCIe slot to be expanded, the auxiliary signal connector is communicatively connected to the auxiliary signal connector, and at least part of the data path connectors are communicatively connected to at least part of the data path connector groups to expand the PCIe slot to be expanded into multiple PCIe slots.

[0071] In the computer provided in this embodiment, the connection method in the previous embodiment can be followed. During use, the data path connectors can also be plugged and combined according to specific requirements. Thus, the flexibility of the PCIe slot expansion method is greatly improved. In the technical solution provided in this embodiment, data path connectors are provided on the PCIe board card, and the data path connectors are communicatively connected to the data path pins in the PCIe slot one by one. The PCIe connectors in the PCIe cable are used to divide the pin signals of the PCIe connector into single pin signals and lead them out. Thus, through any combination of the data path connectors, the PCIe slot to be expanded can be expanded into PCIe slots of any specification. Whether it is during the function verification process of the CPU or during the use of the PCIe slot, the PCIe slot can be freely and flexibly expanded and used.

[0072] As an alternative embodiment, the Peripheral Component Interconnect Express (PCIe) board of the peripheral high-speed interconnect interface is spaced apart from the motherboard, and the PCIe board of the peripheral high-speed interconnect interface is disposed in the chassis and fixedly connected to the chassis. In some embodiments, a PCIe cable is used to connect the PCIe board to the motherboard, and the PCIe board can be placed at an idle position in the chassis, greatly improving the flexibility of the space planning within the chassis.

[0073] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A Peripheral Component Interconnect Express (PCIe) board for high-speed interconnection of external devices, characterized in that, Comprising: A substrate; One or more PCIe slots provided on the substrate, each PCIe slot having auxiliary signal pins and a plurality of data path pins; One or more data path connector groups provided on the substrate, the one or more data path connector groups being provided in one-to-one correspondence with the one or more PCIe slots, each data path connector group having one or more data path connectors, the data path connectors being communicatively connected in one-to-one correspondence with at least some of the data path pins in the corresponding PCIe slot, and the one or more data path connectors being of different types according to the supported PCIe rates; An auxiliary signal connector provided on the substrate, the auxiliary signal connector being communicatively connected to the auxiliary signal pins of one or more of the PCIe slots.

2. The peripheral high-speed interconnect interface PCIe board according to claim 1, wherein It further includes a power supply module provided on the substrate; the power supply module is electrically connected to the one or more PCIe slots for supplying power to the one or more PCIe slots.

3. The peripheral high-speed interconnect interface PCIe board according to claim 1, characterized in that The one or more PCIe slots include one or more of PCIe X8, PCIe X4, or PCIe X2.

4. The PCIe board of the high-speed peripheral interconnect interface according to claim 1, wherein The data path pins communicatively connected to the data path connectors are data path pins arranged continuously near the auxiliary signal pins.

5. A PCIe cable for high-speed interconnection of peripheral devices, characterized in that, Comprising: A PCIe connector adapted to the PCIe slot to be expanded; A data path cable harness having a plurality of signal transmission lines, the plurality of signal transmission lines being communicatively connected in one-to-one correspondence with the data path pins of the PCIe connector; An auxiliary signal cable harness communicatively connected to the auxiliary signal pins of the PCIe connector; A plurality of data path connectors communicatively connected in one-to-one correspondence with the plurality of signal transmission lines in the data path cable harness, the plurality of data path connectors being of different types according to the supported PCIe rates; An auxiliary signal connector communicatively connected to the auxiliary signal cable harness.

6. The PCIe cable for high-speed interconnection of peripheral devices according to claim 5, wherein, The auxiliary signal includes one or more of a clock signal, a reset signal, or a system management bus signal.

7. A PCIe verification system for high-speed interconnection of peripheral devices, characterized in that, Comprising: The peripheral high-speed interconnect interface PCIe board card according to any one of claims 1-4; The peripheral high-speed interconnect interface PCIe cable according to any one of claims 5-6; The auxiliary signal connector is communicatively connected to the auxiliary signal connector, and at least some of the data path connectors are communicatively connected to at least some of the data path connector groups to verify the PCIe slot corresponding to the data path connector group.

8. The PCIe verification system for high-speed interconnection of peripheral devices according to claim 7, characterized in that, It further includes: A main board including a PCIe slot to be expanded and a central processing unit CPU socket, the CPU socket being communicatively connected to the PCIe slot to be expanded, and the PCIe connector being communicatively connected to the PCIe slot to be expanded.

9. A computer, characterized in that, Comprising: A chassis; A main board provided in the chassis and fixedly connected to the chassis; The main board has a PCIe slot to be expanded; The peripheral high-speed interconnect interface PCIe board card according to any one of claims 1-4; The peripheral high-speed interconnect interface PCIe cable according to any one of claims 5-6; The PCIe connector is communicatively connected to the PCIe slot to be expanded, the auxiliary signal connector head is communicatively connected to the auxiliary signal connector, and at least part of the data path connector head is communicatively connected to at least part of the data path connector group to expand the PCIe slot to be expanded into multiple PCIe slots.

10. The computer according to claim 9, characterized in that, The PCIe board of the peripheral high-speed interconnect interface is spaced apart from the motherboard, and the PCIe board of the peripheral high-speed interconnect interface is disposed in the chassis and fixedly connected to the chassis.

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