Programmable Logic Device Wiring Congestion Conflict Optimization Method, Device and Related Equipment

Abstract

The present invention discloses a method for optimizing routing congestion conflicts in a programmable logic device, which is applied to the field of programmable logic devices. The method provided by the present invention includes: performing pre-routing using a pre-router to obtain a routing conflict file; calculating a first conflict value for each signal relaxation block resource in the routing conflict file; dividing the signal relaxation block resources into different signal relaxation block resource blocks, and calculating a second conflict value for the signal relaxation block resource blocks according to the first conflict value; optimizing the layout of each signal relaxation block resource in the signal relaxation block resource blocks where the second conflict value is greater than a preset value; repeatedly performing the steps between pre-routing using the pre-router and optimizing the layout of the signal relaxation block resources in the signal relaxation block resource blocks where the second conflict value is greater than the preset value until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value.

Description

Technical Field

[0001] The present invention relates to the field of programmable logic devices (PLDs), and particularly to a method, apparatus, and related equipment for optimizing routing congestion conflicts in programmable logic devices. Background Art

[0002] With the increasing complexity and integration of programmable logic device designs, the occurrence of routing congestion conflicts during the design phase becomes more frequent and severe. Moreover, the scale of data to be processed for analyzing routing congestion conflicts also increases, resulting in an increase in the time consumed for computational analysis. That is, traditional methods for optimizing routing congestion conflicts not only have low efficiency in performing analysis and calculations but also have a reduced effect on optimizing routing congestion conflicts with the development of programmable logic devices. Summary of the Invention

[0003] Embodiments of the present invention provide a method, apparatus, computer device, and storage medium for optimizing routing congestion conflicts in programmable logic devices to solve the problems of low efficiency in optimizing and resolving routing congestion conflicts in programmable logic devices.

[0004] A method for optimizing routing congestion conflicts in a programmable logic device includes:

[0005] Performing pre-routing using a pre-router to obtain a routing conflict file;

[0006] Calculating a first conflict value for each signal relaxation block resource in the routing conflict file;

[0007] Dividing the signal relaxation block resources into different signal relaxation block resource blocks and calculating a second conflict value for the signal relaxation block resource blocks according to the first conflict value;

[0008] Optimizing the layout of each signal relaxation block resource in the signal relaxation block resource blocks where the second conflict value is greater than a preset value;

[0009] Repeatedly performing the steps between pre-routing using the pre-router and optimizing the layout of the signal relaxation block resources in the signal relaxation block resource blocks where the second conflict value is greater than the preset value until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value.

[0010] A device for optimizing routing congestion conflicts in a programmable logic device includes:

[0011] A pre-routing module for performing pre-routing using a pre-router to obtain a routing conflict file;

[0012] The first conflict value calculation module is used to calculate the first conflict value of each signal relaxation block resource in the routing conflict file;

[0013] The second conflict value calculation module is used to divide the signal relaxation block resources into different signal relaxation block resource blocks, and calculate the second conflict value of the signal relaxation block resource blocks according to the first conflict value;

[0014] The optimization module is used to optimize the layout of each signal relaxation block resource in the signal relaxation block resource block where the second conflict value is greater than the preset value;

[0015] The loop module is used to loop through the steps of using a pre-router for pre-routing until the layout of the signal relaxation block resources in the signal relaxation block resource block where the second conflict value is greater than the preset value is optimized, until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value.

[0016] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned programmable logic device routing congestion conflict optimization method are implemented.

[0017] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned programmable logic device routing congestion conflict optimization method are implemented.

[0018] In the above-mentioned programmable logic device routing congestion conflict optimization method, device, computer device, and storage medium, during the design process of the programmable logic device, after using a pre-router for pre-routing to obtain a routing conflict file, the signal relaxation block resources in the routing conflict file are divided into blocks, and the conflict value of each signal relaxation block resource block is calculated through a normalization processing method. Then, the signal relaxation block resource blocks with high conflict values are continuously optimized until the conflict values of all signal relaxation block resource blocks are within the preset range, improving the analysis efficiency of the programmable logic device routing congestion conflict and also improving the optimization effect of the programmable logic device routing congestion conflict. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1It is a flowchart of a method for optimizing routing congestion conflicts in a programmable logic device according to an embodiment of the present invention;

[0021] Figure 2 It is a schematic diagram of the conflict value distribution of signal relaxation block resources in a signal relaxation block resource block according to an embodiment of the present invention;

[0022] Figure 3 It is a schematic diagram of dividing a signal relaxation block resource into signal relaxation block resource blocks according to an embodiment of the present invention;

[0023] Figure 4 It is a schematic structural diagram of a device for optimizing routing congestion conflicts in a programmable logic device according to an embodiment of the present invention;

[0024] Figure 5 It is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] In one embodiment, as Figure 1 shown, a method for optimizing routing congestion conflicts in a programmable logic device is provided, including the following steps S101 to S105.

[0027] S101. Use a pre-router for pre-routing to obtain a routing conflict file.

[0028] Among them, in this embodiment, an FPGA (Field Programmable Gate Array) chip, which is one of the programmable logic devices, is taken as an example for illustration.

[0029] Among them, in the FPGA chip design process, the quality of the placement result directly affects the routing efficiency of the routing process, and the pros and cons of the routing process efficiency indirectly reflect the reasonable degree of the placement of resources; in the routing process, the scenario where routing conflicts occur and multiple rounds of routing are required is very common. Based on this, a pre-router CDRouter (Congestion Detection Router) is designed, which can perform pre-routing operations in the placement phase process before the routing process starts, call the pre-router to obtain a routing conflict file, and then optimize the placement result to reduce the congestion conflict degree in the routing process, thereby accelerating the routing efficiency.

[0030] S102. Calculate the first conflict value of each signal relaxation block resource in the routing conflict file.

[0031] Among them, the signal relaxation block (SRB) resource is the main placement and routing resource, and the congestion conflicts mainly occur on the output ports of the signal relaxation block.

[0032] Among them, the calculation of the first conflict value of each signal relaxation block resource in the routing conflict file includes the following steps:

[0033] Calculate the first conflict value of each signal relaxation block resource through the following formula:

[0034]

[0035] where jam i represents the output port conflict value on the i-th signal relaxation block resource, and sum represents the first conflict value of the signal relaxation block resource.

[0036] S103. Divide the signal relaxation block resources into different signal relaxation block resource blocks, and calculate the second conflict value of the signal relaxation block resource block according to the first conflict value.

[0037] Among them, the routing congestion conflict of the FPGA chip is often not isolated for a single signal relaxation block resource, but multiple signal relaxation block resources are concentrated in a certain area range; for analyzing the conflict situation of the signal relaxation block resources in a certain block, the homogenization treatment method HTM (Homogenization treatment method) is adopted, that is, multiple adjacent signal relaxation block resources are divided into a signal relaxation block resource block, and the sum of all output port conflict values of each signal relaxation block resource in the signal relaxation block resource block is used as the conflict value of the signal relaxation block resource block, and the average value of the conflict values of all signal relaxation block resources in the signal relaxation block resource block after homogenization treatment is used as the conflict value of the signal relaxation block resource block.

[0038] Among them, the calculation of the second conflict value specifically includes the following steps:

[0039] Divide the signal relaxation block resources into different signal relaxation block resource blocks;

[0040] Calculate the second conflict value of the signal relaxation block resource block according to the following formula:

[0041]

[0042] Among them, num represents the number of signal relaxation block resources in the signal relaxation block resource block. n and m represent that there are n*m signal relaxation block resources in the signal relaxation block resource block, that is, n rows and m columns or m rows and n columns, sun block represents the second conflict value of the signal relaxation block resource block.

[0043] As Figure 2 shown in the schematic diagram of the conflict value distribution of the signal relaxation block resources in a signal relaxation block resource block. There are 3*3 signal relaxation blocks in the signal relaxation block resource block. The minimum conflict value is 0 and the maximum conflict value is 9. Then, the conflict values of all signal relaxation block resources in the signal relaxation block resource block are normalized to obtain the average conflict value (2 + 7 + 5 + 6 + 9 + 0 + 3 + 8 + 7) / 9 = 5.2. For the convenience of calculation, the average conflict value is rounded down to obtain the average conflict value of 5. Finally, the average conflict value is used as the conflict value of the signal relaxation block resource block, that is, sun block The result of is 5.

[0044] Among them, the signal relaxation block resource block division parameters can be adjusted according to the actual scenario and empirical values, and should not be set too large or too small. They can also be passed in by the interface function through parameters; Figure 3 is a schematic diagram of dividing a signal relaxation block into signal relaxation block resources, which describes all signal relaxation block resources on the normalization processing chip. In the figure, taking uniform division as an example, different forms of the processing chip in 4 different scenarios are shown. The type with the most signal relaxation block resources is 3*3, and there are also a small number of 2*3 type and 3*2 type signal relaxation block resources, as well as the least 2*2 type signal relaxation block resources.

[0045] Further, after the step of dividing the signal relaxation block resources into different signal relaxation block resources and calculating the second conflict value of the signal relaxation block resource block according to the first conflict value, the following steps are further included;

[0046] According to the preset level division range, all the signal relaxation block resources are divided into levels;

[0047] According to the preset color corresponding to the level, assign corresponding colors to all the signal relaxation block resources;

[0048] Generate a heat map of the wiring congestion conflict area according to the positions of all the signal relaxation block resources in the wiring conflict file and the colors of the signal relaxation block resources.

[0049] Among them, the heat map of the routing congestion conflict area can intuitively show the user which areas on the FPGA chip have the most obvious congestion conflicts. For example, green is used to represent areas with less congestion conflicts, yellow is used to represent areas with greater congestion conflicts, and red is used to represent areas with serious congestion conflicts.

[0050] S104. Optimize the layout of each signal relaxation block resource in the signal relaxation block resource block where the second conflict value is greater than the preset value.

[0051] Among them, the following steps are adopted to optimize the congestion conflict of the signal relaxation block resource block:

[0052] Arrange all the signal relaxation block resources in the signal relaxation block resource block in descending or ascending order according to the first conflict value;

[0053] Take out the signal relaxation block resources whose first conflict value is greater than the preset congestion conflict threshold of the signal relaxation block resources and put them into the set to be optimized;

[0054] According to the number of signal relaxation block resources in the set to be optimized, establish multiple threads and divide the signal relaxation block resources to the threads for optimization.

[0055] S105. Loop through the steps between using the pre-router for pre-routing and optimizing the layout of the signal relaxation block resources in the signal relaxation block resource block where the second conflict value is greater than the preset value until the second conflict value of all signal relaxation block resources blocks is not greater than the preset value.

[0056] Furthermore, in each iteration, write the actual position and offset of the programmable logic device of the routing conflict file and the pre-routing conflict data finally generated in each iteration into a file for storage.

[0057] Among them, the actual position can be, but is not limited to, the lower left corner, lower right corner, upper left corner, upper right corner, and center point position of the programmable logic device.

[0058] Among them, writing the pre-routing conflict data finally generated in each iteration into a file for storage is convenient for taking out the pre-routing conflict data generated in each iteration for analysis after the routing congestion conflict optimization process ends, comparing the pre-routing changes and optimization effects in each iteration, and further improving the efficiency of the optimization algorithm.

[0059] The programmable logic device wiring congestion conflict optimization method proposed in this embodiment, during the process of designing the FPGA chip, after using a pre-router for pre-routing to obtain a wiring conflict file, divides the signal relaxation block resources in the wiring conflict file into blocks, calculates the conflict value of each signal relaxation block resource block through a normalization processing method, and simultaneously generates a wiring congestion conflict heat map to more intuitively reflect the wiring congestion conflict situation of the FPGA chip. Then, continuously optimize the signal relaxation block resource blocks with high conflict values until the conflict values of all signal relaxation block resource blocks are within a preset range, which improves the analysis efficiency of the wiring congestion conflict of the FPGA chip and also improves the optimization effect of the wiring congestion conflict of the FPGA chip.

[0060] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0061] In one embodiment, a programmable logic device wiring congestion conflict optimization device 20 is provided. The programmable logic device wiring congestion conflict optimization device 20 corresponds one-to-one with the programmable logic device wiring congestion conflict optimization method in the above embodiment. As Figure 4 shown, the programmable logic device wiring congestion conflict optimization device 20 includes a pre-routing module 201, a first conflict value calculation module 202, a second conflict value calculation module 203, an optimization module 204, and a loop module 205. The detailed description of each functional module is as follows:

[0062] The pre-routing module 201 is used to perform pre-routing using a pre-router to obtain a wiring conflict file;

[0063] The first conflict value calculation module 202 is used to calculate the first conflict value of each signal relaxation block resource in the wiring conflict file;

[0064] The second conflict value calculation module 203 is used to divide the signal relaxation block resources into different signal relaxation block resource blocks and calculate the second conflict value of the signal relaxation block resource blocks according to the first conflict value;

[0065] The optimization module 204 is used to optimize the layout of each signal relaxation block resource in the signal relaxation block resource block where the second conflict value is greater than the preset value;

[0066] The loop module 205 is used to loop through the steps between performing pre-routing using a pre-router and optimizing the layout of the signal relaxation block resources in the signal relaxation block resource block where the second conflict value is greater than the preset value until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value.

[0067] Furthermore, the first conflict value calculation module 202 further includes the following functions:

[0068] Calculate the first conflict value of each signal relaxation block resource through the following formula:

[0069]

[0070] where jam i represents the output port conflict value on the i-th signal relaxation block resource, and sum represents the first conflict value of the signal relaxation block resource.

[0071] Furthermore, the second conflict value calculation module 203 further includes the following units:

[0072] A resource partitioning unit for partitioning the signal relaxation block resources into different signal relaxation block resource blocks;

[0073] A conflict value calculation unit for calculating the second conflict value of the signal relaxation block resource block according to the following formula:

[0074]

[0075] where num represents the number of the signal relaxation block resources in the signal relaxation block resource block, n and m represent that there are n*m signal relaxation block resources in the signal relaxation block resource block, that is, n rows and m columns or m rows and n columns, sun block represents the second conflict value of the signal relaxation block resource block.

[0076] Among them, the second conflict calculation module specifically includes:

[0077] A level partitioning unit for partitioning all the signal relaxation block resources blocks according to a preset level partitioning range;

[0078] A color configuration unit for assigning corresponding colors to all the signal relaxation block resources blocks according to the preset level corresponding colors;

[0079] A heat map generation unit for generating a heat map of the routing congestion conflict area according to the positions of all the signal relaxation block resources blocks and the colors of the signal relaxation block resources blocks in the routing conflict file.

[0080] Furthermore, the loop module 205 further includes the following units:

[0081] A file writing unit for writing the actual positions and offsets of the programmable logic devices of the routing conflict file and the pre-routing conflict data finally generated in each iteration into a file for storage in each iteration.

[0082] The meanings of "first" and "second" in the above-mentioned modules / units are only used to distinguish different modules / units, and are not used to define which module / unit has a higher priority or other defining meanings. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or modules does not have to be limited to those steps or modules clearly listed, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or devices. The division of modules in this application is only a logical division, and there may be other division methods in actual implementation.

[0083] For the specific limitations of the programmable logic device wiring congestion conflict optimization device, reference can be made to the limitations of the programmable logic device wiring congestion conflict optimization method in the above text, which will not be elaborated here. Each module in the above programmable logic device wiring congestion conflict optimization device can be implemented in whole or in part by software, hardware and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above modules.

[0084] In one embodiment, a computer device is provided. The computer device can be a programmable logic device. The computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the programmable logic device wiring congestion conflict optimization method in the above embodiment, such as Figure 1 the steps 101 to 105 shown and the extension of other extended and related steps of the method. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit of the programmable logic device wiring congestion conflict optimization device in the above embodiment, such as Figure 4 the functions of the modules 201 to 205 shown. To avoid repetition, it will not be elaborated here.

[0085] The processor can be a Central Processing Unit (CPU), or can also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The processor is the control center of the computer device, and connects various parts of the entire computer device using various interfaces and lines.

[0086] The memory can be used to store the computer program and / or modules. The processor realizes various functions of the computer device by running or executing the computer program and / or modules stored in the memory, and by calling the data stored in the memory. The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function (such as a text editing function, an image drawing function, etc.); the data storage area can store data created according to the use of the mobile phone (such as text data, image data, etc.).

[0087] The memory can be integrated in the processor or can be separately provided from the processor.

[0088] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the programmable logic device routing congestion conflict optimization method in the above embodiment are realized, such as Figure 1 the steps 101 to 105 shown and the extensions and related steps of the method. Or, when the computer program is executed by a processor, the functions of the various modules / units of the programmable logic device routing congestion conflict optimization device in the above embodiment are realized, such as Figure 4 the functions of the modules 201 to 205 shown. To avoid repetition, it will not be elaborated here.

[0089] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile and / or volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0090] Those skilled in the art can clearly understand that for the convenience and brevity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0091] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for optimizing routing congestion conflicts in a programmable logic device, characterized in that, it includes: Using a pre-router for pre-routing to obtain a routing conflict file; Calculating a first conflict value for each signal relaxation block resource in the routing conflict file; Dividing the signal relaxation block resources into different signal relaxation block resource blocks, and calculating a second conflict value for the signal relaxation block resource blocks according to the first conflict value; Optimizing the layout of each signal relaxation block resource in the signal relaxation block resource blocks where the second conflict value is greater than a preset value; Repeatedly using the pre-router for pre-routing until the layout of the signal relaxation block resources in the signal relaxation block resource blocks where the second conflict value is greater than the preset value is optimized, until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value.

2. The method for optimizing routing congestion conflicts in a programmable logic device according to claim 1, characterized in that, The calculating the first conflict value for each signal relaxation block resource in the routing conflict file includes the following steps: Calculating the first conflict value for each signal relaxation block resource through the following formula: where jam i represents the output port conflict value on the i-th signal relaxation block resource, and sum represents the first conflict value of the signal relaxation block resource.

3. The method for optimizing routing congestion conflicts in a programmable logic device according to claim 2, characterized in that, The dividing the signal relaxation block resources into different signal relaxation block resource blocks and calculating the second conflict value for the signal relaxation block resource blocks according to the first conflict value includes the following steps: Dividing the signal relaxation block resources into different signal relaxation block resource blocks; Calculating the second conflict value for the signal relaxation block resource blocks according to the following formula: where num represents the number of the signal relaxation block resources in the signal relaxation block resource block, n and m indicate that there are n*m signal relaxation block resources in the signal relaxation block resource block, and sun block represents the second conflict value of the signal relaxation block resource block.

4. The method for optimizing routing congestion conflicts in a programmable logic device according to claim 1, characterized in that, After the step of dividing the signal relaxation block resources into different signal relaxation block resource blocks and calculating the second conflict value for the signal relaxation block resource blocks according to the first conflict value, the following steps are further included; Dividing all the signal relaxation block resource blocks according to a preset level division range; Assigning corresponding colors to all the signal relaxation block resource blocks according to the preset level corresponding colors; Generating a routing congestion conflict area heat map according to the positions of all the signal relaxation block resource blocks in the routing conflict file and the colors of the signal relaxation block resource blocks.

5. The method for optimizing routing congestion conflicts in a programmable logic device according to claim 1, characterized in that, The step of repeatedly using the pre-router for pre-routing until the layout of the signal relaxation block resources in the signal relaxation block resource blocks where the second conflict value is greater than the preset value is optimized, until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value includes the following steps: In each iteration, writing the actual position and offset of the programmable logic device in the routing conflict file and the pre-routing conflict data finally generated in each iteration into a file for storage.

6. A device for optimizing routing congestion conflicts in a programmable logic device, characterized in that, it includes: A pre-routing module for using a pre-router for pre-routing to obtain a routing conflict file; The first conflict value calculation module is used to calculate the first conflict value of each signal relaxation block resource in the wiring conflict file; The second conflict value calculation module is used to divide the signal relaxation block resources into different signal relaxation block resource blocks, and calculate the second conflict value of the signal relaxation block resource blocks according to the first conflict value; The optimization module is used to optimize the layout of each signal relaxation block resource in the signal relaxation block resource block where the second conflict value is greater than a preset value; The loop module is used to loop through the steps between pre-routing using a pre-router and optimizing the layout of the signal relaxation block resources in the signal relaxation block resource block where the second conflict value is greater than a preset value until the second conflict value of all signal relaxation block resource blocks is not greater than the preset value.

7. The programmable logic device wiring congestion conflict optimization device according to claim 6, wherein, the second conflict calculation module further includes: The level division unit is used to divide all the signal relaxation block resources into levels according to a preset level division range; The color configuration unit is used to assign corresponding colors to all the signal relaxation block resources according to the colors corresponding to the preset levels; The heat map generation unit is used to generate a wiring congestion conflict area heat map according to the positions of all the signal relaxation block resources in the wiring conflict file and the colors of the signal relaxation block resources.

8. The programmable logic device wiring congestion conflict optimization device according to claim 7, wherein, the loop module further includes: The file writing unit is used to write the actual position and offset of the programmable logic device in the wiring conflict file and the pre-routing conflict data finally generated in each iteration into a file for storage in each iteration.

9. A computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein, when the processor executes the computer program, the steps of the programmable logic device wiring congestion conflict optimization method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium storing a computer program, wherein, when the computer program is executed by a processor, the steps of the programmable logic device wiring congestion conflict optimization method according to any one of claims 1 to 5 are implemented.

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