Integrated circuit design method, system and computer program product

Abstract

The present disclosure relates to integrated circuit design methods, systems and computer program products. A method is performed at least in part by a processor, the method comprising creating multiple groups of paths from multiple paths in an integrated circuit (IC) layout diagram. Each group in the multiple groups has a main feature among multiple features of the multiple paths. The main features of the multiple groups are different from each other. The method also includes testing at least one path in one of the multiple groups. The method also includes modifying at least one of the following items in response to the test indicating that the at least one path has not passed: the IC layout diagram, at least a portion of at least one library of cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit design methods, systems and computer program products. Background Art

[0002] An integrated circuit (IC) typically includes a plurality of semiconductor devices represented in an IC layout diagram. The IC layout diagram is hierarchical and includes modules that perform higher-level functions according to the design specifications of the semiconductor device. These modules are typically composed of a combination of cells, each of which represents one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layout diagrams (sometimes referred to as standard cells) are stored in a standard cell library (hereinafter referred to as a "library" or "cell library") and can be accessed by various tools (e.g., electronic design automation (EDA) tools) to generate, optimize, and verify the design of the IC. At various steps during the IC design process, various checks and tests are performed to ensure that the IC can be manufactured and function as designed. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for integrated circuit design is provided, the method being at least partially executed by a processor, the method comprising: creating a plurality of groups of paths from a plurality of paths in an integrated circuit IC layout diagram, wherein each of the plurality of groups has a main feature among a plurality of features of the plurality of paths, and the main features of the plurality of groups are different from each other; testing at least one path in one of the plurality of groups; and in response to the test indicating that the at least one path has failed, modifying at least one of the following: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0004] According to another embodiment of the present disclosure, a system for integrated circuit design is provided, comprising a processor, wherein the processor is configured to: extract multiple features of multiple paths in an integrated circuit IC layout diagram, cluster the multiple paths into multiple clusters, determine, for each of the multiple clusters, a main feature of the each cluster, the main feature being included in the multiple features, create multiple groups of paths from the multiple clusters based on the main features of the multiple clusters, each of the multiple groups having a unique main feature among the main features, perform automatic test pattern generation ATPG to generate at least one test pattern for each of the multiple groups, perform a test on at least one path in each group using the generated at least one test pattern, and in response to the test indicating that the at least one path fails, modify at least one of the following: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0005] According to another embodiment of the present disclosure, a computer program product is provided, including a non-transitory computer-readable medium, which includes instructions, which, when executed by a processor, cause the processor to perform the following operations: creating multiple groups of paths from multiple paths in an integrated circuit IC layout diagram by the following operations: clustering the multiple paths into multiple clusters, determining a main feature for each of the multiple clusters, the main feature being included in the multiple features of the multiple paths, designating each cluster having a main feature different from the main feature of other clusters as one of the multiple groups, and merging clusters with the same main feature to obtain another group of the multiple groups; performing a test on at least one path in one of the multiple groups; and in response to the at least one path failing the test, modifying at least one of the following items: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, various aspects of the present disclosure will be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a functional flow diagram of at least a portion of an IC design flow according to some embodiments.

[0008] Figures 2A-2Fis a schematic logic diagram of portions of an IC layout diagram with example paths according to some embodiments.

[0009] Figure 2G is a schematic diagram of various extracted features of paths in an IC layout diagram according to some embodiments.

[0010] Figure 3A is a flow diagram of a process in a feature encoding and reduction operation according to some embodiments.

[0011] Figure 3B is a schematic data representation of example features in a first feature reduction operation according to some embodiments.

[0012] Figure 3C is a schematic diagram of a table including various numerical features and categorical features with corresponding values ​​in several example paths in a first encoding operation according to some embodiments.

[0013] Figure 3D is a schematic diagram of a table including example features with corresponding values ​​in several example paths in a second encoding operation according to some embodiments.

[0014] Figure 3E is a schematic diagram of a table including example features with corresponding values ​​in several example paths in a third encoding operation according to some embodiments.

[0015] Figure 3F is a schematic diagram of a table of various numerical features and categorical features with corresponding values ​​in several example paths in a normalization operation, according to some embodiments.

[0016] Figure 3G is a schematic diagram of a table including various features with corresponding correlation coefficients in a second feature reduction operation according to some embodiments.

[0017] Figure 3H is a schematic diagram of a simplified feature set of paths in an IC layout diagram according to some embodiments.

[0018] Figure 4 is a flow diagram of a process in feature clustering and path grouping operations according to some embodiments.

[0019] Figure 5 is a flow diagram of a process according to some embodiments.

[0020] Figure 6 is a block diagram of an EDA system according to some embodiments.

[0021] Figure 7is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are considered. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted to form, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0024] In the IC design process, one or more pre-manufacturing verifications or post-manufacturing verifications are performed to identify potential faults in an IC layout diagram or an IC (chip) manufactured according to the IC layout diagram. In some embodiments, multiple paths in the IC layout diagram are grouped into multiple groups. The paths in each group share common main features, such as timing features, logical features, or physical features. Tests are performed on at least one path in each group. When the path fails the test, the main feature associated with the corresponding group is identified as being related to a system defect. Based on the main feature identified as being related to a system defect, at least one of the IC layout diagram, a library with a cell included in the IC layout diagram, or a manufacturing process is corrected to repair the fault path. As a result, in at least one embodiment, multiple paths sharing the same main feature can be repaired or improved by a common correction strategy. In one or more embodiments, by grouping paths according to the main features for testing, various system defects that are not identified in other methods can be identified and corrected.

[0025] Figure 11 is a functional flow chart of at least a portion of an IC design flow 100 according to some embodiments. The IC design flow 100 utilizes one or more electronic design automation (EDA) tools for generating, optimizing, and / or verifying the design of an IC before and / or after manufacturing the IC. In some embodiments, the EDA tool is a tool for executing a program executed by a processor or controller or a programmed computer (e.g., system 600 ( Figure 6 )) is executed to perform one or more sets of executable instructions for performing the functions shown. In at least one embodiment, the IC design process 100 is provided by the present invention for Figure 7 Discuss the design house implementation of IC manufacturing systems.

[0026] In IC design generation operation 110, a design of an IC is provided by a circuit designer. In some embodiments, the design of the IC includes an IC schematic diagram, i.e., a circuit diagram, of the IC. In some embodiments, the schematic diagram is generated or provided in the form of a schematic netlist (e.g., a special purpose simulation program for integrated circuits (SPICE) netlist). Other data formats (e.g., Verilog) for describing the design are available in some embodiments. In some embodiments, a pre-layout simulation is performed on the design to determine whether the design meets predetermined specifications. When the design does not meet predetermined specifications, the IC is redesigned. In at least one embodiment, the pre-layout simulation is omitted.

[0027] In the cell placement and routing operation 120, a layout diagram of the IC is generated based on the IC schematic diagram. In at least one embodiment, the cell placement and routing operation 120 is referred to as automatic placement and routing (APR). The IC layout diagram includes the physical locations of various circuit elements of the IC and the physical locations of various networks (nets) of the interconnected circuit elements. For example, the IC layout diagram is generated in the form of a graphic design system (GDS) file. Other data formats (such as design exchange format (DEF)) for describing the design of the IC are within the scope of various embodiments. In at least one embodiment, the IC layout diagram is generated by an EDA tool (such as an APR tool). As described herein, the APR tool receives the design of the IC in the form of a netlist. The APR tool performs a layout plan for identifying circuit elements that will be electrically connected to each other and placed in close proximity to each other to reduce the area of ​​the IC and / or reduce the time delay of the signal transmitted by the interconnection or network that connects the electrically connected circuit elements together. In some embodiments, the APR tool performs partitioning to divide the design of the IC into multiple blocks or groups, such as clock and logic groups. Example operations of the APR tool include, but are not limited to, cell placement operations and routing operations.

[0028] In the cell layout operation, the APR tool performs cell layout. Cells configured to provide predefined functions and having pre-designed layout diagrams are stored in one or more cell libraries, for example, in a library exchange format (LEF). LEF is a specification that includes design rules and related information of cells in the library. In at least one embodiment, LEF is used together with DEF to represent the physical layout of the IC being designed. The APR tool accesses various cells from one or more cell libraries and places cells in an adjacent manner to generate an IC layout diagram corresponding to the IC schematic diagram. Each cell includes one or more circuit elements and / or one or more networks. Circuit elements are active elements or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drains, etc. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. Examples of networks include, but are not limited to, vias, conductive pads, conductive traces, and conductive redistribution layers, among others.

[0029] In the routing operation, the APR tool performs routing to route various networks of the circuit elements placed by the interconnection. Routing is performed to ensure that the interconnection or network being routed meets a set of constraints. For example, the routing operation includes global routing, trace allocation, and detailed routing. During global routing, routing resources for the interconnection or network are allocated. For example, the routing area is divided into a plurality of sub-areas, the pins (or terminals) of the placed circuit elements are mapped to the sub-areas, and the network is constructed as a set of sub-areas, in which the interconnection is physically routable. During trace allocation, the APR tool assigns the interconnection or network to the corresponding conductive layer of the IC layout diagram. During detailed routing, the APR tool routes the interconnection or network within the specified conductive layer and global routing resources. For example, the detailed physical interconnection is generated within the corresponding sub-area set defined in the global routing and in the conductive layer defined in the trace allocation. After the routing operation, the APR tool outputs the IC layout diagram, including the placed circuit elements and the routed network. The APR tool is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the operations described are omitted, or one or more additional operations are added before, during, or after the operations described.

[0030] In some embodiments, one or more verifications are performed after the cell place and route operation 120. Example verifications include, but are not limited to, layout-to-schematic (LVS) checking and design rule checking (DRC). Other verification processes may be used in other embodiments.

[0031] LVS check is performed to ensure that the generated IC layout diagram corresponds to the design of the IC. Specifically, the LVS check tool (i.e., EDA tool) identifies electrical components and connections between them from the pattern of the generated IC layout diagram. Then, the LVS check tool generates a layout netlist representing the identified electrical components and connections. By the LVS check tool, the layout netlist generated by the IC layout diagram is compared with the principle netlist of the IC design. If the two netlists match within the matching tolerance, the LVS check is passed. Otherwise, at least one of the IC layout diagram or the design of the IC is corrected by returning the process to at least one of the IC design generation operation 110 or the cell placement and routing operation 120.

[0032] For example, DRC is performed by an EDA tool to ensure that the IC layout diagram meets certain manufacturing design rules, that is, to ensure the manufacturability of the IC. If one or more design rules are violated, at least one of the IC layout diagram or the design of the IC is corrected by returning the process to at least one of the IC design generation operation 110 or the cell layout and routing operation 120. Examples of design rules include, but are not limited to: a width rule that specifies the minimum width of a pattern in the IC layout diagram, a spacing rule that specifies the minimum spacing between adjacent patterns in the IC layout diagram, an area rule that specifies the minimum area of ​​a pattern in the IC layout diagram, etc.

[0033] In a resistance and capacitance (RC) extraction operation 130 , RC extraction is performed, for example, by an EDA tool, to determine parasitic parameters, such as parasitic resistance and parasitic capacitance, of components in an IC layout for use in timing simulation in one or more subsequent operations.

[0034] In a static timing analysis (STA) operation 140, the EDA tool estimates delays in multiple paths in an IC layout diagram. The input data of the STA operation 140 includes, but is not limited to, the IC layout diagram, parasitic parameters extracted by the RC extraction operation 130, and cell delays obtained from one or more cell libraries having cells included in the IC layout diagram. The output data from the STA operation 140 is included in the timing report described herein. In at least one embodiment, the STA operation 140 is performed without simulating the operation of the IC corresponding to the IC layout diagram. In at least one embodiment, when the delay for one or more paths estimated in the STA operation 140 cannot meet the corresponding timing requirements, at least one of the IC layout diagram or the design of the IC is corrected by returning the process to at least one of the IC design generation operation 110 or the cell placement and routing operation 120.

[0035] In automatic path selection and testing (APST) operation 150, paths in the IC layout are grouped and test patterns are generated for the grouped paths. In some embodiments, APST operation 150 is performed at least in part by an EDA tool. Figure 1 1 also shows an exploded schematic diagram of further operations of the APST operation 150 according to some embodiments. The input data for the APST operation 150 includes one or more of the IC schematic 113 output from the IC design generation operation 110, the IC layout 123 output from the cell placement and routing operation 120, and the timing report 143 output from the STA operation 140. Figure 1 In the exemplary configuration of , the APST operation 150 includes a feature extraction operation 152 , a feature encoding and simplification operation 153 , a feature clustering operation 154 , a cluster analysis and path grouping operation 155 , and an automatic test pattern generation (ATPG) operation 156 .

[0036] In feature extraction operation 152, multiple features of the paths in the IC layout are extracted, such as Figure 2A-2G described.

[0037] In the feature encoding and simplification operation 153, the extracted features are encoded and simplified to obtain a simplified feature set, such as Figures 3A-3G described.

[0038] In feature clustering operation 154, the paths of the IC layout diagram are divided into a plurality of clusters, such as Figure 4 described.

[0039] In the cluster analysis and path grouping operation 155, the clusters are analyzed and grouped into a plurality of groups having associated unique primary characteristics, such as Figure 4 described.

[0040] In ATPG operation 156 , test patterns are generated for one or more paths in each group using one or more ATPG methodologies or algorithms, as described herein.

[0041] In the test operation 160, one or more paths in each group are tested using the test pattern generated by the ATPG operation 156 to determine whether the IC layout diagram or the actual IC manufactured according to the IC layout diagram meets the predetermined specifications of one or more timing requirements. In at least one embodiment, the test includes, for example, a post-layout simulation performed by an EDA tool to simulate the operation of the IC corresponding to the IC layout diagram. In some embodiments, the test is performed by an automatic test equipment (ATE) with hardware structures (e.g., probes) for testing the operation of the actual IC, which are electrically coupled to the actual IC (chip) manufactured according to the IC layout diagram. In one or more embodiments, the test in the test operation 160 includes both the post-layout simulation performed by the EDA tool and the test performed by the ATE on the actual IC. When the IC layout diagram and / or the actual IC manufactured based on the IC layout diagram passes the test, an additional verification process will be performed, or the IC will be manufactured based on the IC layout diagram.

[0042] In modification operation 170, when the IC layout diagram and / or the actual IC manufactured based on the IC layout diagram fails the test in test operation 160, correction is performed. In some embodiments, at least one of the IC layout diagram or the design of the IC is corrected by returning the process to at least one of the IC design generation operation 110 or the cell layout and routing operation 120. The correction of the IC design in the IC design generation operation 110 results in a corresponding correction of the IC layout diagram in the cell layout and routing operation 120. In some embodiments, one or more cell libraries having cells included in the IC layout diagram are corrected. The correction of one or more cell libraries results in a corresponding correction of the IC layout diagram in the cell layout and routing operation 120. In some embodiments, the manufacturing process for manufacturing the IC corresponding to the IC layout diagram is corrected. Figure 1 The IC design flow 100 in FIG. 1 is an example. In some embodiments, the IC design flow 100 includes one or more further operations, and / or omits one or more of the operations.

[0043] Figures 2A-2F is a schematic logic diagram of portions of an IC layout diagram with example paths according to some embodiments. Figure 2G is a schematic diagram illustrating various extracted features of paths in an IC layout diagram according to some embodiments.

[0044] Figure 2A1 is a schematic logic diagram of a portion 200A of an IC layout diagram having a path 1 according to some embodiments. Portion 200A includes a plurality of logic gates 201-204 and a plurality of networks (or wires) 205-210, which couple the logic gates 201-204 to each other and to two flip-flops FF1, FF2. For simplicity, it is assumed that each logic gate is a cell. Path 1 includes a network 205, a cell 201, a network 206, a cell 204, and a network 207 serially coupled between flip-flops FF1, FF2. In at least one embodiment, path 1 is identified in a timing report output from STA operation 140. Characteristics of path 1 include characteristics of the networks 205, 206, 207 in path 1 and characteristics of the cells 201, 204.

[0045] Example features of a network include, but are not limited to: "physical network length in metal layer", "total physical network length", "number of vias in a wire (or network)", "network delay", "slew-ratio", "layout shape", etc. The feature "physical network length in metal layer" represents the physical length of the portion of the network arranged in a metal layer (e.g., M0, M1, M2, etc.). The feature "total physical network length" represents the total physical length of the network in all metal layers in which the network is arranged. The feature "number of vias in a wire (or network)" represents the number of vias that couple different network portions in different metal layers together. The feature "network delay" represents the time delay of a signal traveling through the network due to the parasitic capacitance and parasitic resistance of the network. The feature "slew-ratio" represents how fast the leading or trailing edge of the signal rises or falls. The feature "layout shape" represents the shape of the network. Example shapes of a network include, but are not limited to, L-shape, I-shape, T-shape, etc. Other features of the network are within the scope of various embodiments.

[0046] Example features of a cell include, but are not limited to: "Drive Strength", "VT Type", "Number of Inputs", "Number of Outputs", "Functional Type", "Number of Transistors", "Height", "Pitch", "Layout Shape", "Sensitivity Delay", etc. The feature "Drive Strength" represents the designed load of the cell. The feature "VT Type" represents a type of threshold voltage (VT) at which the transistors in the cell are turned on or off. Example VT types include, but are not limited to: high threshold voltage (HVT), low threshold voltage (LVT), ultra-low threshold voltage (ULVT), standard threshold voltage (SVT). Generally, cells with lower threshold voltages are faster but consume more power than cells with higher threshold voltages. The feature "Number of Inputs" represents the number of inputs of the cell. The feature "Number of Outputs" represents the number of outputs of the cell. The feature "Functional Type" represents the logic type of the cell. Example logic types include, but are not limited to AOI (AND-OR-Inverted), AND, XOR, OR, NAND, NOR, INV (Inverted), etc. The feature "Number of Transistors" represents the number of transistors in the cell. The feature "Height" represents the height of the cell in the direction along the gate region of the transistors in the cell. The feature "Pitch" represents the spacing between adjacent gate regions. The feature "layout shape" represents the shape of the network within the cell. The feature "sensitivity delay" represents the time delay of a signal traveling through the cell. Other features of the cell are within the scope of various embodiments. Figure 2G Further example features of the paths are described.

[0047] Figure 2B is a schematic logic diagram of a portion 200B of an IC layout diagram having path 2 according to some embodiments. Figure 2B In the example configuration in , the physical network lengths of the networks 211-214 along path 2 in metal layer M3 are 50 units, 30 units, 100 units, and 200 units, respectively. The physical network lengths 211-214 in metal layer M3 are greater than the physical network lengths in other metal layers. That is, the networks 211-214 along path 2 are mainly arranged in metal layer M3, or path 2 is controlled by the networks in metal layer M3. Because the networks 211-214 are mainly arranged in metal layer M3, path 2 will be more affected by changes in metal layer M3 than other paths that are not controlled by metal layer M3. When there are changes in metal layer M3, small delays along the networks 211-214 in path 2 will accumulate into larger, more easily detected delays. In some embodiments as described herein, by determining the physical network lengths 211-214 in metal layer M3 based on primary features (e.g., metal layer M3 for path 2 or about Figure 2C-2G Another feature described herein) is that by routing packets and testing the paths of the packets, small delay defects (SDDs) can be identified and repaired.

[0048] Figure 2Cis a schematic logic diagram of a portion 200C of an IC layout diagram having path 3 according to some embodiments. Figure 2C In the example configuration of FIG. 3 , cells 215-218 are arranged along path 3. Cells 215, 216, 218 are configured from transistors with low threshold voltage (LVT), and cell 217 is configured from transistors with standard threshold voltage (SVT). In other words, the cells along path 3 are mainly configured as LVT cells, or path 3 is controlled by LVT cells.

[0049] Figure 2D is a schematic logic diagram of a portion 200D of an IC layout diagram having path 4 according to some embodiments. Figure 2D In the example configuration of , cells 219-221 are arranged along path 4. Each of cells 219-221 is configured to have three inputs. In other words, the cells along path 4 are mainly configured as 3-input cells, or path 4 is controlled by 3-input cells.

[0050] Figure 2E is a schematic logic diagram of a portion 200E of an IC layout diagram having path 5 according to some embodiments. Figure 2E In the example configuration of FIG. 5 , nets 222-226 are arranged along path 5. The number of vias in nets 222-226 is 5, 59, 137, 8, and 23, respectively. The total number of vias in the net of path 5 is greater than the average total number of vias in multiple paths of the IC layout. In other words, path 5 is dominated by the number of vias in the path.

[0051] Figure 2F is a schematic logic diagram of a portion 200F of an IC layout diagram having path 6 according to some embodiments. Figure 2F In the example configuration, the physical network lengths of the networks 227-230 arranged along path 6 in metal layer M5 are 121.3, 68.5, 259.4, and 97.6, respectively. The total physical network length of the network of path 6 in metal layer M5 is greater than that of other paths. In other words, path 6 is dominated by the physical network length in metal layer M5.

[0052] Figure 2G 2 is a schematic diagram of a feature list 200G illustrating various extracted features of a path in an IC layout diagram according to some embodiments. Feature list 200G is an example of a result of feature extraction operation 152. Feature list 200G includes one or more of timing features 240, logical features 250, and physical features 260. Feature list 200G is not exhaustive, and other features are within the scope of various embodiments.

[0053] One or more of the timing features 240 are obtained as a result of the STA operation 140, are included in the timing report 143 provided to the APST operation 150, and are then extracted from the timing report 143 by the feature extraction operation 152. An example characteristic is slack 241. The slack of a path is the amount of delay that can be tolerated in the path before violating the timing constraint. A negative value of slack indicates that the path has violated the timing constraint. A zero value of slack indicates that the IC corresponding to the IC layout diagram is operational, but there is no available time margin. A positive value of slack indicates that the IC can operate with a certain time margin. The IC design flow attempts to achieve positive or at least non-negative slack values ​​in all paths.

[0054] One or more of the timing features 240 are obtained from a library. One example is a library setup / hold time 242. The library setup / hold time 242 is a predetermined or known timing parameter of a cell and is retrieved from a library corresponding to the cell. In at least one embodiment, the library setup / hold time 242 is extracted from the library in a feature extraction operation 152. In one or more embodiments, in the STA operation 140, the library setup / hold time 242 is included in the timing report 143, which is then sent to the APST operation 150 to be extracted in the feature extraction operation 152.

[0055] One or more of logic features 250 are extracted from IC schematic 113 , such as a Verilog netlist.

[0056] One or more of physical features 260 are extracted from IC layout 123 , such as from one or more DEF and / or LEF files that include IC layout 123 .

[0057] Figure 3A is a flow chart of a process 300A in the feature encoding and reduction operation 153 according to some embodiments. The process 300A includes a first feature reduction operation 310, a feature encoding operation 320, and a second feature reduction operation 330.

[0058] In the first feature reduction operation 310, one or more features among the plurality of features extracted by the feature extraction operation 152 are removed based on data variations of features on a plurality of paths of the IC layout diagram. Figure 3B Describe the first feature simplification operation 310. In at least one embodiment, the first feature simplification operation 310 is omitted.

[0059] At the beginning of the feature encoding operation 320, the features remaining after the first feature simplification operation 310 are divided into numerical features 321 and categorical features 322. Numerical features are features with numerical values. Categorical features are features with non-numerical values. Example non-numerical values ​​include, but are not limited to, strings. Figure 3C An example of describing numerical features and categorical features. Because the numerical value of numerical feature 321 can be used for further calculations, numerical feature 321 is not subjected to one or more of the first to third encoding operations 323-325. In contrast, the non-numerical value of categorical feature 322 is not ready for further calculations and is converted or encoded in one or more of the first to third encoding operations 323-325 in feature encoding operation 320 to obtain a corresponding converted numerical value.

[0060] In a first encoding operation 323, a non-numeric value corresponding to a name of a pin or instance (e.g., from a netlist) is encoded or converted to a corresponding converted numeric value based on one or more hierarchical levels associated with the pin or instance, such as with respect to Figure 3C described.

[0061] In a second encoding operation 324, the non-numeric values ​​corresponding to the characteristics of the unit are separated into functional types and process parameters and encoded or converted to corresponding converted numeric values, such as Figure 3D described.

[0062] In a third encoding operation 325, a non-numeric value corresponding to another feature is encoded or converted to a corresponding converted numeric value using sequential encoding, such as with respect to Figure 3E described.

[0063] In the normalization operation 326 of the feature encoding operation 320, the numerical values ​​of the numerical features and the converted numerical values ​​of the categorical features are normalized, such as Figure 3F The operations described in feature encoding operation 320 are examples. Other arrangements for converting non-numeric values ​​to converted numeric values ​​are within the scope of various embodiments.

[0064] In a second feature reduction operation 330, based on the normalized values ​​output from the normalization operation 326, one or more features are further removed according to their correlation with tightness, such as Figure 3G As a result, a simplified feature set is obtained, such as Figure 3H described.

[0065] Figure 3B is a schematic data representation 300B of exemplary features in the first feature reduction operation 310 according to some embodiments. Figure 3BSchematic data representations of a limited number of exemplary features "slack", "clock uncertainty", "LVT cell", "net length", and "net area" are shown in the form of corresponding figures 311-315. The abscissa of each figure 311-315 represents the number of paths N in a plurality of paths of the IC layout diagram. The ordinate of each figure 311-315 represents the value of the corresponding feature for each of the N paths. The data representation is for illustrative purposes and is omitted in one or more embodiments.

[0066] In some embodiments, all features extracted by feature extraction operation 152 are analyzed to determine how the features vary across multiple paths of the IC layout diagram. Features that do not vary across N paths are removed from further analysis. For example, as shown in FIG. 312 , the value of “clock uncertainty” remains constant across N paths of the IC layout diagram. Therefore, “clock uncertainty” is removed from further analysis. Other example features “tightness,” “LVT cell,” “network length,” and “network area” have different values ​​across N paths, and these values ​​are maintained for further analysis. In at least one embodiment, features with incomplete information are also removed through further analysis.

[0067] In at least one embodiment, the described removal of one or more features based on data variation and / or information incompleteness is a simple method for reducing the number of features to be subjected to further analysis, thereby reducing computational workload.

[0068] Figure 3C 3 is a diagram of a table 300C including various numerical features 340 and classification features 345 having corresponding values ​​in several example paths_#1 to paths_#4 among N paths in an IC layout diagram according to some embodiments. The numerical features 340 include numerical features 341-344, which correspond to Figure 2C One or more of the timing characteristics 240. Figure 3C As shown, the numerical features 341-344 have numerical values ​​for each of the paths 1 to 4. In this example, the numerical values ​​of the numerical features 341-344 are delay times. The classification features 345 include classification features 346-348, which correspond to the Figure 2C One or more of the logical features 250. Figure 3C As shown, classification features 346-348 have non-numeric values ​​presented in the form of strings. In this example, the strings of classification features 346-348 represent pin or instance name, cell feature, and clock, respectively. Figure 3CThe feature list shown in is an example and is not exhaustive.

[0069] exist Figure 3C , to provide an example of the pin or instance name encoding in the first encoding operation 323. Each non-numeric value of the classification feature 346 indicates the name of the pin or instance of the corresponding path in path_#1 to path_#4. Each pin or instance name is presented in the form of a string containing one or more slash characters " / " to indicate the multiple hierarchical levels associated with the pin or instance. Figure 3C In the example configuration in , there are 9 hierarchical levels 349-357 in each non-numeric value of classification feature 346. Hierarchical level 349 is the highest level, followed by level 350, and so on, all the way to the lowest level 357. According to a predetermined encoding scheme, the string segments of each level in hierarchical levels 349-357 are encoded as numbers. For example, for all paths_#1 to path_#4, the string segment "u12_logic" of hierarchical level 355 is encoded as the number "1". Similarly, for all paths_#1 to path_#4, the string segments of each level in hierarchical levels 349-354 are encoded as the number "1". In hierarchical levels 356, 357, the string segments in path_#1 to path_#4 are different and are therefore encoded as different numbers. Specifically, in hierarchy level 356, the string segment "ucpu3_arb" is the same in path_#1 and path_#2 and is encoded as "21" in both paths_#1 and path_#2, while the string segment "uarb_1c" is the same in path_#3 and path_#4 and is encoded as "10" in both paths_#3 and path_#4. In hierarchy level 357, the string segment is the same in path_#1 and path_#2 and is encoded as "60" in both paths_#1 and path_#2, while the different string segments in paths_#3 and path_#4 are encoded as "40" and "50", respectively. As a result of the pin or instance name encoding operation 323, the non-numeric values ​​of the classification features 346 of path_#1 to path_#4 are encoded as corresponding converted numeric values ​​"11111112160", "1111111112160", "11111111040" and "11111111050", respectively. Figure 3F as shown in .

[0070] Figure 3D347, whose corresponding non-numeric values ​​are encoded in the second encoding operation 324, according to some embodiments. The classification feature 347 includes several features of a cell and is segmented into additional classification features 360, 361 that represent the cell function type and process parameters of the cell, respectively. Each non-numeric value or string of the classification feature 347 is also segmented into shorter segments corresponding to the classification features 360, 361. For example, the non-numeric value or string "DFRPQD4BWP300H8P63PDULVT" of the classification feature 347 is segmented into string segment 362 "DFRPQ", string segment 363 "D4", string segment 364 "BWP300H8P63PD", and string segment 365 "ULVT". The string segment 362 "DFRPQ" indicates that the cell function type is a flip-flop and is converted to the non-numeric value 366 "Flop" of the classification feature 360. The string segment 363 "D4" indicates the drive strength of the cell. Figure 3D In the example of , for simplicity, the drive strength is not further shown. However, it is within the scope of one or more embodiments to include this feature in further analysis. String segment 364 "BWP300H8P63PD" represents a process parameter and is converted to a non-numeric value 367 "BWP300H8P63P" of classification feature 361. String segment 365 "ULVT" represents the threshold voltage of the cell. Figure 3D In the example of , for simplicity, the threshold voltage is not further shown. However, it is within the scope of one or more embodiments to include this feature in further analysis. Similarly, for the first encoding operation 323, each of the non-numeric values ​​366, 367 is encoded as a number according to a predetermined encoding scheme. For example, the non-numeric value 366 "Flop" is encoded as a corresponding converted numeric value 368 "1", and the non-numeric value 367 "BWP300H8P63P" is encoded as a corresponding converted numeric value 369 "1". Other non-numeric values ​​of the classification feature 347 ( Figure 3D ) are similarly segmented and encoded into corresponding converted numerical values, Figure 3D Commonly indicated at 371.

[0071] Figure 3E 300E is a schematic diagram of a table 300E including a classification feature 348, the corresponding non-numeric value of which is encoded in the third encoding operation 325, according to some embodiments. Similarly, for the first encoding operation 323, each non-numeric value of the classification feature 348 is encoded as a number according to a predetermined encoding scheme (e.g., sequential encoding). For example, the non-numeric value "CA72_ACLK" is encoded as a corresponding converted numeric value "1". Other non-numeric values ​​of the classification feature 348 are also similarly encoded, such as Figure 3E shown.

[0072] Figure 3F is a diagram of a table 300F including various numerical features 340 and categorical features 345 having corresponding numerical values ​​and converted numerical values ​​in a standardization operation 326, according to some embodiments. Table 300F includes Figure 3F the numerical value of the numerical feature 340 collectively indicated at 372, and Figure 3F The converted numerical value of the categorical feature 345 is collectively indicated at 373. The numerical value 372 of the numerical feature 340 is the same as the corresponding numerical value in Table 300C. The converted numerical value 373 of the categorical feature 345 is obtained by encoding or converting the corresponding non-numeric value of the categorical feature 345 in the first to third encoding operations 323-325, as described with respect to Figure 3C-3E The numerical value 372 and the converted numerical value 373 are normalized to obtain the corresponding normalized value 380. For example, the numerical values ​​"0.000228", "0.007996", "0.005491", and "0.006957" of the numerical feature 341 (hereinafter referred to as feature LIB) are normalized to obtain the corresponding normalized values ​​"0.01502", "0.08514", "0.04104", and "0.05694".

[0073] As a result of the standardization operation 326, each feature has a plurality of standardized values ​​corresponding to the N paths of the IC layout diagram. For example, for path #_1 to path #_4, the feature LIB has standardized values ​​of "0.01502", "0.08514", "0.04104" and "0.05694". Similarly, for path #_1 to path #_4, the characteristic tightness also has a standardized value (not shown). In the second feature simplification operation 330, these two sets of standardized values ​​and tightness of the feature LIB are used to determine the correlation coefficient between the feature LIB and the tightness. In at least one embodiment, the reason for selecting tightness as the basic feature for determining the correlation with other features is that it is tested for timing verification and / or in one or more embodiments, the STA operation 140 is configured for tightness optimization. Basic features for determining correlation other than tightness are within the scope of various embodiments.

[0074] In some embodiments, the correlation coefficient is calculated using the following formula (1):

[0075]

[0076] Among them, r xy is the correlation coefficient, x i is the normalized value of the slack at the i-th path among the N paths in the IC layout diagram, yi is the normalized value of another feature (e.g., LIB) at the i-th path, is the average of all normalized values ​​of tightness on all N paths, and is the average of all normalized values ​​of LIB on all N paths. Similarly, the correlation coefficients between tightness and other features are calculated and Figure 3G Example results are given in .

[0077] Figure 3G is a diagram of a table 300G including various features having corresponding correlation coefficients in the second feature reduction operation 330 according to some embodiments. As shown at 391, in this example, the correlation coefficient between LIB and tightness on N paths of the IC layout diagram calculated as described herein is "0.178542". In table 300G, the correlation coefficients are sorted in descending order.

[0078] Remove the feature corresponding to the correlation coefficient in the predetermined range 393 from further analysis. In some embodiments, the predetermined range is between -0.15 and 0.15. The feature whose correlation coefficient is about zero in this predetermined range is considered to have little or no correlation with tightness. When there is a change in this characteristic, for example, the ViaCount (number of through holes in the path) indicated at 394, since the correlation between ViaCount and tightness is little or no correlation, it is unlikely to affect tightness. In other words, in this specific example, ViaCount is considered to have little or no significant impact on tightness and timing performance due to its low correlation with tightness. Therefore, feature ViaCount will be removed from further analysis. In at least one embodiment, this removal reduces the computational workload of further subsequent analysis. Other predetermined ranges for removing features that are considered to have little or no correlation with tightness are within the scope of various embodiments.

[0079] Features corresponding to correlation coefficients outside the predetermined range 393 are retained for further analysis. For example, features corresponding to correlation coefficients in ranges 395 and 396 that are respectively above and below the predetermined range 393 are retained for further analysis. Features corresponding to correlation coefficients in range 395 have a positive correlation with tightness, which means that when the value of one of these features increases, there is a possibility that tightness also increases. Features corresponding to correlation coefficients in range 396 have a negative correlation with tightness, which means that when the value of one of these features increases, there is a possibility that tightness decreases. Due to sufficient correlation with tightness, features corresponding to correlation coefficients in ranges 395, 396 are considered to have potential impact on tightness and timing performance. These features are retained for further analysis and together constitute a simplified feature set, an example of which is shown in FIG. Figure 3H Given in.

[0080] Figure 3H 3 is a schematic diagram showing a simplified set 300H of features of a path in an IC layout diagram according to some embodiments. The simplified set 300H lists the following features: Figure 2G 300H. However, features that have been removed based on data variation by the first feature simplification operation 310 and removed based on correlation with tightness by the second feature simplification operation 330 are indicated as stricken through in the simplified set 300H. The simplified set 300H is an example result of the feature encoding and simplification operation 153. In at least one embodiment, the encoding process in the feature encoding and simplification operation 153 enables the analysis of classification features in a manner similar to the numerical features described herein. In at least one embodiment, the feature simplification in the feature encoding and simplification operation 153 enables the removal of features that are unlikely to affect timing performance and reduces the computational workload.

[0081] Figure 4 4 is a flow chart of a process 400 in a feature clustering operation 154 and a cluster analysis and path grouping operation 155 according to some embodiments. The feature clustering operation 154 includes operations 410, 420, by which the paths of the IC layout are clustered or divided into a plurality of clusters. The cluster analysis and path grouping operation 155 includes operations 430, 440, 450, by which the clusters are analyzed and grouped into a plurality of groups having associated unique primary features.

[0082] At operation 410, the number of clusters into which the N paths of the IC layout diagram are to be divided is determined. In some embodiments, the number of clusters k is calculated using the following formula (2):

[0083]

[0084] At operation 420, a clustering algorithm is applied to cluster the N paths. In some embodiments, the clustering algorithm applied in operation 420 is K-means clustering. K-means clustering is used for unsupervised learning. Other clustering algorithms are within the scope of various embodiments.

[0085] The data used for K-means clustering includes a reduced set 300H of m features obtained as a result of the feature encoding and simplification operation 153, and the normalized values ​​of the m features in the N paths obtained as a result of the normalization operation 326. Each path is presented as a data point including m normalized values ​​of the m features. The purpose of K-means clustering is to cluster the N data points into k clusters S in an iterative process. 1 …S k , to minimize:

[0086]

[0087] In operation 430, the bias of each of the m features is calculated in each of the k clusters, for example, using the following formula:

[0088] CB nx =(CM nx -DS x ) / DS x (4)

[0089] Among them, CB nx is the bias of feature x in cluster n, CM nx is the average of feature x in the paths in cluster n, and DS x is the average value of feature x in all N paths.

[0090] In operation 440, a primary feature is determined for each cluster based on the bias of each feature in each cluster calculated in operation 430. For example, for each cluster n, when If the threshold value X is greater than a predetermined threshold value X, cluster n is biased toward feature x, and feature x is determined to be the main feature of cluster n. In some embodiments, the threshold value X used to determine whether cluster n is biased toward feature x is a value from 40% to 60%. Any other value of the threshold value X is within the scope of various embodiments. For example, in one or more embodiments, the threshold value X is 70%, 85%, or 90%. In at least one embodiment where the threshold value X is greater than 50%, there is a condition that satisfies the condition in the cluster. In at least one embodiment where the threshold is 50% or lower, it is possible that more than one feature in the cluster satisfies the condition In such cases, clusters are determined to be dominated by more than one feature.

[0091] When there is no cluster with a value greater than a predefined threshold X for feature x When The cluster with feature x as the main feature is determined. This determination is made even if the cluster with the largest This may also apply when a cluster has been identified as having a primary feature other than feature x. It is within the scope of one or more embodiments that a cluster has more than one primary feature. It is also within the scope of one or more embodiments that a feature is identified as a primary feature of more than one cluster.

[0092] As a result of operation 440 , each of the k clusters has at least one main feature that is one of the m features, and each of the m features is determined to be a main feature of at least one of the k clusters.

[0093] In operation 450, m path groups are created from the k clusters so that each group has a unique main feature that is different from the main features of other groups. For example, when the first feature is determined to be the main feature of only one cluster among the k clusters, the cluster is designated as a group having the first feature as the main feature. In addition, when the second feature is determined to be the main feature of more than one cluster among the k clusters, such clusters are merged together into a group having the second feature as the main feature. In some embodiments, each path is included in a group, thereby generating multiple non-overlapping groups. In another example, in the case where a cluster has been determined to have several main features, the cluster is merged into several groups corresponding to the several main features. As a result, at least one embodiment includes a potential situation where a path is included in more than one group.

[0094] In some embodiments, as a result of operation 450 of cluster analysis and path grouping operation 155, N paths of the IC layout diagram are grouped into m groups having m different primary features, each primary feature corresponding to one of the m features in the reduced set 300H of features obtained by feature encoding and simplification operation 153. The primary features of a group are the features that control the paths in the group, such as Figure 2B-2F For example, as Figure 2B As described above, the paths in the group having the metal layer M3 as the main feature are controlled by the metal layer M3.

[0095] like Figure 4 As shown, after operation 450 of the cluster analysis and path grouping operation 155, the process proceeds to ATPG operation 156, where one or more ATPG methods or algorithms are used to generate test patterns for one or more paths in each group for which a primary feature has been assigned. A specific example of a group having metal layer M3 as a primary feature is described herein.

[0096] Specifically, the paths in the group having the metal layer M3 as the main feature are identified in the report (e.g., a netlist) from the cluster analysis and path grouping operation 155 to the ATPG operation 156 for subsequent testing. In practice, not all paths in the group are testable because the number of paths is too large or the specific properties of the paths make the paths untestable. For all testable paths in the group, the ATPG operation 156 generates corresponding test patterns. The generated test patterns vary from path to path, for example, depending on the type and / or number of cells or gates on the path, the test strategy, or the ATPG method or algorithm used to generate the test patterns. An example ATPG strategy used in one or more embodiments is path delay ATPG for generating robust and non-robust path delay test patterns. As described herein with respect to Figure 1 As described above, the generated test patterns are used for simulation of IC design verification prior to manufacturing and / or for ATE testing of the actually manufactured IC.

[0097] When one of the paths fails the test, since the APST operation 150 identifies the failed path as belonging to a group having a main feature of metal layer M3, in one or more embodiments, a correction strategy associated with the main feature (i.e., metal layer M3) can be selected to repair or improve the timing performance of the failed path. In at least one embodiment, it is expected that such a correction strategy associated with metal layer M3 will also improve the performance of other paths in the same group controlled by metal layer M3. As a result, in some embodiments, a single correction strategy can be used to target or improve multiple paths, thereby saving time and effort in the IC design and / or manufacturing process. The above advantages can be achieved not only in simulations before signing off manufacturing, or when testing the actual manufacturing of integrated circuits, but also at an earlier stage. For example, in at least one embodiment, a strategy for repairing timing problems discovered by the STA operation 140 is defined based on an identified group of paths having a specified main feature.

[0098] There are several methods to repair or improve the faulty path based on the identified primary features of the path. In the example with metal layer M3 as the primary feature, a strategy according to some embodiments is to reroute at least a portion of the faulty path in a different metal layer. Another strategy is to adjust the manufacturing process to improve the formation of interconnects in metal layer M3 and / or other metal layers surrounding metal layer M3. Other correction strategies are within the scope of various embodiments. The advantages described are not limited to the specific example with metal layer M3 as the primary feature. Similar advantages can be obtained in one or more embodiments with respect to paths and groups having other primary features, such as with respect to Figure 2G or as described in 3H.

[0099] Compared to other methods, in some embodiments, more paths to be tested can be identified, thereby increasing the likelihood of locating and correcting small delay defects (SDD) while covering a wide range of potential causes of SDD. As described herein, SDD involves small delay variations caused by various factors, including but not limited to manufacturing process variations, power supply noise, crosstalk, etc. In some cases, although the delays of individual cells or networks are small and within specifications, the cumulative delay of multiple such small delays (especially on long paths) may be large enough to cause failures. To detect potential SDD failures, other methods select and test the most critical paths, i.e., the longest paths and / or the paths with the smallest slack based on STA timing reports. This approach focuses on a very narrow range of issues and may result in a small number of paths being selected for testing and / or being tested without providing sufficient coverage for the various causes of SDD.

[0100] In contrast, in one or more embodiments, because the paths identified for testing involve a wide range of features, such as Figure 2G and 3H As described above, a greater number of paths are ultimately tested, while covering various potential causes of SDD. At the same time, critical paths covered by other methods are covered in one or more embodiments, which include one or more groups of paths whose main feature is timing characteristics (including tightness).

[0101] In at least one embodiment, the broad coverage of potential causes of SDD enables the location and repair of various systematic defects, which are one of the main challenges in advanced process nodes. Other methods lack this capability. In some embodiments, additional advantages include but are not limited to distributed process defect coverage of SDD, the ability to target any specific feature and / or process problem, and process node independence.

[0102] Figure 5 is a flow chart of method 500 according to some embodiments. In at least one embodiment, method 500 is performed in whole or in part by a processor as described herein.

[0103] At operation 505, a plurality of features of a plurality of paths in an integrated circuit (IC) layout are extracted. For example, features are extracted from at least one of a Verilog netlist containing an IC schematic corresponding to the IC layout, one or more DEF and / or LEF files containing the IC layout, a timing report of an STA, or a library, such as the features of the plurality of paths in the integrated circuit (IC) layout. Figure 2G described.

[0104] In operation 510, based on the correlation coefficient between at least one feature on the multiple paths and the tightness and / or based on at least one feature that has not changed, at least one feature is removed from the multiple features to obtain a simplified feature set. For example, the correlation coefficient between each feature on the multiple paths and the tightness is calculated, such as Figure 3G In response to the correlation coefficient of one or more features being within a predetermined range, one or more features are removed from the plurality of features, thereby obtaining a simplified feature set, such as Figure 3H For example, in at least one embodiment, when all features have changes and the correlation coefficients of all features on multiple paths with tightness are about Figure 3G When it is outside the predetermined range described, operation 510 is omitted.

[0105] At operation 515, the plurality of paths are clustered into a plurality of clusters. For example, a clustering algorithm is applied to divide the plurality of paths into a plurality of clusters, such as Figure 4 The feature clustering operation 154 is described in detail.

[0106] In operation 520, the features included in the reduced feature set are determined as the main features of each cluster among the plurality of clusters. Figure 4 As described above, a primary feature is determined for each cluster. For example, a primary feature is a feature that controls the paths in a cluster, such as Figure 2B-2F described.

[0107] In operation 525, each cluster having a main feature different from the main features of other clusters is designated as a path group among a plurality of path groups to be created from the plurality of clusters, for example, as described with respect to Figure 4 As described in operation 450 in .

[0108] In operation 530, clusters having the same main features are merged to obtain another group of the plurality of groups, for example, as described with respect to Figure 4 As described in operation 450 in .

[0109] In operation 535 , a plurality of path groups are created from the plurality of paths in the IC layout diagram, wherein each group has a main feature among the plurality of features of the plurality of paths, and the main features of the plurality of groups are different from each other, for example, as a result of operations 525 , 530 .

[0110] At operation 540, at least one test pattern is generated for at least one path in each of the plurality of groups. For example, automatic test pattern generation (ATPG) is performed to generate at least one test pattern, such as Figure 4 The ATPG operation 156 is described in detail.

[0111] At operation 545, at least one path in a group of the plurality of groups is tested. For example, by testing the at least one path using the generated at least one test pattern in a simulation or by ATE, as described with respect to Figure 1 The test operation 160 is described in detail.

[0112] At operation 550, in response to the test indicating that at least one path failed, at least one of the IC layout, at least a portion of at least one library having cells included in the IC layout, or a manufacturing process for manufacturing an IC corresponding to the IC layout is modified. For example, when a path fails, one or more corrections are made to at least one of the IC design, library, or manufacturing process, such as with respect to Figure 1 The modification operation 170 is described in detail.

[0113] In at least one embodiment, all operations 505-550 are performed automatically without user input or intervention.

[0114] The method includes example operations, but does not necessarily require that the example operations be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations can be appropriately added, replaced, the order of operations can be changed, and / or operations can be eliminated. Embodiments combining different features and / or different embodiments are within the scope of the present disclosure and will be apparent to those of ordinary skill in the art after reviewing the present disclosure.

[0115] In some embodiments, at least one (or more) of the methods discussed above are performed in whole or in part by at least one EDA system. In some embodiments, the EDA system may be used as part of a design room of an IC manufacturing system discussed below.

[0116] Figure 6 is a block diagram of an electronic design automation (EDA) system 600 according to some embodiments.

[0117] In some embodiments, the EDA system 600 includes an APR system. The methods of designing floorplans described herein represent routing arrangements according to one or more embodiments that are implementable using the EDA system 600 , for example, according to some embodiments.

[0118] In some embodiments, EDA system 600 is a general purpose computing device including a hardware processor 602 and a non-transitory computer-readable storage medium 604. Storage medium 604 is encoded with, i.e., stores, computer program code 606 (i.e., a set of executable instructions), among other things. Execution of instructions 606 by hardware processor 602 represents (at least in part) an EDA tool that implements some or all of the methods described herein (hereinafter, the processes and / or methods) according to one or more embodiments.

[0119] The processor 602 is electrically coupled to the computer readable storage medium 604 via a bus 608. The processor 602 is also electrically coupled to an I / O interface 610 via the bus 608. A network interface 612 is also electrically connected to the processor 602 via the bus 608. The network interface 612 is connected to a network 614 so that the processor 602 and the computer readable storage medium 604 can be connected to external elements via the network 614. The processor 602 is configured to execute a computer program code 606 encoded in the computer readable storage medium 604 so that the system 600 can be used to perform part or all of the described processes and / or methods. In one or more embodiments, the processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0120] In one or more embodiments, the computer-readable storage medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 604 includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), hard disk, and / or magnetic disk. In one or more embodiments using optical disks, the computer-readable storage medium 604 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0121] In one or more embodiments, the storage medium 604 stores computer program code 606 configured to enable the system 600 (where such execution represents (at least in part) an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, the storage medium 604 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, the storage medium 604 stores a library 607 of standard cells including such standard cells disclosed herein.

[0122] The EDA system 600 includes an I / O interface 610. The I / O interface 610 is coupled to an external circuit. In one or more embodiments, the I / O interface 610 includes a keyboard, a key, a mouse, a trackball, a touch pad, a touch screen, and / or cursor direction keys for transmitting information and commands to the processor 602.

[0123] The EDA system 600 also includes a network interface 612 coupled to the processor 602. The network interface 612 allows the system 600 to communicate with a network 614 to which one or more other computer systems are connected. The network interface 612 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 600.

[0124] The system 600 is configured to receive information through the I / O interface 610. The information received through the I / O interface 610 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 602. The information is transmitted to the processor 602 via the bus 608. The EDA system 600 is configured to receive information related to the UI through the I / O interface 610. The information is stored in the computer readable medium 604 through the user interface (UI) 642.

[0125] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 600. In some embodiments, the system is implemented using a software application provided by CADENCE DESIGN SYSTEMS. A tool such as or another suitable layout generation tool generates a layout diagram including standard cells.

[0126] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or storage units, such as one or more of an optical disk (e.g., DVD), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., ROM, RAM, a memory card, etc.).

[0127] Figure 7is a block diagram of an integrated circuit (IC) manufacturing system 700 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 700 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0128] exist Figure 7 In the embodiment, IC manufacturing system 700 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 760, such as design room 720, mask room 730 and IC manufacturer / fabricator ("fab") 750. The entities in system 700 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of design room 720, mask room 730 and IC fab 750 are owned by a single larger company. In some embodiments, two or more of design room 720, mask room 730 and IC fab 750 coexist in a public facility and use public resources.

[0129] The design office (or design team) 720 generates an IC design layout diagram 722. The IC design layout diagram 722 includes various geometric patterns designed for the IC device 760. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components constituting the IC device 760 to be manufactured. The layers are combined to form various integrated circuit features. For example, a portion of the IC design layout diagram 722 includes various IC features, such as active areas, gate electrodes, source and drain electrodes, metal lines or through holes for interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 720 implements an appropriate design program to form the IC design layout diagram 722. The design program includes one or more of a logic design, a physical design, or a layout and routing operation. The IC design layout diagram 722 is presented in one or more data files with geometric pattern information. For example, the IC design layout diagram 722 can be represented in a GDSII file format or a DFII file format.

[0130] The mask chamber 730 includes data preparation 732 and mask manufacturing 744. The mask chamber 730 uses the IC design layout drawing 722 to manufacture one or more masks 745 for manufacturing various layers of the IC device 760 based on the IC design layout drawing 722. The mask chamber 730 performs mask data preparation 732, wherein the IC design layout drawing 722 is converted into a representative data file ("RDF"). The mask data preparation 732 provides the RDF to the mask manufacturing 744. The mask manufacturing 744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 745 or a semiconductor wafer 753. The design layout drawing 722 is manipulated by the mask data preparation 732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 750. In Figure 7 , mask data preparation 732 and mask fabrication 744 are shown as separate elements. In some embodiments, mask data preparation 732 and mask fabrication 744 may be collectively referred to as mask data preparation.

[0131] In some embodiments, mask data preparation 732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as those caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 722. In some embodiments, mask data preparation 732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0132] In some embodiments, mask data preparation 732 includes a mask rule checker (MRC) that checks an IC design layout 722 that has been processed in an OPC, where a set of mask creation rules contain certain geometry and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 722 to compensate for the constraints during mask fabrication 744, which may undo portions of the modifications performed by the OPC to satisfy the mask creation rules.

[0133] In some embodiments, mask data preparation 732 includes a lithography process check (LPC), which simulates the process to be implemented by IC fab750 to manufacture IC device 760. LPC simulates the process based on IC design layout diagram 722 to create a simulated manufactured device, such as IC device 760. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the simulated manufactured device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further improve the IC design layout diagram 722.

[0134] It should be understood that the above description of mask data preparation 732 is simplified for the sake of clarity. In some embodiments, data preparation 732 includes additional features such as logic operations (LOPs) to modify IC design layout 722 according to manufacturing rules. In addition, the processes applied to IC design layout 722 during data preparation 732 can be performed in a variety of different orders.

[0135] After the mask data preparation 732 and during the mask manufacturing 744, a mask 745 or a set of masks 745 is manufactured based on the modified IC design layout 722. In some embodiments, the mask manufacturing 744 includes performing one or more photolithography exposures based on the IC design layout 722. In some embodiments, based on the modified IC design layout 722, a pattern is formed on the mask (photomask or reticle) 745 using an electron beam (e-beam) or a plurality of e-beam mechanisms. The mask 745 can be formed using various techniques. In some embodiments, the mask 745 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque region and a transparent region. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque region and passes through the transparent region. In one example, a binary mask version of the mask 745 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque region of the binary mask. In another example, a mask 745 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 745, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The (one or more) masks generated by the mask manufacturing 744 are used in various processes. For example, such (one or more) masks are used in an ion implantation process to form various doped regions in the semiconductor wafer 753, in an etching process to form various etching regions in the semiconductor wafer 753, and / or in other suitable processes.

[0136] IC fab 750 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Fab 750 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end of line (FEOL) process) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services for the foundry enterprise.

[0137] IC fab 750 includes fabrication tool 752 configured to perform various fabrication operations on semiconductor wafer 753 such that IC device 760 is fabricated according to mask(s), such as mask 745. In various embodiments, fabrication tool 752 includes one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes described herein.

[0138] IC fab 750 uses (one or more) masks 745 manufactured by mask chamber 730 to manufacture IC device 760. Therefore, IC fab 750 uses IC design layout diagram 722 at least indirectly to manufacture IC device 760. In some embodiments, semiconductor wafer 753 is manufactured by IC fab 750 using (one or more) masks 745 to form IC device 760. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout diagram 722 at least indirectly. Semiconductor wafer 753 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 753 also includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0139] With respect to integrated circuit (IC) manufacturing systems (e.g., Figure 7 Detailed information of the system 700 and the IC manufacturing process associated therewith are found in the following patents: for example, U.S. Patent No. 9,256,709 issued on February 9, 2016, U.S. Pregrant Publication No. 20150278429 published on October 1, 2015, U.S. Pregrant Publication No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, each of which is incorporated herein by reference in its entirety.

[0140] In some embodiments, a method is performed at least in part by a processor, the method comprising creating multiple groups of paths from multiple paths in an integrated circuit (IC) layout diagram. Each group in the multiple groups has a main feature among multiple features of the multiple paths. The main features of the multiple groups are different from each other. The method also includes testing at least one path in one of the multiple groups. The method also includes modifying at least one of the following items in response to the test indicating that the at least one path has not passed: the IC layout diagram, at least a portion of at least one library of cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0141] In some embodiments, a system includes a processor. The processor is configured to extract multiple features of multiple paths in an integrated circuit (IC) layout diagram. The processor is also configured to cluster the multiple paths into multiple clusters. The processor is also configured to determine the main features of each cluster for each of the multiple clusters, and the main features are included in the multiple features. The processor is also configured to create multiple groups of paths from the multiple clusters based on the main features of the multiple clusters, and each group among the multiple groups has a unique main feature among the main features. The processor is also configured to perform automatic test pattern generation (ATPG) to generate at least one test pattern for each of the multiple groups, and perform a test on at least one path in each group using the generated at least one test pattern. The processor is also configured to modify at least one of the following items in response to the test indicating that the at least one path has not passed: the IC layout diagram, at least a portion of at least one library having a cell included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0142] In some embodiments, a computer program product includes a non-state computer-readable medium, including instructions. When the instructions are executed by a processor, the processor performs the following operations: creating multiple groups of paths from multiple paths in an integrated circuit (IC) layout diagram by clustering the multiple paths into multiple clusters, determining a main feature for each cluster among the multiple clusters, the main feature being included in the multiple features of the multiple paths; designating each cluster having a main feature different from the main feature of other clusters as one of the multiple groups; and merging clusters having the same main feature to obtain another group in the multiple groups. When the instructions are executed by the processor, the processor also performs a test on at least one path in one of the multiple groups, and in response to the at least one path failing the test, modifies at least one of the following items: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0143] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0144] Example 1. A method for integrated circuit design, the method being at least partially performed by a processor, the method comprising: creating multiple groups of paths from multiple paths in an integrated circuit (IC) layout diagram, wherein each of the multiple groups has a main feature among multiple features of the multiple paths, and the main features of the multiple groups are different from each other; testing at least one path in one of the multiple groups; and in response to the test indicating that the at least one path has failed, modifying at least one of the following: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0145] Example 2. The method of example 1, wherein the modifying not only changes the at least one path that fails the test, but also changes other paths in the same group as the at least one path.

[0146] Example 3. The method of Example 1 further comprises: generating at least one test pattern for the at least one path in the group, wherein the testing comprises testing the at least one path using the generated at least one test pattern.

[0147] Example 4. A method according to Example 1, wherein: the multiple features include at least one of the following: one or more timing features in a timing report of a static timing analysis (STA) of the IC layout drawing, one or more logical features in an IC schematic corresponding to the IC layout drawing, or one or more physical features of components in the IC layout drawing.

[0148] Example 5. The method according to Example 1 further includes: removing at least one feature from the plurality of features to obtain a simplified feature set including the main features of the plurality of groups.

[0149] Example 6. The method of Example 5, wherein: in the removing, at least one feature removed includes a feature that does not vary over the plurality of paths.

[0150] Example 7. The method according to Example 5 further includes: for each feature among the multiple features, determining a correlation coefficient between: the value of the feature in the multiple paths, and the value of the tightness in the multiple paths, wherein, in the removal, at least one feature removed includes a feature having a correlation coefficient within a predetermined range.

[0151] Example 8. A method according to Example 7, wherein: the multiple features include: numerical features with numerical values, and categorical features with non-numerical values, and the method further includes: converting the non-numerical values ​​of the categorical features into converted numerical values; standardizing the numerical values ​​of the numerical features and the converted numerical values ​​of the categorical features; and using the standardized values ​​to determine the correlation coefficient between tightness and each of the multiple features.

[0152] Example 9. A method according to Example 8, wherein: the classification features include: a pin name or an instance name, in which, based on a hierarchical level associated with the pin name or the instance name, the pin name or the instance name is converted into a corresponding conversion numerical value, a unit feature, in which, the unit feature is segmented into a unit function type and a process parameter, and then the unit function type and the process parameters are converted into corresponding conversion numerical values, and other features, in which, using sequential encoding, the other features are converted into corresponding conversion numerical values.

[0153] Example 10. A method according to Example 1, wherein: creating the multiple groups includes: clustering the multiple paths into multiple clusters, determining the main feature for each of the multiple clusters, and, among the multiple clusters, designating each cluster having a main feature different from the main features of other clusters as one of the multiple groups, and merging clusters having the same main feature to obtain another group among the multiple groups.

[0154] Example 11. The method according to Example 10, wherein: determining the main feature for each cluster among the plurality of clusters comprises: calculating CB nx =(CM nx -DS x ) / DS x , where CB nx is the bias of feature x in cluster n, CM nx is the average of feature x in the paths in cluster n, and DS x is the average of the feature x in multiple paths, and responds to is greater than a predetermined threshold, determining that feature x is the main feature of cluster n, wherein the plurality of features includes m features.

[0155] Example 12. The method of Example 11, wherein: determining the main feature for each cluster among the plurality of clusters further comprises: in response to no cluster having a value greater than the predetermined threshold Assign feature x to the feature with maximum The main characteristics of the cluster.

[0156] Example 13. The method according to Example 10, wherein: the clustering includes K-means clustering.

[0157] Example 14. A system for integrated circuit design, comprising a processor, wherein the processor is configured to: extract multiple features of multiple paths in an integrated circuit IC layout diagram, cluster the multiple paths into multiple clusters, determine, for each of the multiple clusters, a main feature of the each cluster, the main feature being included in the multiple features, create multiple groups of paths from the multiple clusters based on the main features of the multiple clusters, each of the multiple groups having a unique main feature among the main features, for each of the multiple groups, perform automatic test pattern generation ATPG to generate at least one test pattern, perform a test on at least one path in each group using the generated at least one test pattern, and in response to the test indicating that the at least one path has failed, modify at least one of the following: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0158] Example 15. A system according to Example 14, wherein: the processor is configured to extract the multiple features as: one or more timing features of a timing report of a static timing analysis (STA) of the IC layout drawing, one or more logical features of an IC schematic corresponding to the IC layout drawing, and one or more physical characteristics of components in the IC layout drawing.

[0159] Example 16. The system of Example 14, wherein: the processor is configured to remove features from the plurality of features that do not vary over the plurality of paths.

[0160] Example 17. A system according to Example 14, wherein: the multiple features include: numerical features having numerical values, and categorical features having non-numerical values, and the processor is further configured to: convert the non-numerical values ​​of the categorical features into converted numerical values; standardize the numerical values ​​of the numerical features and the converted numerical values ​​of the categorical features; use the standardized values ​​to determine the correlation coefficient between the tightness and the multiple features; and remove features having the correlation coefficient within a predetermined range from the multiple features.

[0161] Example 18. A computer program product, comprising a non-transitory computer-readable medium, including instructions that, when executed by a processor, cause the processor to perform the following operations: create multiple groups of paths from multiple paths in an integrated circuit (IC) layout diagram by clustering the multiple paths into multiple clusters, determining a main feature for each of the multiple clusters, the main feature being included in the multiple features of the multiple paths, designating each cluster having a main feature different from the main feature of other clusters as one of the multiple groups, and merging clusters having the same main feature to obtain another group of the multiple groups; performing a test on at least one path in one of the multiple groups; and in response to the at least one path failing the test, modifying at least one of the following: the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

[0162] Example 19. The computer program product of Example 18, wherein the instructions, when executed by the processor, further cause the processor to: determine the main feature for each of the plurality of clusters by: calculating CB nx =(CM nx -DS x ) / DS x , where CB nx is the bias of feature x in cluster n, CM nx is the average of feature x in the paths in cluster n, and DS x is the average of the feature x in multiple paths, and responds to is greater than a predetermined threshold, determining that feature x is a main feature of cluster n, wherein the plurality of features includes m features, and in response to no cluster having a feature x greater than the predetermined threshold Assign feature x to the feature with maximum The main characteristics of the cluster.

[0163] Example 20. The computer program product of Example 18, wherein the instructions, when executed by the processor, further cause the processor to: perform K-means clustering to cluster the plurality of paths into the plurality of clusters.

Claims

1. A method for integrated circuit design, the method being at least partially performed by a processor, the method include: A plurality of groups of paths are created from a plurality of paths in an integrated circuit IC layout diagram, wherein Each of the plurality of groups has a main feature among the plurality of features of the plurality of paths, and The main features of the plurality of groups are different from each other; testing at least one path in one of the plurality of groups; and In response to the test indicating that the at least one path has failed, modifying at least one of the following: The IC layout diagram, having at least a portion of at least one library of cells included in the IC layout, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram, The method further comprises: removing at least one feature from the plurality of features to obtain a simplified feature set including the plurality of groups of main features.

2. The method according to claim 1, wherein The modification not only changes the at least one path that fails the test, but also changes other paths in the same group as the at least one path.

3. The method according to claim 1, further comprising: include: generating at least one test pattern for the at least one path in the group, The testing includes testing the at least one path using the generated at least one test pattern.

4. The method according to claim 1, in: The plurality of features include at least one of the following: One or more timing features in the timing report of the static timing analysis STA of the IC layout diagram, One or more logic features in an IC schematic corresponding to the IC layout, or One or more physical features of a component in the IC layout.

5. The method according to claim 1, in: In the removing, the at least one feature removed includes a feature that does not vary over the plurality of paths.

6. The method according to claim 1, further comprising: include: For each feature among the plurality of features, a correlation coefficient is determined between: the values ​​of the feature in the plurality of paths, and The values ​​of tightness in the plurality of paths, Wherein, in the removing, at least one feature removed includes a feature having a correlation coefficient within a predetermined range.

7. The method according to claim 6, in: The features include: Numeric features with numeric values, and Categorical features with non-numeric values, The method further comprises: Converting the non-numeric value of the categorical feature into a converted numeric value; normalizing the numerical values ​​of the numerical features and the transformed numerical values ​​of the categorical features; and A correlation coefficient between tightness and each of the plurality of features is determined using the normalized values.

8. The method according to claim 7, in: The classification features include: a pin name or an instance name, wherein the pin name or the instance name is converted to a corresponding converted numeric value based on a hierarchical level associated with the pin name or the instance name, unit characteristics, in which the unit characteristics are split into unit function types and process parameters, and then the unit function types and the process parameters are converted into corresponding converted numerical values, and Other features, in the conversion, use sequential encoding, and the other features are converted into corresponding conversion numerical values.

9. The method according to claim 1, in: Creating the plurality of groups includes: clustering the plurality of paths into a plurality of clusters, determining the primary feature for each of the plurality of clusters, and In the plurality of clusters, designating each cluster having a primary characteristic different from the primary characteristics of the other clusters as one of the plurality of groups, and Clusters having the same main feature are merged to obtain another group of the plurality of groups.

10. The method according to claim 9, in: Determining the main feature for each of the plurality of clusters includes: Calculate CB nx =(CM nx -DS x ) / DS x , in, CB nx is the bias of feature x in cluster n, CM nx is the mean of feature x in the paths in cluster n, and DS x is the average of feature x across multiple paths, and In response to is greater than a predetermined threshold, determining that feature x is the main feature of cluster n, wherein the plurality of features includes m features.

11. The method according to claim 10, in: Determining the main feature for each cluster among the plurality of clusters further comprises: In response to no cluster having a value greater than the predetermined threshold Assign feature x to the feature with maximum The main characteristics of the cluster.

12. The method according to claim 9, in: The clustering includes K-means clustering.

13. A system for integrated circuit design, comprising a processor, wherein the processor is configured to: Extract multiple features of multiple paths in the integrated circuit IC layout diagram, clustering the plurality of paths into a plurality of clusters, For each cluster among the plurality of clusters, calculating a bias for each of the plurality of features, and determining a main feature of each cluster based on the calculated bias of each feature in the plurality of features, the main feature being included in the plurality of features, creating a plurality of groups of paths from the plurality of clusters based on the primary features of the plurality of clusters, each group among the plurality of groups having a unique primary feature of the primary features, For each group among the plurality of groups, performing automatic test pattern generation ATPG to generate at least one test pattern, performing a test on at least one path in each of the groups using the generated at least one test pattern, and In response to the test indicating that the at least one path has failed, causing at least one of the following to be modified: The IC layout diagram, having at least a portion of at least one library of cells included in the IC layout, or A manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

14. The system according to claim 13, in: The processor is configured to extract the plurality of features as: One or more timing characteristics of the timing report of the static timing analysis STA of the IC layout diagram, one or more logical features of an IC schematic corresponding to the IC layout, and One or more physical characteristics of components in the IC layout.

15. The system according to claim 13, in: The processor is configured to remove features from the plurality of features that do not vary over the plurality of paths.

16. The system according to claim 13, in: The features include: Numeric features with numeric values, and Categorical features with non-numeric values, The processor is further configured to: Converting the non-numeric value of the categorical feature into a converted numeric value; normalizing the numerical values ​​of the numerical features and the converted numerical values ​​of the categorical features; Determining a correlation coefficient between tightness and the plurality of features using the normalized values; and Features having the correlation coefficient within a predetermined range are removed from the plurality of features.

17. A computer program product comprising a non-transitory computer readable medium comprising instructions which, when executed by a processor, cause the processor to: Create multiple groups of paths from multiple paths in an integrated circuit IC layout by the following operations: clustering the plurality of paths into a plurality of clusters, A main feature is determined for each cluster among the plurality of clusters, the main feature being included in a plurality of features of the plurality of paths, the plurality of features comprising at least one of the following: The physical size of at least one element in the IC layout, or the tightness of the multiple paths, designating each cluster having a primary characteristic different from the primary characteristics of the other clusters as one of the plurality of groups, and merging clusters having the same primary characteristic to obtain another group of the plurality of groups; performing a test on at least one path in one of the plurality of groups; and in response to the at least one path failing the test, modifying at least one of the following: The IC layout diagram, having at least a portion of at least one library of cells included in the IC layout, or A manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

18. The computer program product according to claim 17, in, When the instructions are executed by the processor, the processor further causes the processor to: The main feature is determined for each cluster among the plurality of clusters by: Calculate CB nx =(CM nx -DS x ) / DS x , in, CB nx is the bias of feature x in cluster n, CM nx is the mean of feature x in the paths in cluster n, and DS x is the average of feature x across multiple paths, and In response to is greater than a predetermined threshold, determining that feature x is the main feature of cluster n, wherein the plurality of features includes m features, and In response to no cluster having a value greater than the predetermined threshold Assign feature x to the feature with maximum The main characteristics of the cluster.

19. The computer program product according to claim 17, in, When the instructions are executed by the processor, the processor further causes the processor to: K-means clustering is performed to cluster the plurality of paths into the plurality of clusters.

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