Chip interconnect packaging structure and chip interconnect packaging method

Abstract

The present invention provides a chip interconnect packaging structure and a chip interconnect packaging method, wherein a first plastic encapsulation layer is formed to encapsulate a first chip, and a groove is formed on a side of the first plastic encapsulation layer close to the front surface of the first chip; a first redistribution layer is formed at least on the bottom and side surfaces of the groove, and after a second chip is placed on the first redistribution layer on the bottom surface of the groove, the back surface of the second chip is electrically connected to the first redistribution layer; a second redistribution layer is formed on a first pad on the front surface of the first chip, a second pad on the front surface of the second chip, the first redistribution layer, and the second plastic encapsulation layer, and the first pad and the first redistribution layer are electrically connected via the second redistribution layer, so that the front surface of the first chip is electrically connected to the back surface of the second chip via the second redistribution layer and the first redistribution layer. The technical solution of the present invention can not only realize double-sided chip interconnection, but also improve the problems of deformation of the packaged product, high production cost, and limited chip quantity.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip interconnection packaging structure and a chip interconnection packaging method. Background Art

[0002] Double-sided interconnect packaging is to attach the back of the chip to the lead frame and rewire the front of the chip. Through rewiring, the front of the chip on one lead frame is connected to the other adjacent lead frame, thereby connecting the front of the chip on one lead frame to the back of the chip on the other adjacent lead frame, thereby achieving double-sided interconnection.

[0003] See Figure 1 The back of the chip 12 is attached to the lead frame 11 using conductive adhesive 13, and a redistribution layer is formed on the front of the chip 12. The redistribution layer includes multiple copper pillars 14 formed on the front of the chip 12 and copper wires 15 electrically connected to the copper pillars 14. The plastic encapsulation layer 16 encapsulates the lead frame 11, chip 12, adhesive layer 13, copper pillars 14, and copper wires 15. The front of the chip 12 on one lead frame 11 is electrically connected to the adjacent lead frame 11 through the copper pillars 14 and copper wires 15, thereby electrically connecting the front of the chip 12 on one lead frame 11 to the back of the chip 12 on the adjacent lead frame 11, thereby achieving double-sided interconnection of the chips 12.

[0004] but, Figure 1 The double-sided interconnect package structure shown has the following problems:

[0005] (1) The chip 12 is attached to the lead frame 11, which makes the overall thickness of the package structure thicker, which is not conducive to the thinning of the product, and it is easy to cause product deformation due to the deformation of the lead frame 11;

[0006] (2) The design of the copper pillars 14 on the chip 12 increases production costs, and the welding of the copper pillars 14 reduces overall production efficiency;

[0007] (3) Using conductive glue 13 to fix the chip 12 increases the production process and leads to poor introduction efficiency;

[0008] (4) The area of the lead frame 11 limits the area and number of chips 12;

[0009] (5) Since the conductive adhesive 13 has poor conductivity, in order to improve the conductivity, it is necessary to perform metallization on the back of the chip 12, which increases the processing cost of the chip.

[0010] Therefore, it is necessary to improve the existing chip interconnect packaging structure and chip interconnect packaging method to solve the above problems. Summary of the Invention

[0011] The purpose of the present invention is to provide a chip interconnection packaging structure and a chip interconnection packaging method, which can improve the problems of deformation of the packaged product, high production cost and limited chip quantity while realizing double-sided chip interconnection.

[0012] To achieve the above object, the present invention provides a chip interconnect packaging method, comprising:

[0013] Providing a carrier board and a first chip, wherein a first bonding pad is formed on the front surface of the first chip;

[0014] Mounting the first chip with its front side facing the carrier board;

[0015] forming a first plastic packaging layer on the carrier board to encapsulate the first chip;

[0016] Removing the carrier board and forming a groove on a side of the first plastic packaging layer close to the front surface of the first chip;

[0017] forming a first redistribution layer at least on the bottom and side surfaces of the groove;

[0018] Providing a second chip, wherein a second pad is formed on the front surface of the second chip;

[0019] placing the second chip on the first redistribution layer on the bottom surface of the groove, wherein the back surface of the second chip faces the bottom surface of the groove;

[0020] forming a second plastic encapsulation layer covering the first chip and the second chip;

[0021] A second redistribution layer is formed on the first pad, the second pad, the first redistribution layer and the second plastic packaging layer, and the first pad and the first redistribution layer are electrically connected through the second redistribution layer.

[0022] Optionally, there is a gap between the second chip and the first redistribution layer on the side of the groove, and the second plastic packaging layer also fills the gap.

[0023] Optionally, the first redistribution layer is located on part or all of the bottom surface and side surfaces of the groove.

[0024] Optionally, the first redistribution layer extends from a side surface of the groove to a top surface of the first plastic packaging layer.

[0025] Optionally, before forming the groove on the side of the first plastic packaging layer close to the front of the first chip, the actual position of the first chip in the first plastic packaging layer is used as a reference, and the formation position of the groove in the first plastic packaging layer is determined according to the designed theoretical distance between the second chip and the first chip.

[0026] The present invention also provides a chip interconnect packaging structure, comprising:

[0027] A first chip having a first pad formed on the front side;

[0028] a first plastic encapsulation layer covering the first chip, wherein a groove is formed in the first plastic encapsulation layer, and an opening of the groove and a front surface of the first chip are located on the same side of the first plastic encapsulation layer;

[0029] a first redistribution layer formed at least on the bottom and side surfaces of the groove;

[0030] a second chip located in the groove, wherein a second pad is formed on a front surface of the second chip, and a back surface of the second chip is electrically connected to the first redistribution layer on a bottom surface of the groove;

[0031] a second plastic packaging layer, covering the first chip and the second chip; and

[0032] A second redistribution layer is formed on the first pad, the second pad, the first redistribution layer and the second plastic packaging layer, and the first pad and the first redistribution layer are electrically connected through the second redistribution layer.

[0033] Optionally, there is a gap between the second chip and the first redistribution layer on the side of the groove, and the second plastic encapsulation layer is also filled in the gap. The second plastic encapsulation layer is made of the same material as the first plastic encapsulation layer.

[0034] Optionally, the first redistribution layer is located on the entire bottom surface and side surfaces of the groove.

[0035] Optionally, the first redistribution layer extends from a side surface of the groove to a top surface of the first plastic packaging layer.

[0036] Optionally, the second plastic encapsulation layer exposes the first redistribution layer so that the second redistribution layer is electrically connected to the first redistribution layer; or, the second plastic encapsulation layer covers the first redistribution layer so that the second redistribution layer passes through the second plastic encapsulation layer to be electrically connected to the first redistribution layer.

[0037] The chip interconnect packaging structure and chip interconnect packaging method of the present invention form a groove on the side of the first plastic layer encapsulating the first chip close to the front of the first chip, and at least the bottom and side surfaces of the groove form a first redistribution layer. After placing the second chip on the first redistribution layer on the bottom surface of the groove, the back of the second chip is electrically connected to the first redistribution layer. A second redistribution layer is formed on the first solder pad on the front of the first chip, the second solder pad on the front of the second chip, the first redistribution layer, and the second plastic layer, and the first solder pad and the first redistribution layer are electrically connected through the second redistribution layer, so that the front of the first chip is electrically connected to the back of the second chip through the second redistribution layer and the first redistribution layer, thereby realizing double-sided interconnection of the chips. In addition, the chip interconnect packaging structure and chip interconnect packaging method provided by the present invention also have the following advantages:

[0038] (1) Since the back surface of the second chip is directly electrically connected to the first redistribution layer, the impedance of the packaged product is reduced;

[0039] (2) No lead frame and copper pillar are required, so the production process is simplified, production efficiency is improved, and production costs are reduced; in addition, the package product can be made thinner and the risk of package product deformation due to lead frame deformation is reduced;

[0040] (3) No need to use conductive glue to fix the first chip and the second chip, which simplifies the production process;

[0041] (4) directly fixing the first chip and the second chip in the plastic encapsulation layer (i.e., the first plastic encapsulation layer, the second plastic encapsulation layer, and the third plastic encapsulation layer), and adjusting the area of the first plastic encapsulation layer and the area and number of the grooves to meet the area and number of the first chip and the second chip, thereby avoiding the area of the lead frame limiting the area and number of the first chip and the second chip;

[0042] (5) Since the back side of the second chip is directly electrically connected to the first redistribution layer instead of using conductive glue to achieve electrical connection, the back side of the second chip can have high conductivity without metallization treatment, thereby reducing the processing cost of the second chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of a chip interconnect packaging structure;

[0044] Figure 2 is a schematic diagram of a chip interconnect packaging structure according to an embodiment of the present invention;

[0045] Figure 3 is a flow chart of a chip interconnect packaging method according to an embodiment of the present invention;

[0046] Figure 4a to Figure 4l yes Figure 3 Device schematic diagram of the chip interconnect packaging method shown.

[0047] Among them, Figures 1 to 41 The reference numerals are described as follows:

[0048] 11-lead frame; 12-chip; 13-conductive adhesive; 14-copper pillar; 15-copper wire; 16-plastic layer;

[0049] 21-first chip; 211-first solder pad; 22-first plastic layer; 221-carrier; 222-groove; 23-first redistribution layer; 24-second chip; 241-second solder pad; 25-second plastic layer; 251-first through hole; 252-second through hole; 26-second redistribution layer; 27-external pin layer; 28-third plastic layer; 29-tin layer. DETAILED DESCRIPTION

[0050] To further clarify the objectives, advantages, and features of the present invention, the following further describes the chip interconnect packaging structure and chip interconnect packaging method proposed in the present invention. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the objectives of the present invention.

[0051] An embodiment of the present invention provides a chip interconnect packaging structure, which includes a first chip having a first solder pad formed on the front side; a first plastic packaging layer covering the first chip, and a groove formed in the first plastic packaging layer, the opening of the groove and the front side of the first chip are located on the same side of the first plastic packaging layer; a first redistribution layer formed at least on the bottom and side surfaces of the groove; a second chip located in the groove, a second solder pad formed on the front side of the second chip, and the back side of the second chip is electrically connected to the first redistribution layer on the bottom surface of the groove; a second plastic packaging layer covering the first chip and the second chip; and a second redistribution layer formed on the first solder pad, the second solder pad, the first redistribution layer and the second plastic packaging layer, and the first solder pad and the first redistribution layer are electrically connected through the second redistribution layer.

[0052] See below Figure 2 The chip interconnect packaging structure of this embodiment is described in more detail.

[0053] A first pad 211 is formed on the front surface of the first chip 21 .

[0054] The first pad 211 may be protruding or not protruding from the surface of the first chip 21; Figure 2In the embodiment shown, the first pad 211 protrudes from the surface of the first chip 21. There may be a plurality of first pads 211.

[0055] The first plastic layer 22 covers the first chip 21 and has a groove formed therein. The first plastic layer 22 is spaced between the groove and the first chip 21 . The opening of the groove and the front surface of the first chip 21 are located on the same side of the first plastic layer 22 .

[0056] Among them, if the first solder pad 211 protrudes from the surface of the first chip 21, only the front of the first solder pad 211 is exposed by the first plastic sealing layer 22, and the other areas of the first chip 21 are covered by the first plastic sealing layer 22; if the first solder pad 211 does not protrude from the surface of the first chip 21, the entire front of the first chip 21 is exposed by the first plastic sealing layer 22, and the back and side surfaces of the first chip 21 are covered by the first plastic sealing layer 22.

[0057] The first redistribution layer 23 may be located only on the inner surface (including the bottom and side surfaces) of the groove, and preferably the top surface of the first redistribution layer 23 located on the side surfaces of the groove is higher than or flush with the top surface of the first plastic packaging layer 22; or Figure 2 As shown, the first redistribution layer 23 extends from the side surface of the groove to the top surface of the first plastic packaging layer 22 , and the first redistribution layer 23 can extend toward the first chip 21 on the top surface of the first plastic packaging layer 22 .

[0058] Furthermore, the first redistribution layer 23 may be located on a portion or all of the bottom surface of the groove, and the first redistribution layer 23 may be located on a portion or all of the side surfaces of the groove.

[0059] The second chip 24 is located in the groove, and the back of the second chip 24 is electrically connected to the first redistribution layer 23 on the bottom of the groove. Then, the front of the second chip 24 and the front of the first chip 21 are located on the same side of the first plastic layer 22.

[0060] A second pad 241 is formed on the front surface of the second chip 24. The second pad 241 may or may not protrude from the surface of the second chip 24. There may be multiple second pads 241. The first chip 21 and the second chip 24 may be the same or different in size and type.

[0061] If the width of the groove is greater than the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sides of the groove, there will be a gap between the second chip 24 and the first redistribution layer 23 on the sides of the groove; or if the width of the groove is equal to the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sides of the groove, there will be no gap between the second chip 24 and the first redistribution layer 23 on the sides of the groove, and the second chip 24 will be in contact with the first redistribution layer 23 on the sides of the groove. In addition, it is preferred that the width of the groove is slightly greater than the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sides of the groove, so that the second chip 24 can be placed in the groove more smoothly while avoiding obvious position deviation of the second chip 24. It is preferred that the second chip 24 is located in the middle area of the bottom surface of the groove, at which time, the side of the second chip 24 does not contact the first redistribution layer 23 on the sidewall of the groove. It should be noted that, in other embodiments, the second chip 24 may also be located in a non-middle area of the groove. In this case, one or two side surfaces of the second chip 24 are in contact with the first redistribution layer 23 on the side surfaces of the groove.

[0062] The second plastic layer 25 covers the first chip 21 and the second chip 24 .

[0063] Furthermore, if the width of the groove is greater than the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposing sidewalls of the groove, the second plastic encapsulation layer 25 also fills the gap between the second chip 24 and the first redistribution layer 23 on the side of the groove to secure the position of the second chip 24 in the groove. In this case, preferably, the second plastic encapsulation layer 25 is made of the same material as the first plastic encapsulation layer 22, and thus, the second plastic encapsulation layer 25 has the same thermal expansion coefficient as the first plastic encapsulation layer 22. In other embodiments, the second plastic encapsulation layer 25 and the first plastic encapsulation layer 22 may also be made of different materials.

[0064] Furthermore, preferably, the second plastic encapsulation layer 25 also covers the first redistribution layer 23. In this case, if the first redistribution layer 23 is only located on the inner surface of the groove, and the top surface of the first redistribution layer 23 located on the side of the groove is higher than or flush with the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 can be lower than, flush with, or higher than the top surface of the first redistribution layer 23 on the side of the groove; if the first redistribution layer 23 extends from the side of the groove to the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 can be lower than, flush with, or higher than the top surface of the first redistribution layer 23 on the top surface of the first plastic encapsulation layer 22. Therefore, the second plastic encapsulation layer 25 also covering the first redistribution layer 23 can reduce the limitation between the thickness of the second chip 24 and the depth of the groove.

[0065] In other embodiments, the second plastic encapsulation layer 25 may also expose the first redistribution layer 23. In this case, if the first redistribution layer 23 is only located on the inner surface of the groove, and the top surface of the first redistribution layer 23 located on the side of the groove is higher than or flush with the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 needs to be lower than the top surface of the first redistribution layer 23 on the side of the groove, otherwise the second plastic encapsulation layer 25 will not be able to cover the second chip 24. If the first redistribution layer 23 extends from the inner surface of the groove to the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 needs to be lower than the top surface of the first redistribution layer 23 on the top surface of the first plastic encapsulation layer 22, otherwise the second plastic encapsulation layer 25 will not be able to cover the second chip 24. Therefore, compared with the case where the second plastic encapsulation layer 25 also covers the first redistribution layer 23, the second plastic encapsulation layer 25 exposing the first redistribution layer 23 increases the limit between the thickness of the second chip 24 and the depth of the groove.

[0066] The second redistribution layer 26 is formed on the first pad 211 , the second pad 241 , the first redistribution layer 23 and the second plastic layer 25 , and the first pad 211 and the first redistribution layer 23 are electrically connected through the second redistribution layer 26 .

[0067] Since there are multiple first solder pads 211 and second solder pads 241, each first solder pad 211 and each second solder pad 241 is electrically connected to a second redistribution layer 26, and the second redistribution layers 26 are not connected to each other; only the second redistribution layer 26 on the first solder pad 211 is electrically connected to the second redistribution layer 26 on the first redistribution layer 23, so that the first solder pad 211 and the first redistribution layer 23 are electrically connected through the second redistribution layer 26.

[0068] The second redistribution layer 26 on the first pad 211 and the second pad 241 is electrically connected to the first pad 211 and the second pad 241 by respectively penetrating the second plastic layer 25 .

[0069] Moreover, if the second plastic sealing layer 25 exposes the first redistribution layer 23, the second redistribution layer 26 is directly electrically connected to the first redistribution layer 23; if the second plastic sealing layer 25 also covers the first redistribution layer 23, the second redistribution layer 26 passes through the second plastic sealing layer 25 to be electrically connected to the first redistribution layer 23.

[0070] In addition, the chip interconnect packaging structure further includes:

[0071] an external pin layer 27 formed on the second redistribution layer 26;

[0072] a third plastic encapsulation layer 28 covering the second plastic encapsulation layer 25 and the second redistribution layer 26 , wherein the third plastic encapsulation layer 28 at least exposes the top surface of the external pin layer 27 ;

[0073] A tin layer 29 is formed on the exposed outer pin layer 27 , and the tin layer 29 also extends onto the third plastic packaging layer 28 .

[0074] and, Figure 2 The chip interconnect packaging structure shown can be repeatedly formed in a packaged product so that the packaged product can include at least two first chips 21 and at least two second chips 24. Taking the packaged product containing two first chips 21 and two second chips 24 as an example, one of the first pads 211 on the first first chip 21 is electrically connected to the first redistribution layer 23 in the first groove and the back side of the second chip 24 through the connected second redistribution layer 26, and another first pad 211 on the first first chip 21 is electrically connected to the first redistribution layer 23 in the second groove and the back side of the second chip 24 through the connected second redistribution layer 26. The first redistribution layer 23 in the second groove is electrically connected to one of the first pads 211 on the second first chip 21, thereby enabling electrical conduction between the back side of the second chip 24 in the first groove and the front side of the first first chip 21, the front side of the first first chip 21 and the back side of the second chip 24 in the second groove, and the back side of the second chip 24 in the second groove and the front side of the second first chip 21, thereby achieving double-sided interconnection between the chips.

[0075] The first plastic packaging layer 22 , the second plastic packaging layer 25 and the third plastic packaging layer 28 may be made of epoxy resin molding compound, and the first redistribution layer 23 and the second redistribution layer 26 may be made of metal such as copper.

[0076] From the above content, it can be seen that the chip interconnection packaging structure provided by the present invention has a groove formed in the first plastic packaging layer covering the first chip, the opening of the groove and the front of the first chip are located on the same side of the first plastic packaging layer, and a first redistribution layer is formed on at least the bottom and side surfaces of the groove, and the back of the second chip in the groove is electrically connected to the first redistribution layer on the bottom surface of the groove, a second redistribution layer is formed on the first solder pad on the front of the first chip, the second solder pad on the front of the second chip, the first redistribution layer and the second plastic packaging layer, and the first solder pad and the first redistribution layer are electrically connected through the second redistribution layer, so that the front of the first chip is electrically connected to the back of the second chip through the second redistribution layer and the first redistribution layer, thereby realizing double-sided interconnection of the chips and realizing forward and reverse conduction of the chips.

[0077] And, with Figure 1 Compared with the chip interconnect packaging structure shown in FIG, the chip interconnect packaging structure provided by the present invention also has the following advantages:

[0078] (1) Since the back surface of the second chip is directly electrically connected to the first redistribution layer, the impedance of the packaged product is reduced; and if the first redistribution layer is located on the entire bottom surface of the groove, the entire back surface of the second chip is in contact with the first redistribution layer, so that the impedance of the packaged product is significantly reduced;

[0079] (2) No lead frame and copper pillar are required, so the production process is simplified, production efficiency is improved, and production costs are reduced; in addition, the package product can be made thinner and the risk of package product deformation due to lead frame deformation is reduced;

[0080] (3) No need to use conductive glue to fix the first chip and the second chip, which simplifies the production process;

[0081] (4) directly fixing the first chip and the second chip in the plastic encapsulation layer (i.e., the first plastic encapsulation layer, the second plastic encapsulation layer, and the third plastic encapsulation layer), and adjusting the area of the first plastic encapsulation layer and the area and number of the grooves to meet the area and number of the first chip and the second chip, thereby avoiding the area of the lead frame limiting the area and number of the first chip and the second chip;

[0082] (5) Since the back side of the second chip is directly electrically connected to the first redistribution layer instead of using conductive glue to achieve electrical connection, the back side of the second chip can have high conductivity without metallization treatment, thereby reducing the processing cost of the second chip.

[0083] In addition, compared to another chip interconnect packaging structure, the structure includes: a plastic layer, two grooves are formed in the plastic layer, a chip is placed in each groove, and the back of the chip faces the bottom of the groove. A redistribution layer is arranged on the front of the two chips so that the pads on the front of the two chips are electrically connected to each other, thereby achieving a single-sided interconnection between the fronts of the two chips. In this case, the metal (i.e., the redistribution layer) is located on one side of the front of the two chips. Due to the large difference in thermal expansion coefficient between the metal and the plastic layer, if the metal is located on the same side of the front of the two chips, the chip interconnect packaging structure will cause warping when used in a high-temperature environment. After long-term use, delamination between the metal and the plastic layer will occur, affecting the reliability of the product. In the present invention, although a second redistribution layer made of metal is also formed on the front of the two chips (i.e., the first chip and the second chip), warping will also occur when used in a high-temperature environment, the first redistribution layer is also formed on the bottom and side surfaces of the groove of the first plastic layer. This means that a layer of metal is present between the second chip placed in the groove and the first plastic layer, which is equivalent to adding a layer of metal inside the first plastic layer. This can generate a pulling force on the chip when warping occurs, thereby reducing warping. Therefore, the chip interconnect packaging structure of the present invention can improve the reliability of the product and make the product performance more stable.

[0084] Moreover, in the above-mentioned other chip interconnect packaging structure, in order to reduce warping, the thermal expansion coefficient of the filling layer between the side of the groove and the chip is between the chip and the plastic layer, so it is necessary to use different materials for the filling layer and the plastic layer; whereas in the present invention, since the first redistribution layer formed on the bottom and side of the groove can already reduce the warping, the second plastic layer filled in the gap between the second chip and the first redistribution layer on the side of the groove can be made of the same material as the first plastic layer, thereby making the range of material selection for the first plastic layer and the second plastic layer wider.

[0085] An embodiment of the present invention provides a chip interconnect packaging method, referring to Figure 3 , Figure 3 1 is a flow chart of a chip interconnect packaging method according to an embodiment of the present invention, wherein the chip interconnect packaging method includes:

[0086] Step S1, providing a carrier board and a first chip, wherein a first bonding pad is formed on the front surface of the first chip;

[0087] Step S2, mounting the first chip with its front side facing the carrier board;

[0088] Step S3, forming a first plastic packaging layer on the carrier board to encapsulate the first chip;

[0089] Step S4, removing the carrier board and forming a groove on a side of the first plastic packaging layer close to the front surface of the first chip;

[0090] Step S5, forming a first redistribution layer at least on the bottom surface and side surfaces of the groove;

[0091] Step S6, providing a second chip, wherein a second pad is formed on the front surface of the second chip;

[0092] Step S7, placing the second chip on the first redistribution layer on the bottom surface of the groove, wherein the back surface of the second chip faces the bottom surface of the groove;

[0093] Step S8, forming a second plastic packaging layer covering the first chip and the second chip;

[0094] Step S9: forming a second redistribution layer on the first pad, the second pad, the first redistribution layer and the second plastic packaging layer, and electrically connecting the first pad and the first redistribution layer through the second redistribution layer.

[0095] See below Figure 4a to Figure 4l The chip interconnect packaging method provided by this embodiment is introduced in more detail.

[0096] According to step S1 , a carrier 221 and a first chip 21 are provided, wherein a first bonding pad 211 is formed on the front surface of the first chip 21 .

[0097] The first pad 211 may be protruding or not protruding from the surface of the first chip 21; Figure 4a to Figure 4l In the embodiment shown, the first pad 211 protrudes from the surface of the first chip 21. There may be a plurality of first pads 211.

[0098] The carrier plate 221 can be a steel plate, a glass plate, etc.

[0099] Step S2, see Figure 4a , mount the first chip 21 with its front side facing the carrier 221 .

[0100] The carrier surface of the carrier 221 may be provided with an adhesive layer (not shown), and the first chip 21 is attached to the carrier 221 via the adhesive layer. The adhesive layer may be made of an easily peelable material to facilitate peeling off the carrier 221. Alternatively, the adhesive layer may be a thermal release material that loses its stickiness upon heating or a UV release material that loses its stickiness upon exposure to ultraviolet light.

[0101] Furthermore, if the first solder pad 211 protrudes from the surface of the first chip 21, when the front surface of the first chip 21 is mounted toward the carrier 221, only the first solder pad 211 contacts the adhesive layer on the carrier 221, and other areas of the front surface of the first chip 21 do not contact the adhesive layer on the carrier 221.

[0102] Step S3, see Figure 4a A first plastic packaging layer 22 is formed on the carrier board 221 to encapsulate the first chip 21 , and the first plastic packaging layer 22 covers the first chip 21 .

[0103] The carrier board 221 and the first chip 21 may be placed together in a molding device, and a molding process may be performed to form a first molding layer 22 covering the first chip 21 .

[0104] Follow step S4, refer to Figure 4b , the carrier board 221 is removed, and a groove 222 is formed on the side of the first plastic layer 22 close to the front surface of the first chip 21. The opening of the groove 222 and the front surface of the first chip 21 are located on the same side of the first plastic layer 22, and the first plastic layer 22 is between the groove 222 and the first chip 21.

[0105] Among them, since the position of the first chip 21 in the first plastic packaging layer 22 has been fixed after the first chip 21 is packaged, before the groove 222 is formed on the side of the first plastic packaging layer 22 close to the front of the first chip 21, it is preferred to first use the actual position of the first chip 21 in the first plastic packaging layer 22 as a reference, and determine the formation position of the groove 222 in the first plastic packaging layer 22 according to the theoretical distance between the second chip 24 subsequently placed in the groove 222 and the first chip 21.

[0106] After packaging the first chip 21, the board can be transferred and the carrier 221 can be removed to place the first plastic layer 22 on another carrier (not shown). At this time, the front side of the first chip 21 in the first plastic layer 22 faces upward.

[0107] Moreover, if the first solder pad 211 protrudes from the surface of the first chip 21, after removing the carrier 221, only the front side of the first solder pad 211 is exposed, and the other areas of the first chip 21 are covered by the first plastic layer 22; if the first solder pad 211 does not protrude from the surface of the first chip 21, after removing the carrier 221, the entire front side of the first chip 21 is exposed, and the back and sides of the first chip 21 are covered by the first plastic layer 22.

[0108] The groove 222 may be formed by a laser process, and the depth and width of the groove 222 may be adjusted by adjusting parameters of the laser process (eg, frequency, power, spot size, etc.).

[0109] According to step S5, refer to Figure 4c A first redistribution layer 23 is formed at least on the inner surface (including the bottom and side surfaces) of the groove 222. The first redistribution layer 23 may be formed by an electroplating process.

[0110] The first redistribution layer 23 may be located only on the inner surface of the groove 222, and preferably the top surface of the first redistribution layer 23 located on the side of the groove 222 is higher than or flush with the top surface of the first plastic layer 22; or Figure 4c As shown, the first redistribution layer 23 extends from the side surface of the groove 222 to the top surface of the first plastic packaging layer 22 , and the first redistribution layer 23 can extend toward the first chip 21 on the top surface of the first plastic packaging layer 22 .

[0111] Furthermore, the first redistribution layer 23 may be located on a portion or all of the bottom surface of the groove 222 , and the first redistribution layer 23 may be located on a portion or all of the side surfaces of the groove 222 .

[0112] According to step S6 , a second chip 24 is provided, wherein a second bonding pad 241 is formed on the front surface of the second chip 24 .

[0113] The second pad 241 may or may not protrude from the surface of the second chip 24. There may be a plurality of second pads 241. The first chip 21 and the second chip 24 may be of the same or different size and type.

[0114] According to step S7, refer to Figure 4d, the second chip 24 is placed on the first redistribution layer 23 on the bottom surface of the groove 222, with the back surface of the second chip 24 facing the bottom surface of the groove 222, and the back surface of the second chip 24 is electrically connected to the first redistribution layer 23 on the bottom surface of the groove 222. Then, the second chip 24 also faces the front surface upward and the back surface downward, and the front surfaces of the second chip 24 and the first chip 21 are located on the same side of the first plastic layer 22.

[0115] If the width of the groove 222 is greater than the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sides of the groove 222, there will be a gap between the second chip 24 and the first redistribution layer 23 on the sides of the groove 222; or if the width of the groove 222 is equal to the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sides of the groove 222, there will be no gap between the second chip 24 and the first redistribution layer 23 on the sides of the groove 222, and the second chip 24 will be in contact with the first redistribution layer 23 on the sides of the groove 222. Furthermore, it is preferred that the width of the groove is slightly greater than the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sides of the groove, so that the second chip 24 can be placed in the groove 222 more smoothly while avoiding obvious positional deviation of the second chip 24. The second chip 24 is preferably placed in the middle area of the bottom surface of the groove 222. In this case, the side surfaces of the second chip 24 do not contact the first redistribution layer 23 on the sidewalls of the groove 222. It should be noted that, in other embodiments, the second chip 24 may also be placed in a non-middle area of the groove 222. In this case, one or both side surfaces of the second chip 24 contact the first redistribution layer 23 on the side surfaces of the groove 222.

[0116] According to step S8, refer to Figure 4e and Figure 4f , forming a second plastic encapsulation layer 25 covering the first chip 21 and the second chip 24. Furthermore, if the width of the groove 222 is greater than the sum of the width of the second chip 24 and the thickness of the first redistribution layer 23 on the two opposite sidewalls of the groove 222, the second plastic encapsulation layer 25 also fills the gap between the second chip 24 and the first redistribution layer on the sides of the groove 222 to fix the position of the second chip 24 in the groove 222.

[0117] Furthermore, preferably, the second plastic encapsulation layer 25 also covers the first redistribution layer 23. In this case, if the first redistribution layer 23 is only located on the inner surface of the groove 222, and the top surface of the first redistribution layer 23 located on the side of the groove 222 is higher than or flush with the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 can be lower than, flush with, or higher than the top surface of the first redistribution layer 23 on the side of the groove 222. If the first redistribution layer 23 extends from the side of the groove 222 to the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 can be lower than, flush with, or higher than the top surface of the first redistribution layer 23 on the top surface of the first plastic encapsulation layer 22. Therefore, the second plastic encapsulation layer 25 also covering the first redistribution layer 23 can reduce the limitation between the thickness of the second chip 24 and the depth of the groove 222.

[0118] In other embodiments, the second plastic encapsulation layer 25 may also expose the first redistribution layer 23. In this case, if the first redistribution layer 23 is only located on the inner surface of the groove 222, and the top surface of the first redistribution layer 23 located on the side of the groove 222 is higher than or flush with the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 needs to be lower than the top surface of the first redistribution layer 23 on the side of the groove 222, otherwise the second plastic encapsulation layer 25 will not cover the second chip 24. If the first redistribution layer 23 extends from the inner surface of the groove 222 to the top surface of the first plastic encapsulation layer 22, then the front surface of the second chip 24 needs to be lower than the top surface of the first redistribution layer 23 on the top surface of the first plastic encapsulation layer 22, otherwise the second plastic encapsulation layer 25 will not cover the second chip 24. Therefore, compared to when the second plastic encapsulation layer 25 also covers the first redistribution layer 23, the second plastic encapsulation layer 25 exposing the first redistribution layer 23 increases the limit between the thickness of the second chip 24 and the depth of the groove 222.

[0119] Taking the second plastic encapsulation layer 25 exposing the first redistribution layer 23 as an example, a large plate lamination process can be used to cover the first plastic encapsulation layer 22 with a plastic encapsulation film, such as Figure 4e As shown, the second plastic encapsulation layer 25 is formed to bury the first chip 21, the second chip 24 and the first redistribution layer 23, and the second plastic encapsulation layer 25 fills the groove 222; then, as shown Figure 4f As shown, the second plastic encapsulation layer 25 is ground until the first redistribution layer 23 is exposed. At this time, the second plastic encapsulation layer 25 covers the first chip 21 and encapsulates the second chip 24 .

[0120] According to step S9, refer to Figure 4g and Figure 4hA second redistribution layer 26 is formed on the first pad 211 , the second pad 241 , the first redistribution layer 23 and the second plastic layer 25 , and the first pad 211 and the first redistribution layer 26 are electrically connected through the second redistribution layer 26 .

[0121] Since there are multiple first solder pads 211 and second solder pads 241, each first solder pad 211 and each second solder pad 241 is electrically connected to a second redistribution layer 26, and the second redistribution layers 26 are not connected to each other; only the second redistribution layer 26 on the first solder pad 211 is electrically connected to the second redistribution layer 26 on the first redistribution layer 23, so that the first solder pad 211 and the first redistribution layer 26 are electrically connected through the second redistribution layer 26.

[0122] Moreover, if the second plastic sealing layer 25 exposes the first redistribution layer 23, the second redistribution layer 26 is directly electrically connected to the first redistribution layer 23; if the second plastic sealing layer 25 also covers the first redistribution layer 23, the second redistribution layer 26 passes through the second plastic sealing layer 25 to be electrically connected to the first redistribution layer 23.

[0123] If the second plastic encapsulation layer 25 exposes the first redistribution layer 23, the steps of forming the second redistribution layer 26 include: first, Figure 4g As shown, a first through hole 251 exposing the first pad 211 and a second through hole 252 exposing the second pad 241 are formed in the second plastic encapsulation layer 25 by a laser process; then, as shown in FIG. Figure 4h As shown, a plurality of second redistribution layers 26 are formed on the first solder pad 211 exposed by the first through hole 251, the second solder pad 241 exposed by the second through hole 252, the first redistribution layer 23 and the second plastic encapsulation layer 25 by an electroplating process, and only the second redistribution layer 26 on the first solder pad 211 is electrically connected to the second redistribution layer 26 on the first redistribution layer 23.

[0124] If the second plastic packaging layer 25 also covers the first redistribution layer 23, the step of forming the second redistribution layer 26 includes (this step is not shown in the figure): first, a first through hole exposing the first solder pad 211, a second through hole exposing the second solder pad 241, and a third through hole exposing the first redistribution layer 23 are formed in the second plastic packaging layer 25; then, a second redistribution layer 26 is formed on the first solder pad 211 exposed by the first through hole, the second solder pad 241 exposed by the second through hole, the first redistribution layer 23 exposed by the third through hole, and the second plastic packaging layer 25, and the second redistribution layer 26 on the first solder pad 211 is electrically connected to the second redistribution layer 26 on the first redistribution layer 23.

[0125] In addition, the chip interconnect packaging method further includes: first, as Figure 4i As shown, an outer pin layer 27 is formed on the second redistribution layer 26; then, as shown Figure 4j As shown, a large plate lamination process is used to form a third plastic encapsulation layer 28 covering the second plastic encapsulation layer 25, the second redistribution layer 26, the first redistribution layer 23 and the external pin layer 27; then, as shown Figure 4k As shown, the third plastic encapsulation layer 28 is ground by a grinding process until the third plastic encapsulation layer 28 at least exposes the top surface of the outer lead layer 27; then, as shown in FIG. Figure 4l As shown, a tin layer 29 is formed on the exposed outer pin layer 27 by electroplating, and the tin layer 29 also extends onto the third plastic packaging layer 28 .

[0126] and, Figure 4lThe chip interconnection packaging structure shown can be repeatedly formed in a packaged product, so that the packaged product can include at least two first chips 21 and at least two second chips 24 . Taking the packaged product as an example, which includes two first chips 21 and two second chips 24, one of the first solder pads 211 on the first first chip 21 is electrically connected to the first redistribution layer 23 in the first groove 222 and the back of the second chip 24 through the connected second redistribution layer 26, and another first solder pad 211 on the first first chip 21 is electrically connected to the first redistribution layer 23 in the second groove 222 and the back of the second chip 24 through the connected second redistribution layer 26, and the first redistribution layer 23 in the second groove 222 is electrically connected to one of the first solder pads 211 on the second first chip 21, so that the back of the second chip 24 in the first groove is conductive to the front of the first first chip 21, the front of the first first chip 21 is conductive to the back of the second chip 24 in the second groove, and the back of the second chip 24 in the second groove is conductive to the front of the second first chip 21, thereby realizing double-sided interconnection between the chips.

[0127] The first plastic packaging layer 22 , the second plastic packaging layer 25 and the third plastic packaging layer 28 may be made of epoxy resin molding compound, and the first redistribution layer 23 and the second redistribution layer 26 may be made of metal such as copper.

[0128] From the above content, it can be seen that the chip interconnection packaging method provided by the present invention forms a groove on the side of the first plastic layer encapsulating the first chip close to the front side of the first chip, forms a first redistribution layer at least on the bottom and side of the groove, and after placing the second chip on the first redistribution layer on the bottom of the groove, the back side of the second chip is electrically connected to the first redistribution layer, and forms a second redistribution layer on the first solder pad on the front side of the first chip, the second solder pad on the front side of the second chip, the first redistribution layer and the second plastic layer, and the first solder pad and the first redistribution layer are electrically connected through the second redistribution layer, so that the front side of the first chip is electrically connected to the back side of the second chip through the second redistribution layer and the first redistribution layer, thereby realizing double-sided interconnection of the chips and realizing forward and reverse conduction of the chips.

[0129] Furthermore, a packaging method for interconnecting a chip (forming a packaging structure such as Figure 1 Compared with the packaging method of chip interconnection provided by the present invention, the packaging method of chip interconnection provided by the present invention also has the following advantages:

[0130] (1) Since the back surface of the second chip is directly electrically connected to the first redistribution layer, the impedance of the packaged product is reduced; and if the first redistribution layer is located on the entire bottom surface of the groove, the entire back surface of the second chip is in contact with the first redistribution layer, so that the impedance of the packaged product is significantly reduced;

[0131] (2) No lead frame and copper pillar are required, so the production process is simplified, production efficiency is improved, and production costs are reduced; in addition, the package product can be made thinner and the risk of package product deformation due to lead frame deformation is reduced;

[0132] (3) No need to use conductive glue to fix the first chip and the second chip, which simplifies the production process;

[0133] (4) directly fixing the first chip and the second chip in the plastic encapsulation layer (i.e., the first plastic encapsulation layer, the second plastic encapsulation layer, and the third plastic encapsulation layer), and adjusting the area of the first plastic encapsulation layer and the area and number of the grooves to meet the area and number of the first chip and the second chip, thereby avoiding the area of the lead frame limiting the area and number of the first chip and the second chip;

[0134] (5) Since the back side of the second chip is directly electrically connected to the first redistribution layer instead of using conductive glue to achieve electrical connection, the back side of the second chip can have high conductivity without metallization treatment, thereby reducing the processing cost of the second chip.

[0135] In addition, with respect to another chip interconnect packaging method, the method includes: providing a plastic layer, first forming two grooves in the plastic layer, then placing two chips in the two grooves, respectively, with the backs of the chips facing the bottoms of the grooves, and then, by laying out a redistribution layer on the front sides of the two chips, electrically connecting the pads on the front sides of the two chips, thereby achieving a single-sided interconnection between the front sides of the two chips. In this case, the metal (i.e., the redistribution layer) in the formed chip interconnect packaging structure is all located on one side of the front sides of the two chips. Due to the significant difference in thermal expansion coefficients between the metal and the plastic layer, if the metal is all located on the same side of the front sides of the two chips, the chip interconnect packaging structure will warp when used in a high-temperature environment. After long-term use, delamination will occur between the metal and the plastic layer, affecting the reliability of the product. In the present invention, although a second redistribution layer made of metal is formed on the front of both chips (i.e., the first chip and the second chip), warping will occur when used in a high-temperature environment, a first redistribution layer is also formed on the bottom and side surfaces of the groove of the first plastic layer, so that a layer of metal exists between the second chip placed in the groove and the first plastic layer, which is equivalent to adding a layer of metal inside the first plastic layer, and can generate a pulling force on the chip when warping occurs, so that the warping is reduced, thereby improving the reliability of the product and making the product performance more stable.

[0136] Furthermore, in the above-mentioned other chip interconnection packaging method, after the two chips are respectively placed in the two grooves and before a filling layer is formed between the side of the groove and the chips to fix the chips, the positions of the two chips will be offset, resulting in poor alignment accuracy between the redistribution layer and the pads on the front of the two chips; in the present invention, since the actual position of the first chip in the first plastic packaging layer has been fixed after the first chip is packaged, then before the groove is formed on the side of the first plastic packaging layer close to the front of the first chip, if the actual position of the first chip in the first plastic packaging layer is used as a reference, the formation position of the groove in the first plastic packaging layer is determined according to the designed theoretical distance between the second chip and the first chip, so that the position of the groove is determined, then before covering the second plastic packaging layer, only the position of the second chip will be offset in the groove, while the position of the first chip is accurate, thereby significantly improving the alignment accuracy between the subsequently produced second redistribution layer and the pads on the first chip and the second chip.

[0137] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A chip interconnect packaging method, characterized in that: include: Providing a carrier board and a first chip, wherein a first bonding pad is formed on the front surface of the first chip; Mounting the first chip with its front side facing the carrier board; forming a first plastic packaging layer on the carrier board to encapsulate the first chip; Removing the carrier board and forming a groove on a side of the first plastic packaging layer close to the front surface of the first chip; forming a first redistribution layer at least on the bottom and side surfaces of the groove; Providing a second chip, wherein a second pad is formed on the front surface of the second chip; placing the second chip on the first redistribution layer on the bottom surface of the groove, wherein the back surface of the second chip faces the bottom surface of the groove, and the back surface of the second chip contacts the first redistribution layer on the bottom surface of the groove; forming a second plastic encapsulation layer covering the first chip and the second chip; A second redistribution layer is formed on the first pad, the second pad, the first redistribution layer and the second plastic packaging layer, and the first pad and the first redistribution layer are electrically connected through the second redistribution layer.

2. The chip interconnect packaging method according to claim 1, wherein: There is a gap between the second chip and the first redistribution layer on the side of the groove, and the second plastic packaging layer also fills the gap.

3. The chip interconnect packaging method according to claim 1, wherein: The first redistribution layer is located on part or all of the bottom surface and side surfaces of the groove.

4. The chip interconnect packaging method according to claim 1, wherein: The first redistribution layer extends from a side surface of the groove to a top surface of the first plastic packaging layer.

5. The chip interconnect packaging method according to claim 1, wherein: Before forming the groove on the side of the first plastic packaging layer close to the front surface of the first chip, the actual position of the first chip in the first plastic packaging layer is used as a reference, and the formation position of the groove in the first plastic packaging layer is determined according to the designed theoretical distance between the second chip and the first chip.

6. A chip interconnect packaging structure, characterized in that: include: A first chip having a first pad formed on the front side; a first plastic encapsulation layer covering the first chip, wherein a groove is formed in the first plastic encapsulation layer, and an opening of the groove and a front surface of the first chip are located on the same side of the first plastic encapsulation layer; a first redistribution layer formed at least on the bottom and side surfaces of the groove; a second chip located in the groove, a second pad being formed on a front surface of the second chip, and a back surface of the second chip being electrically connected to the first redistribution layer on the bottom surface of the groove, and the back surface of the second chip being in contact with the first redistribution layer on the bottom surface of the groove; a second plastic sealing layer, covering the first chip and the second chip; as well as, A second redistribution layer is formed on the first pad, the second pad, the first redistribution layer and the second plastic packaging layer, and the first pad and the first redistribution layer are electrically connected through the second redistribution layer.

7. The chip interconnect packaging structure according to claim 6, wherein: There is a gap between the second chip and the first redistribution layer on the side of the groove, and the second plastic packaging layer is also filled in the gap. The second plastic packaging layer is made of the same material as the first plastic packaging layer.

8. The chip interconnect packaging structure according to claim 6, wherein: The first redistribution layer is located on the entire bottom surface and side surfaces of the groove.

9. The chip interconnect packaging structure according to claim 6, wherein: The first redistribution layer extends from a side surface of the groove to a top surface of the first plastic packaging layer.

10. The chip interconnect packaging structure according to claim 6, wherein: The second plastic encapsulation layer exposes the first redistribution layer so that the second redistribution layer is electrically connected to the first redistribution layer; or, the second plastic encapsulation layer covers the first redistribution layer so that the second redistribution layer passes through the second plastic encapsulation layer to be electrically connected to the first redistribution layer.

Images