Measurement sequence determination for quantum computing devices

Abstract

A computing system is provided, including a processor configured to identify multiple measurement sequences that implement a logic gate. Each measurement sequence may include multiple measurements of a quantum state of a topological quantum computing device. The processor may also be configured to determine a corresponding estimated total resource cost for each measurement sequence in the multiple measurement sequences. The processor may also be configured to determine a first measurement sequence in the multiple measurement sequences that has a lowest estimated total resource cost. The topological quantum computing device may be configured to implement the logic gate by applying the first measurement sequence to the quantum state.

Description

Background Art

[0001] Recent experiments have confirmed the existence of Majorana zero modes (MZMs) in hybrid semiconductor-superconductor heterostructures. MZMs have been investigated as platforms for topological quantum computing. Current research lines in topological quantum computing using MZMs aim to assemble networks of topological superconductors in a way that allows for practical quantum information processing on many qubits. Summary of the Invention

[0002] According to one aspect of the present disclosure, a computing system is provided, comprising a processor configured to identify a plurality of measurement sequences that implement a logic gate. Each measurement sequence may include a plurality of measurements of a quantum state of a topological quantum computing device. The processor may also be configured to determine a corresponding estimated total resource cost for each of the plurality of measurement sequences. The processor may also be configured to determine a first measurement sequence having a lowest estimated total resource cost among the plurality of measurement sequences. The topological quantum computing device may be configured to implement the logic gate by applying the first measurement sequence to the quantum state.

[0003] This summary is provided to introduce a series of concepts that are further described in the detailed description below in a simplified form. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all of the shortcomings noted in any part of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An example quantum computing system including a processor and a topological quantum computing device including two Majorana hexacons is shown according to one embodiment of the present disclosure.

[0005] Figure 2 Shown according to Figure 1 An example of an embodiment of a bilateral Majorana hexagram architecture.

[0006] Figure 3 Shown according to Figure 1 An example of an embodiment of a one-sided Majorana hexagram architecture.

[0007] Figure 4 An example quantum computing system including a processor and a topological quantum computing device including two Majorana tetraons according to another embodiment of the present disclosure is shown.

[0008] Figure 5 Shown according to Figure 1Example of the projection operator of the Majorana hexagram.

[0009] Figure 6 Shown according to Figure 1 A joint Fermi (fermionic) parity operator expressed in terms of a Pauli matrix of an embodiment.

[0010] Figure 7 Shown according to Figure 1 A diagrammatic representation of a Majorana hexason including computational qubits and auxiliary qubits of an embodiment.

[0011] Figure 8 Shown according to Figure 1 An example of a braided transformation for the Majorana hexaplex and an example measurement sequence.

[0012] Figure 9 Shown according to Figure 1 Schematic representation of an example measurement sequence for a Majorana hexaplex of an embodiment.

[0013] Figure 10 Shown according to Figure 1 An auxiliary projection operator for the Majorana hexagram of an embodiment.

[0014] Figure 11 Shown according to Figure 1 An embodiment includes a projector sequence of auxiliary projection operators.

[0015] Figure 12 Shown according to Figure 1 Embodiment of the two-qubit projection operator for the four Majorana zero-energy modes of the Majorana hexaton.

[0016] Figure 13 Shown according to Figure 1 An embodiment of the invention generates a measurement sequence of a two-qubit logic gate.

[0017] Figures 14A-14C Shown according to Figure 2 An example Fermi parity measurement configuration of an embodiment in a double-sided Majorana hexaplex architecture.

[0018] Figure 14D Shown according to Figure 2 Estimated weighted measurement cost of a Fermi parity measurement of an embodiment.

[0019] Figures 15A-15E Shown according to Figure 3 An example Fermi parity measurement configuration in a one-sided Majorana hexaplex architecture of an embodiment.

[0020] Figure 16A Shown according to Figure 1Example post-measurement states of a Majorana hexaplex of embodiment.

[0021] Figure 16B Shown according to Figure 1 A method for performing forced measurement of a projection operator of an embodiment.

[0022] Figure 17A Shown according to Figure 1 Illustration of the projection operator sequence of an embodiment.

[0023] Figure 17B Shown according to Figure 17A Illustration of a projection operator sequence after a measurement of an undesired parity of the projection operator has been performed according to an embodiment of the present invention.

[0024] Figure 17C Shown is applied to Figure 17B Illustration of the forced measurement of the sequence of projection operators.

[0025] Figure 18 Shown according to Figures 16A-16B An estimated total resource cost of a measurement sequence of an embodiment in which mandatory measurements occur.

[0026] Figures 19A-19B Shown according to Figure 1 Illustration of an example measurement sequence of an embodiment of , in which an alternative forced measurement protocol is applied to a quantum state.

[0027] Figure 20 Shown according to Figures 19A-19B An estimated total resource cost of a measurement sequence of an embodiment in which an alternative mandatory measurement protocol is applied.

[0028] Figure 21 Shown according to Figure 1 An example measurement sequence that occurs when using forced measurement on the four Majorana zero-energy modes of a Majorana hexaplex.

[0029] Figure 22 Shown according to Figure 21 An embodiment of the invention provides an estimated total resource cost for a measurement sequence comprising forced measurements on four Majorana zero-energy modes of a Majorana hexaplex.

[0030] Figure 23 Shown according to Figure 1 A joint Fermi parity operator expressed in terms of a Pauli operator is provided for an embodiment of the present invention.

[0031] Figures 24A-24B Shown according to Figure 23 Illustration of a measurement sequence of embodiments that differ only in the overall Pauli operator.

[0032] Figure 25 Shown according to Figure 1 The compilation of the embodiment is the construction of a measurement sequence of logic gates for a plurality of Majorana hexaplexes.

[0033] Figure 26 shows that when using the Majorana-Pauli tracking protocol Figure 25 The estimated total resource cost of the measurement sequence.

[0034] Figure 27 shows that when using the forced measurement protocol Figure 25 The estimated total resource cost of the measurement sequence.

[0035] Figure 28 Shown according to Figure 1 A flowchart of an example method of an embodiment that can be used to perform quantum computing by implementing logic gates.

[0036] Figure 29 shows that it is possible to formulate Figure 1 Schematic diagram of an example computing environment for a quantum computing system. DETAILED DESCRIPTION

[0037] Measurement-only topological quantum computing is an approach to topological quantum computing that is well suited for implementations using Majorana zero modes (MZMs). Measurement-only topological quantum computing allows computations to be performed without physically moving the MZMs, which are typically bound to macroscopic defects (such as the ends of wires, as discussed in further detail below) and can be difficult to move. Instead, braided transformations can be performed by making a series of (possibly non-local) measurements on a group of MZMs that involve an MZM encoding the computational state to be manipulated and another group of MZMs serving as auxiliary degrees of freedom. In certain architectures, the MZMs can be coupled to quantum dots, allowing the state of the MZMs to be measured by measuring their effect on the energy spectrum of the quantum dots.

[0038] Using MZM, Clifford gates (e.g., Hadamard gates, π / 4 phase gates, or controlled NOT gates) can be constructed in quantum computing devices. To perform universal quantum computation, additional gates such as T-gates (π / 8 phase gates) can be additionally implemented. The Clifford gates can be topologically protected so that perturbations to the quantum state when implementing the Clifford gates are suppressed. In such a configuration, the T-gates may not be topologically protected.

[0039] Each Clifford gate implemented at a quantum computing device can be compiled from a sequence of measurements of quantum states. According to previous methods for constructing Clifford gates from measurement sequences, a measurement sequence with a minimum length is generated for each of the elementary braiding transformations of each qubit. In such an approach, a minimum-length measurement sequence for a two-qubit entangled gate is then generated for each pair of qubits, and the resulting set of gates is used as a generator gate set to synthesize any other Clifford gates. However, this approach can be inefficient because there may be shorter measurement sequences that compile to the same gate.

[0040] In order to solve the above-mentioned inefficiency problem of the existing methods for compiling Clifford gates in topological quantum computing devices, a method is provided as follows: Figure 1 1. Computing system 10 is shown in an example embodiment of FIG. Computing system 10 may include a processor 12 and a memory 14, which may be operably coupled. Processor 12 and memory 14 may be included in a conventional computing device. Computing system 10 may also include other hardware components, such as one or more input devices, one or more output devices, and / or one or more communication devices. In some embodiments, the functionality of computing system 10 may be distributed across multiple communicatively coupled computing devices.

[0041] As discussed in further detail below, processor 12 may be configured to identify a plurality of measurement sequences 50 that implement logic gate 40. Logic gate 40 may be a single-qubit Clifford gate or a multi-qubit Clifford gate. In some embodiments, as Figure 1 As shown in the example of , the computing system 10 may include a topological quantum computing device 20 having a quantum state 22. Each measurement sequence 50 in a plurality of measurement sequences 50 may include a plurality of measurements 52 of the quantum state 22 of the topological quantum computing device 20. In such an embodiment, the processor 12 may be operably coupled to the topological quantum computing device 20 and may be configured to transmit the one or more measurement sequences 50 to the topological quantum computing device 50 to implement one or more logic gates 40. In some other embodiments, when the computing system 10 does not include the topological quantum computing device 20, the processor 12 may be configured to identify the plurality of measurement sequences 50 for later use with the topological quantum computing device 20.

[0042] The processor 12 may also be configured to determine a respective estimated total resource cost 56 for each measurement sequence 50 in the plurality of measurement sequences 50. The estimated total resource cost 56 for the measurement sequence 50 may, for example, indicate an amount of time or energy estimated to be consumed to implement the logic gate 40 using the measurement sequence 50. Additionally or alternatively, the estimated total resource cost 56 may indicate an error rate for the measurement sequence 50.

[0043] In some embodiments, for each measurement sequence 50 in the plurality of measurement sequences 50, the processor 12 may be configured to determine a corresponding estimated total resource cost 56 52 at least in part by determining an estimated weighted resource cost 54 for each measurement included in the measurement sequence 50. For example, the estimated weighted resource cost 54 for each measurement 52 may indicate an error rate for that measurement 52. The processor 12 may then be further configured to determine an estimated total resource cost 56 for the measurement sequence 50 based on the plurality of estimated weighted resource costs 54 for the individual measurements 52. For example, the estimated total resource cost 56 may be the product of the estimated weighted resource costs 54.

[0044] Once the respective estimated total resource costs 56 for the plurality of measurement sequences 50 have been determined, the processor 12 may be further configured to determine a first measurement sequence 60 having a lowest estimated total resource cost 66 among the plurality of measurement sequences 50. In some embodiments, the processor 12 may be further configured to transmit the first measurement sequence 60 to the topological quantum computing device 20 so that the topological quantum computing device 20 may implement the logic gate 40 by applying the first measurement sequence 60 to the quantum state 22.

[0045] The topological quantum computing device 20 may include one or more Majorana hexacons, such as Figure 1 As shown in . Figure 1 The example shows a first Majorana hexaphon 30A. In some embodiments, the topological quantum computing device 20 may further include a second Majorana hexaphon 30B. Each Majorana hexaphon may include six Majorana zero-energy modes (MZMs). The first Majorana hexaphon 30A includes Majorana zero-energy modes 32A, 32B, 32C, 32D, 32E, and 32F. The second Majorana hexaphon 30B includes Majorana zero-energy modes 32G, 32H, 32I, 32J, 32K, and 32L. In some embodiments, the topological quantum computing device 20 may include more than two Majorana hexaphons.

[0046] exist Figure 2 and Figure 3 An example structure that may be included in a topological quantum computing device 20 to implement one or more qubits is shown in FIG. The topological quantum computing device 20 may instantiate multiple MZMs 32 in a single-sided architecture or a double-sided architecture. Figure 2 An example of a two-sided Majorana hexagram architecture 80 is shown. Figure 2In the embodiment of FIG, the MZMs 32 included in each Majorana hexaconite 30 are coupled via a topological superconductor 70 and a superconductor 72. In each Majorana hexaconite 30, the superconductor 72 is located between a first side 72A and a second side 72B, three MZMs 32 (labeled γ1, γ2, and γ3) are located on the first side 72A, and the other three MZMs 32 (labeled γ4, γ5, and γ6) are located on the second side 72B. Figure 2 The double-sided Majorana hexaconductor architecture 80 includes a plurality of Majorana hexaconductors 30 and further includes a semiconductor 74 located between adjacent Majorana hexaconductors 30 and coupled to a topological superconductor 70. Each MZM 32 may be formed at a junction between the topological superconductor 70 and the semiconductor 74. Figure 2 When the two-sided Majorana hexaphont architecture 80 is used, each Majorana hexaphont 30 may have a square lattice connectivity, wherein each Majorana hexaphont 30 may be entangled with its vertical and horizontal neighbors.

[0047] exist Figure 3 An example of a one-sided Majorana hexaconstruction 82 is shown in FIG. In the one-sided Majorana hexaconstruction 82, each MZM 32 included in the Majorana hexaconstruction 30 is located on the same side of the superconductor 72. Figure 2 In an example embodiment, each MZM 32 may be formed at a junction between a topological superconductor 70 and a semiconductor 74 . Figure 3 Also shown is a close-up view of a portion of semiconductor 74 in a one-sided Majorana hexacondylar architecture 82. Figure 3 In the example of FIG, a plurality of quantum dots 78 are embedded within a semiconductor 74 adjacent to an MZM 32. In addition, a close-up view of the portion of the semiconductor 74 shows a plurality of cutter gates 76 located between the quantum dots 78 and the MZM 32 and between each pair of quantum dots 78. The cutter gates 76 and the quantum dots 78 are described in more detail below.

[0048] exist Figure 3 In a one-sided Majorana hexaton architecture 82, multiple Majorana hexatons 30 can have asymmetric square lattice connectivity, where the one-sided Majorana hexaton architecture 82 does not have vertical reflection symmetry. Therefore, a two-qubit gate acting on a horizontally displaced qubit may have different left- and right-directed operations. If the labeling of the MZM 32 is asymmetric under left-right reflection, it is included in Figure 2 The two-qubit gates in the bilateral Majorana hexaconstruction 80 may also have different leftward and rightward operations.

[0049] In the double-sided Majorana hexaplex architecture 80 and the single-sided Majorana hexaplex architecture 82, each Majorana hexaplex 30 can be galvanically isolated from other Majorana hexaplexes 30. Therefore, each Majorana hexaplex 30 can have a charge energy E generated by the Coulomb interaction. C The charging energy of each Majorana hexaton 30 can reduce the probability of quasiparticle poisoning of the Majorana hexaton 30, because the probability of electron tunneling into or out of the island is proportional to the charging energy E. C is suppressed exponentially with the ratio of temperature, exp(-E C / k B T), where T is the temperature of the Majorana hexaconite 30, and k B is the Boltzmann constant.

[0050] A projection measurement of the joint Fermi parity of any two MZMs 32 can be performed by enabling weakly coherent single-electron tunneling between the MZMs 32 included in the pair and the quantum dots 78 adjacent to those MZMs 32. This coupling induces a shift in the energy spectrum and the charge occupation of the dots, which can then be measured. Such measurements can be topologically protected in the sense that the operator being measured is known to have corrections that are exponentially small in the separation distance of the MZMs 32 in the pair through the superconductor 72 and the topological superconductor 70. However, the measurement fidelity may be limited by the signal-to-noise ratio and decoherence of the qubit.

[0051] In each Majorana hexaplex 30, a qubit can be formed by four MZMs 32. The remaining two MZMs 32 included in the Majorana hexaplex 30 can be used as auxiliary MZMs 32 when performing measurement-based topological operations, as discussed in further detail below. In some other embodiments, in addition to or as an alternative to the Majorana hexaplex 30, the topological quantum computing device can include two Majorana tetraplexes. Figure 4 An example computing system 100 including a topological quantum computing device 120 having a quantum state 122 is shown. Figure 4 The topological quantum computing device 120 includes two Majorana tetraons. Figure 4 In an embodiment, one Majorana quartet is a computational Majorana quartet 130A encoding a computational qubit, while the other Majorana quartet is an auxiliary Majorana quartet 130B encoding an auxiliary qubit. Computational Majorana quartet 130A includes four Majorana zero-energy modes 132A, 132B, 132C, and 132D. Auxiliary Majorana quartet 130B includes Majorana zero-energy modes 132E, 132F, 132G, and 132H. In other embodiments, the topological quantum computing device 120 may include some other number of Majorana quartets.

[0052] In some other embodiments not shown in the figures, the topological quantum computing device 20 may include one or more Majorana octons, each of which includes eight MZMs 30.

[0053] Some measurements 52 on the quantum state 22 may be more difficult to perform than other measurements 52. As discussed above, the difficulty of performing a measurement 52 may be indicated by an estimated weighted resource cost 54 for that measurement 52. Figure 2 In a double-sided Majorana hexaplex architecture 80, some measurements 52 may be performed between MZMs 32 on the same side (left or right) of a Majorana hexaplex 30. Other measurements may be performed between MZMs 32 on opposite sides of a Majorana hexaplex 30. When the MZMs 32 have a greater separation distance, achieving coherent single-electron tunneling between these MZMs 32 and the common quantum dot 78 may be more difficult because the distance between the MZMs 32 may exceed the phase coherence length of the semiconductor 74. Therefore, the estimated weighted resource cost 54 of the measurement 52 may increase as the distance between the MZMs 32 performing the measurement 52 increases. In some embodiments, the Majorana hexaplex 30 may include at least one coherent superconducting link between a pair of non-adjacent MZMs 32 to facilitate coherent single-electron tunneling between the non-adjacent MZMs 32.

[0054] like Figure 2 and Figure 3 As shown in the example of , multiple Majorana hexacons 30 may be included in the topological quantum computing device 20. Multi-qubit operations can be performed by weakly coupling MZMs 32 from different Majorana hexacons 30 to a common quantum dot 78. Due to the weak coupling, the charging energy protection against quasiparticle poisoning may still be effective during such operations. This can be achieved during measurement 52 by performing a charge energy E C The measurement 52 of the commute operator maintains the charge energy E of each Majorana hexagram 30 C These measurements 52 may be those that include an even number of Majorana operators, as discussed in further detail below.

[0055] Each of the six MZMs 32 included in the Majorana hexagram 30 may be labeled with a subscript 1 to 6 and each may be associated with the Majorana Fermi operator γ at the j-th position. j Associated. Operator γ j can each obey the Fermi anticommutative relation {γ j ,γ k}=2δ jk For any ordered MZM 32 pair, j and k, their joint Fermi parity operator is given by iγ j γ k=-iγ k γ j Given, which have eigenvalues ​​p for even parity and odd parity respectively jk =±1. When the topological quantum computing device 20 includes the MZM 32, the Fermi parity of the MZM 32 is the topological charge (also called fusion channel) included in the quantum state 22. In the subspace with parity s=p jk = ±1 and the corresponding projection operator is given by Figure 5 In addition, the joint Fermi parity operator iγ j γ k It is expressed using the positive and negative projection operators in Equation 202. Figure 5 As further shown in FIG, the joint Fermi parity operator and the even and odd parity projection operators can be expressed in a graphical calculus as graphical elements 204, 206, and 208, respectively. The joint Fermi parity operator graphical element 204 can be expressed as a wavy line between two straight lines representing states j and k of the MZM. The joint Fermi parity operator graphical element 204 can also be written as an antisymmetric combination of projectors 206 and 208.

[0056] exist Figure 6 In , Equation 210 shows the ground state of the Majorana hexaton 30. Due to the charging energy of the Majorana hexaton 30, the ground state of the Majorana hexaton 30 is assumed to have a fixed collective Fermi parity value. Figure 6 In the example, the ground states of the Majorana hexaplex 30 each have an even collective Fermi parity p 12 p 34 p 56 = +1. Therefore, the state with odd collective parity is the excited state associated with quasiparticle poisoning. In this way, the low-energy state space of the hexacon is 4-dimensional, and its ground state is as shown in Equation 210. Therefore, the Majorana hexacon 30 can be regarded as a two-qubit system, in which the first qubit is represented by p 34 encoding, and the second qubit is represented by p 12 encoding, where the ground states shown in Equation 210 are |0,0>, |0,1>, |1,0>, and |1,1>, respectively. The joint Fermi parity operator can be expressed in terms of the Pauli operator on two qubits, as shown in Equation 212, where the Pauli matrix is ​​shown in Equation 214.

[0057] According to the convention used herein, the third MZM 32C and the fourth MZM 32D of the Majorana hexagram 30A are used as the hexagrams with joint parity p 34 = +1 auxiliary MZM, and the computational qubit is encoded as p 12 =p 56The ground state of the computational qubit is |0>=|p 12 =p 56 =+> and |1>=|p 12 =p 56 =->. Auxiliary MZMs 32C and 32D and calculation MZMs 32A, 32B, 32E and 32F are specified in Figure 7 The general logical qubit state can be represented by Figure 7 The diagram 218 in is shown where the logical qubit state is represented as a weighted sum of the basis states.

[0058] Single-qubit Clifford gates can be implemented on computational qubits in a topologically protected manner via a "measure-only" braiding protocol. Braiding transformations can be expressed in terms of Majorana operators, such as Figure 8 220 shows the counterclockwise exchange of MZM 32 at positions j and k. Using a measurement-only protocol, a single-qubit Clifford gate can be implemented by sequentially measuring the joint Fermi parity of the MZM pair. These sequential measurements may be subject to the following constraints. First, the first measurement involves exactly one MZM 32 from the auxiliary pair. Second, subsequent measurements involve exactly one MZM 32 from the previously measured pair. Third, the final measurement involves the original auxiliary pair, and the measurement result is equal to the initial joint parity of the auxiliary pair, which is taken to be p 34 = +1, as discussed above. Therefore, the sequential measure corresponds to an anti-easy parity check operator, where if and only if iγ j γ k iγ l γ m =-iγ l γ m iγ j γ k , the measurements of the (jk) and (lm) pairs are allowed to follow each other. Each measurement sequence can be viewed as a sequence of anyonic teleportations, where in each measurement the encoded qubit state is re-encoded in a different set of MZMs 32, and where the measured MZM 32 pair temporarily becomes an auxiliary pair. In this view, the teleportation sequence defines a braiding "path" and enacts the corresponding braiding transformation on the encoded state.

[0059] In some embodiments, the topological quantum computing device 20 can be configured to implement the logic gate 40 at least in part by performing a forced measurement of the projection operator 42 included in the logic gate 40. In such an embodiment, the forced measurement can include performing a joint Fermi parity operator iγ on the quantum state 22. j γ k, as discussed above. Performing the forced measurement may further include determining whether the result of the first measurement is a predetermined target value 44. For example, the predetermined target value 44 may be an initial joint parity of the auxiliary pair. When the result of the first measurement is not the predetermined target value 44, performing the forced measurement may further include repeating a second measurement 52 in the measurement sequence 50 that was performed before the first measurement 52. Repeating the second measurement 52 may reset the quantum state 22 to a state prior to the first measurement 52 in the measurement sequence 50. Performing the forced measurement may further include repeating the first measurement 52 on the joint Fermi parity operator. Thus, the joint Fermi parity operator iγ j γ k The measurement may be repeated until it is measured to be equal to a predetermined target value 44 .

[0060] The sequence of projectors on the Majorana hexagram 30 subject to the above constraints can generate a single-qubit Clifford gate acting on the encoded computational qubit. Figure 8 An example of a measurement sequence 50 is further shown in equation 222, where S is a π / 4 phase gate. When the auxiliary MZM 32 is initialized with positive parity, the initial measurement of the auxiliary pair shown in equation 222 is redundant. As another example, equation 224 shows the gate acting on the qubit where H is a Hadamard gate. The gate set {S,B} is the generating set C1 of all single-qubit Clifford gates.

[0061] Figure 9 An example diagram 226 of a measurement sequence 50 that produces the π / 4 phase gate S discussed above is shown. Figure 9 An example diagram 228 of the measurement sequence 50 for generating the B gate is further shown. The initial measurement of the auxiliary pair is omitted in both diagrams 226 and 228 because it is assumed that the parity of the auxiliary pair is initialized to p 34 =+1.

[0062] Two-qubit gates can be generated from sequences of 2-MZM and / or 4-MZM projection operators. Figure 10 , an auxiliary projection operator for two-qubit operations is defined in equation 230. Two-qubit operations can be performed at two Majorana hexacons 30A and 30B. Here, MZMs 32G, 32H, 32I, 32J, 32K, and 32L included in the second Majorana hexacons 30B are labeled 1′ to 6′ to distinguish them from MZMs 32A, 32B, 32C, 32D, 32E, and 32F included in the first Majorana hexacons 30A. Figure 10 The definition of the auxiliary projection operator for operating on two or more qubits is further shown in Equation 232.

[0063] also, Figure 10 The definition of the parity operator is shown in equation 234. In equation 234, M is the set of 2N MZMs 32 of N Majorana hexacons 30, including two MZMs 32 from each Majorana hexacons 30. Since the number of particles on each Majorana hexacons 30 is preserved, each measurement operator involves an even number of Majorana operators on each Majorana hexacons 30. Figure 10 The definition of the projection operator on the set M is further shown. In Equation 236, s=±1.

[0064] The auxiliary projection operator may begin each measurement sequence 50 when a two-qubit operation is performed. Furthermore, the auxiliary projection operator may end each measurement sequence 50 when a two-qubit operation is performed. In the case of a two-qubit operation, each measurement sequence 50 may also end with the auxiliary projection operator so that both auxiliary pairs end up in their respective initialization states. However, if or Commuting with each entry in the measurement sequence 50, the final measurement of the respective auxiliary pair need not involve the corresponding measurement pair of the MZM 32, since the measurement pair will already be in the final auxiliary state.

[0065] A system of N Majorana hexacons 30 can encode N computational qubits, which are of dimension 2 N A general condition for encoding a measurement sequence 50 involving Fermi parity measurements on N Majorana hexacons 30 into a unitary gate acting on a computational qubit is that the measurements 52 (which can range from 2-MZM to 2N-MZM measurements) do not read information out of the computational state. Thus, the projection operator included in the measurement sequence 50 does not collapse the encoded computational state. Thus, the measurement sequence 50 may not include multiplications to rank less than 2. N Any sequence of projection operators of .

[0066] The relationship between projector sequences and logic gates 40 is many-to-one. A particular projector sequence corresponds to a particular measurement sequence and result (or forced measurement) and is used to generate a gate with a measurement-only protocol, which can be labeled as Figure 11 As shown in Equation 238. In Equation 238, the label M μ is used to denote the allowed set of an even number of MZMs 32 whose joint Fermi parity is projected onto the corresponding parity s at the μth projection in the sequence. μ The resulting single gate acting on the encoded computational state space is Figure 11 is shown in Equation 240.

[0067] In the embodiment where the logic gate 40 is constructed from two Majorana hexagrams 30A and 30B, the Hilbert space of the two Majorana hexagrams 30A and 30B is the tensor product of the Hilbert spaces of the two Majorana hexagrams 30A and 30B. Figure 12 The quantum state 22 formed by the tensor product of the respective states of the first Majorana hexaton 30A and the second Majorana hexaton 30B is shown in equation 242.

[0068] To generate an entangled two-qubit gate, one or more measurements 52 can be performed on the collective Fermi parity of the four MZMs 32. The 4-MZM joint parity projection symbol is Figure 12 244, where measurement 52 is performed on the MZMs 32 labeled j and k from the first Majorana hexaphon 30A and on the MZMs 32 labeled l' and m' from the second Majorana hexaphon 30B. Similar to the 2-MZM joint parity projector shown in Equation 200, the 4-MZM joint parity projector of Equation 236 does not change the total Fermi parity of either Majorana hexaphon 30A or 30B.

[0069] Figure 12 Equation 246 shows an example of a two-qubit entangled gate W. The sequence of projectors that can be measured to obtain gate W is shown in Equation 248. Depending on the measurement result of the projection operator shown in Equation 248, W (when s1s2s3 = +1) or the inverse of W (when s1s2s3 = -1) can be obtained. The first term in the tensor product acts on the auxiliary qubit, and the second term acts on the computation qubit. Since Commuting with each operator included in the measurement sequence 50 of equation 248, the final projection operator acts only on the auxiliary pair of MZMs 32. Equation 250 shows the expansion of the sequence of projection operators shown in equation 248. In equation 250, the auxiliary projection operator is decomposed because it commutes with every other projection operator in the measurement sequence 50 .

[0070] The gate set {S, B, W}, where a single-qubit gate can act on any qubit and a two-qubit gate can act on any nearest-neighbor qubit pair, can generate any N-qubit Clifford gate C. N For example, the controlled Z gate can be obtained as And a controlled NOT gate can be obtained from C(Z) by conjugating the second qubit by H = SBS. Therefore, since {S, B, C(Z)} generates the entire set of N-qubit Clifford gates for any N, so can the gate set {S, B, W}.

[0071] As discussed above, some measurements 52 may be more difficult to perform than other measurements 52. These differences in measurement difficulty may include differences in the error rate of the measurements 52. Additionally or alternatively, other factors may be used to determine the difficulty of a measurement 52. The error rate of a measurement 52 may be affected by the distance between the MZMs 32 on which the measurement 52 is performed. In some embodiments, the difficulty of a measurement 52 may be lower when the measured MZMs 32 are closer to each other in the lattice. The processor 12 may be configured to assign a corresponding estimated weighted resource cost 54 to the measurement 52 to account for these differences in difficulty.

[0072] exist Figure 2 The bilateral Majorana hexapod structure 80 and Figure 3 In the one-sided Majorana hexaplex architecture 82 , measurement 52 is performed by coupling the MZM 32 to the quantum dot 78 . Figures 14A-14C Three example Fermi parity measurement configurations 300, 302, and 304 are shown. Figures 14A-14C In the example shown in FIG, the coupling between Majorana hexaconite 30 and quantum dot 78 forms an interference loop bounded by a path connecting MZM 32 via Majorana hexaconite 30 and a path connecting MZM 32 via quantum dot 78. To select the interference path, electrostatic depletion gates are provided to allow different portions of the semiconductor to be connected or disconnected. These gates are referred to as cutting gates 76.

[0073] Each cut gate 76 opened to form the semiconductor quantum dot configuration can increase the difficulty because the number of cut gates 76 opened to achieve quantum dot 78 affects the size of quantum dot 78. As the number of cut gates 76 opened increases, the coherence of quantum dot 78 can decrease, adding a source of noise to the measurement. In addition, the total length of the semiconductor path can affect the phase coherence, and the volume of the semiconductor region enclosed by the path can affect the properties of quantum dot 78, such as its charge energy and energy level spacing. Measurements are generally easier to perform with smaller quantum dots 78.

[0074] The plurality of cutting gates 76 included in the semiconductor path may include one or more vertical cutting gates 76A. The plurality of cutting gates 76 may also include one or more horizontal cutting gates 76B. Figure 14A In the Fermi parity measurement configuration 302, the semiconductor path includes two vertically cut gates 76A; Figure 14B In the Fermi parity measurement configuration 304 of , the semiconductor path includes seven vertically cut gates 76A; and Figure 14C In the Fermi parity measurement configuration 306 , the semiconductor path includes one vertical cut gate 76A. In some embodiments, the length of the semiconductor path may be proportional to the number of vertical cut gates 76A included in the semiconductor path.

[0075] Wherever the MZM 32 is coupled to the semiconductor 74, the coupling can be tuned by the cut gates 76 that form the tunnel junctions 330. In contrast to the cut gates 76 between semiconductor regions, which are typically fully open or closed, each tunnel junction 330 can be tuned so that the coupling energy of the tunnel junction 330 is proportional to the charging energy E of the MZM 32. C The ratio is within a range where the effect of the MZM state on quantum dot 78 can be quickly and reliably measured, while not suppressing the charging energy of quantum dot 78 and increasing the probability of quasiparticle poisoning. Generally, the visibility of the signal decreases with each additional tunnel junction 330. Each tunnel junction 330 between quantum dot 78 and MZM 32 involved in measurement 52 has an associated tunneling amplitude. A reduction in tunneling amplitude may reduce the visibility of the measurement because reducing the tunneling amplitude may result in a smaller energy splitting between states. This reduction in the visibility of measurement 52 may increase the measurement time and / or reduce the accuracy of measurement 52.

[0076] Furthermore, noise in tunnel junction 330 may interfere with the measurement signal. As part of the measurement protocol, the coupling between MZM 32 and semiconductor 74 may be tuned from zero to its target value on a timescale shorter than that of measurement 52 but slower than the timescale on which non-adiabatic corrections would occur.

[0077] The number of tunnel junctions 330 involved in the measurement 52 may be equal to the number of MZMs 32 involved in the measurement 52 , since a tunnel junction 330 may be provided for each MZM 32 . Figure 14A The Fermi parity measurement configuration 302 includes two tunnel junctions 330, Figure 14B The Fermi parity measurement configuration 304 includes four tunnel junctions 330, and Figure 14C The Fermi parity measurement configuration 306 also includes four tunnel junctions 330 .

[0078] Fluctuations in the background magnetic field may be another source of noise in the measurement. The contribution of these fluctuations to the noise may be proportional to the area enclosed by the interference ring defined by the architecture of the topological quantum computing device 20 and the geometry of a given measurement 52. In some embodiments, the hexapod architecture geometry may be such that the relevant area for such errors may be approximately divided into integer multiples of the unit area 340. Figure 14A In the Fermi parity measurement configuration 302, the area of ​​the semiconductor path is twice the unit area 340; Figure 14B In the Fermi parity measurement configuration 304, the area of ​​the semiconductor path is seven times the unit area 340; and Figure 14C In the Fermi parity measurement configuration 306 , the area of ​​the semiconductor path is three times the unit area 340 .

[0079] The difficulty of measurement 52 may also depend on the number of Majorana hexacons 30 involved in measurement 52. This is because measurement visibility may be affected by how accurately the quantum state 22 can be tuned to the degenerate tunneling point. In addition, the operations utilized in measurement 52 may result in errors in migrating the MZM 32 between different Majorana hexacons 30. Increasing the number of Majorana hexacons 30 involved in measurement 52 may increase the probability of such errors.

[0080] In view of the above factors, Figure 14A The estimated weighted resource cost 54 of the 2N-MZM measurement 52 involving N Majorana hexagrams 30 is shown in equation 306. In equation 306, n c is the number of vertical cutting doors 76 opened for measurement, n a is the area enclosed by the interferometric ring defined by measurement 52 (expressed as an integer multiple of the unit area), and n t is the number of tunnel junctions involved in the measurement 52. The number w c 、w a and w t are respectively c 、n a and n t The weight w associated with the tunnel junction t The contribution from the horizontal cutting gate 76B may also be included, since the horizontal cutting gate 76B may be used to control tunneling. The effect of the number N of Majorana hexacons 30 on the estimated weighted resource cost 54 is denoted as f(N). c 、w a and w t Each of can be determined experimentally for the particular topological quantum computing device 20 performing measurement 52.

[0081] Figures 15A-15E Example Fermi parity measurement configurations 310, 312, 314, 316, and 318 are shown, which may be used with Figure 3 The unilateral Majorana hexapod architecture 82 shown in FIG. Figure 15A The Fermi parity measurement configuration 310 has three vertically cut gates 76A, two tunnel junctions 330 , and an interferometer ring that encloses an area three times that of the unit area 340 . Figure 15B The Fermi parity measurement configuration 312 has three vertically cut gates 76A, four tunnel junctions 330 , and an interferometer ring that encloses an area five times that of the unit area 340 . Figure 15CThe Fermi parity measurement configuration 314 has zero vertically cut gates 76A, four tunnel junctions 330 , and an interference ring that encloses an area that is twice the unit area 340 . Figure 15D The Fermi parity measurement configuration 316 has two vertically cut gates 76A, eight tunnel junctions 330 , and an interferometer ring that is six times the area of ​​the enclosed unit area 340 . Figure 15E The Fermi parity measurement configuration 318 has four vertically cut gates 76A, eight tunnel junctions 330 , and an interferometer ring that encloses an area four times that of the unit area 340 . Figures 15B-15E Example Fermi parity measurement configurations 312 , 314 , 316 , and 318 are configurations corresponding to measuring 52 in an upward direction, a downward direction, a rightward direction, and a leftward direction, respectively.

[0082] Thus far, the MZMs 32 in the Majorana hexaplex 30 have been labeled 1, ..., 6 and have been assigned roles in measurements 52 according to these labels. For example, in the computational basis, the MZMs 32 labeled 3 and 4 serve as an auxiliary pair, while MZMs 1, 2, 5, and 6 collectively encode the computational qubit. However, the six labels may be assigned to the physical MZMs 32 of the Majorana hexaplex 30 according to other labeling schemes. The choice of labeling scheme may affect the difficulty 52 of the measurement, as discussed below. In some embodiments, the processor 12 may be configured to determine an estimated total resource cost 56 of at least one measurement sequence 50 at least in part by relabeling the MZMs 32 included in the Majorana hexaplex 30 to change which MZMs 32 are included in the computational qubit and which MZMs 32 are included in the auxiliary qubit. In embodiments where the topological quantum computing device 20 includes one or more Majorana quartets 130 or Majorana octons, the MZMs 32 included in the Majorana quartet 130 or Majorana octon can also be relabeled to change which MZMs 32 are included in computational qubits and which MZMs 32 are included in auxiliary qubits.

[0083] In the following example, let<a,b,c,d,e,f> The configuration of the MZM 32 within the Majorana hexagram 30 is indicated, where for a single-sided Majorana hexagram, the marking is from top to bottom, as shown in FIG. Figure 3 As shown in ; and for the bilateral Majorana hexapods, the marking is carried out counterclockwise from the upper left corner to the upper right corner, as shown in Figure 2As discussed above, one possible configuration for either Majorana hexaplex architecture is <1,2,3,4,5,6>. Here, MZM 1 and MZM 6 are located at opposite ends of Majorana hexaplex 30. On the other hand, in the configuration <1,6,2,3,4,5>, MZM 1 and MZM 6 are adjacent. Therefore, different configurations of MZMs 30 will result in different assignments of estimated weighted resource costs 54 to measurements 52. For example, the measurements of MZM 1 and MZM 6 may have w(16) <1,6,2,3,4,5> and w(16) <1,2,3,4,5,6> The estimated weighted resource cost 54 of the configuration <1,6,2,3,4,5> may be higher. If the measurement 52 occurs frequently in the measurement sequence 52, then using the configuration <1,6,2,3,4,5> is less resource intensive. Furthermore, measurements 52 involving pairs that are neighbors in different directions may have different estimated weighted resource costs 54. For example, in a one-sided Majorana hexapod architecture 82, measurements 52 connecting vertical neighbors may be less resource intensive than measurements 52 connecting horizontal neighbors.

[0084] The bilateral Majorana hexagram framework 80 and the unilateral Majorana hexagram framework 82 each have symmetric relationships that can reduce the number of labeled configurations to be evaluated. The bilateral Majorana hexagram has horizontal and vertical reflection symmetry, which reduces the number of unequal configurations from 6! = 720 to 180. The unilateral Majorana hexagram has vertical reflection symmetry, which reduces the number of unequal configurations from 720 to 360.

[0085] To make the implementation of the logic gate 40 scalable, the complete array of Majorana hexacons 30 in the topological quantum computing device 20 can utilize a labeling configuration that is periodic in the array. In some embodiments, each Majorana hexacons 30 in the array can use the same labeling configuration. However, in other embodiments, different configurations can be assigned to different Majorana hexacons 30. For example, the array can include a first configuration for all right-facing, one-sided Majorana hexacons 30 and a second configuration for all left-facing, one-sided Majorana hexacons 30.

[0086] In some embodiments, the topological quantum computing device 20 can be configured to implement the logic gate 40 at least in part by performing a forced measurement on the projection operator 42 included in the logic gate 40. The forced measurement can include performing a joint Fermi parity operator Γ on the quantum state 22. M The first measurement 52. When the joint Fermi parity operator Γ of an ordered set of M MZMs 32 is measured in a system of pure states |Ψ> M When Figure 16AThe probability shown in equation 400 in FIG. 5 is used to obtain the measurement result s = ±. When this measurement 52 is performed, the measured state shown in equation 402 is obtained. For a general state described by the density matrix p, the measurement result s can be obtained with the probability shown in equation 404. The measured state of the general state described by the density matrix p is shown in equation 406.

[0087] The forced measurement may also include determining whether the result of the first measurement 52 is a predetermined target value 44. Since the predetermined target value 44 of s is not always obtained when performing the first measurement 52, the projection operator 42 with the target parity is not always obtained. In order to obtain the target projection operator in the measurement-only scheme A "forced measurement" process that repeats until successful can be used. The joint Fermi parity operator iγ j γ k When the de measurement is performed, the probability of obtaining the target parity may be 1 / 2. The initial measurement 52 of the auxiliary pair of MZM 32 may have a deterministic result. j γ k When the result of the first measurement 52 is not the predetermined target value 44, the forced measurement may further include resetting the quantum state 22 to the state before the first measurement 52. The quantum state 22 may be reset by performing a parity measurement on a pair of MZMs measured in the second measurement 52 performed before the first measurement 52.

[0088] After resetting the quantum state 22, performing forced measurement may further include: repeatedly performing forced measurement on the joint Fermi parity operator iγ j γ k If the repetition of the first measurement 52 also does not return the predetermined target value 44 of the parity check, the above steps can be repeated. j γ k May be measured and reset until the measurement 52 returns to the predetermined target value 44 .

[0089] Figure 16BA flow chart of an example method 408 by which a forced measurement may be performed is shown. At step 410, method 408 may include performing a measurement 52 of a joint Fermi parity operator of the quantum state. At step 412, method 408 may also include determining whether the result of measurement 52 is a predetermined target value 44 for parity. If the result of measurement 52 is not the predetermined target value 44, method 408 may include resetting quantum state 22 at step 414. Method 408 may then return to step 410. If the result of measurement 52 is the predetermined target value 44, method 408 may also include, at step 416, using a projection operator having the predetermined target value 44 in measurement sequence 50.

[0090] An example in which forced measurements are used to obtain a measurement sequence 50 is Figures 17A-17C is shown in Figures 17A-17C In the example, the S gate is a sequence of projection operators The diagram 418 for this sequence of projection symbols is generated. Figure 17A is shown in Figures 17A-17C In the example, the measurement result of iγ1γ3 is the target value 44 of s1 = +, but the measurement result of iγ2γ3 is the undesirable value s2 = -, as shown in FIG. Figure 17B As shown in the diagram 420 in FIG. Figure 17C As shown in diagram 422 of FIGURE 4, the measurement of iγ1γ3 can be repeated. Regardless of the result of this repeated measurement, quantum state 22 is reset. The measurement of iγ2γ3 can then be repeated, with another 1 / 2 probability of obtaining the predetermined target result s2 = -. If an undesirable measurement result is obtained again, the above steps can be repeated until the predetermined target result is obtained. As indicated in equation 426, the measurement sequence 50 depicted in diagram 422 differs from the measurement sequence 50 depicted in diagram 424 only in the overall phase.

[0091] To distinguish between the application of forced measurement operations and projection symbols associated with physical measurements, Figure 18 The application of this forced measurement to the MZM pair (jk) in the sequence after the measurement of the pair (kl) is indicated in equation 428. In equation 428, the expected measurement result s is obtained at the nth attempt. In addition, for a=1, ..., n-1, s a ≠s, and the measurement result r a It's irrelevant.

[0092] In some embodiments, the estimated total resource cost 56 of the forced measurement sequence of equation 428 may be given by equation 430. The estimated total resource cost 56 provided in equation 430 is equal to the equation comprising <n>= Estimated total resource cost 56 of the measurement sequence 50 for the average case of 2 attempts.

[0093] As an alternative to the forced measurement process discussed above, the following process can be used to obtain the predetermined target value 44 of the measurement 52. When the measurement 52 of the MZM pair (jk) following the measurement 52 of the MZM pair (kl) produces an undesirable result, rather than resetting the quantum state 22 by repeating the previous measurement 52 of the pair (kl), the quantum state 22 can be reset by measuring the MZM pair (jl). Thus, in the alternative forced measurement protocol, resetting the quantum state 22 can include measuring an MZM pair including a first MZM 30 (labeled above as j) on which the first measurement 52 was performed. The MZM pair also includes a second MZM 30 (labeled above as l) on which a second measurement 52 is performed, the second measurement 52 being performed before the first measurement 52 in the measurement sequence 50. However, unlike the first forced measurement protocol discussed above, the second measurement 52 is not performed on the first MZM 30 in the MZM pair.

[0094] More generally, and not specifically with respect to a topological quantum computing device 20 including an MZM 32, resetting the quantum state 22 according to an alternative forced measurement protocol includes measuring a plurality of topological charges. The plurality of topological charges includes a symmetric difference of a first plurality of topological charges and a second plurality of topological charges, a first measurement 52 being performed on the first plurality of topological charges, and a second measurement 52 being performed prior to the first measurement 52 in a sequence of measurements 50 of the second plurality of topological charges. The "symmetric difference" is defined as the union of two sets minus the intersection of the two sets.

[0095] When the measurement results of the MZM (36) are unexpected, an alternative forced measurement method is used. Figures 19A-19B Projection symbol sequence Shown diagrammatically. Figure 19A At diagram 432 a sequence of projection symbols is shown after an undesired measurement result s3=− has occurred. Figure 19A The first forced measurement sequence is further illustrated in diagram 434 . Figure 19B In diagram 436 is shown a diagram which can be used as Figure 19A Alternatively, the second mandatory measurement sequence Figure 19B As shown in equation 438 in FIG, the projector sequence shown in diagram 436 is the same as the projector sequence Differ only in the overall constant.

[0096] In order to distinguish the alternative forced measurement protocol from the first forced measurement protocol (and from the ordinary projection symbol), this alternative forced measurement protocol applied to the MZM pair (jk) after the measurement 52 of the MZM pair (kl) is Figure 20 is defined in equation 440. In equation 440, for a=1,…,n-1, s a ≠s, and the measurement result p a As in the first forced measurement protocol discussed above, the estimated total resource cost 56 of the forced measurement sequence of equation 440 may be the geometric mean of the weighted estimated resource costs 54 of the measurements 52 in the measurement sequence 50. The estimated total resource cost 56 may be equal to the weighted average of the weighted averages 54 of the weighted averages 54 of the weighted averages 52 in the measurement sequence 50. <n>= the difficulty weight of the measurement sequence 50 for the average case of 2 attempts. In such an embodiment, the estimated total resource cost 56 is Figure 20 442. In embodiments where the parity measurement of MZM(jl) has a lower weighted estimated resource cost 54 than the measurement of MZM(kl), the alternative forced measurement protocol may be less resource intensive than the first forced measurement protocol.

[0097] Reference below Figure 21 and Figure 22 Mandatory measurement protocols for 2N-MZM measurements, in particular 4-MZM measurements, are discussed. These mandatory measurement protocols can also be used for 2-MZM measurements following 4-MZM measurements. Figure 21 Equation 444 of shows a condition under which, for certain choices of M3, the forced measurement of M2 follows the measurement of M1. As another condition for performing forced measurement on M2, the subsequent projection operators in the measurement sequence 50 may not commute with each other. and , the condition is met.

[0098] Another form of the left side of equation 444 is Figure 21 Equation 446 shows that. Equation 448 further shows the conditions under which Equation 444 holds. Under the conditions given in Equation 448, Can be replaced by a constant. Figure 21 A generalization of the two different forced measurement protocols described above is provided. The second condition shown in Equation 448 can result in invalid measurement sequences that collapse the qubit state or, if M1 and M2 each include more than two elements, result in measurements greater than 2N-MZM. Because the estimated total resource cost 56 increases rapidly with the number of MZMs 32, it is preferable to avoid having to measure such sequences. However, when the first condition of Equation 448 is met, this problem does not arise.

[0099] Figure 22 Equation 450 shows four example mandatory measurement protocols for a measurement sequence 50 involving four MZMs 32. Furthermore, equation 452 shows the corresponding estimated total resource cost 56 for the measurement sequence 50 of equation 450, according to one embodiment.

[0100] The forced measurement protocols discussed above provide control over which Fermi parities are projected onto at each measurement 52 in a measurement sequence 50. These forced measurement protocols allow for a projector sequence that generates a specified target logic gate 40. The forced measurement protocol can be applied to each projector in a given projector sequence. However, such a strategy can be inefficient because different projectors in a measurement sequence 50 can have correlated effects on the resulting logic gate 40. When determining an estimated total resource cost 56 for a measurement sequence, the processor 12 can also be configured to determine which projectors in the measurement sequence 50 have correlated effects, and therefore, which specific measurements 52 can tolerate any outcome and which measurements 52 may have to be forced in order to obtain the logic gate 40. In such an embodiment, the processor 12 can be configured to determine the corresponding estimated total resource cost 56 for each measurement sequence 50 at least in part by identifying one or more measurement sequences 50 that differ in their overall Pauli operator, as discussed in further detail below.

[0101] return Figure 6 , Equation 212 shows the joint Fermi parity operator iγ expressed in terms of the Pauli operator shown in Equation 214 j γ k In addition, if Figure 5 As shown in , the projection operator can be drawn as a hat and cup, connected by a wavy line if s = - and unconnected if s = +. For each s = - projection symbol in the measurement sequence, the corresponding Fermi line (which terminates on two MZM lines) can be moved to the top of the diagram using the diagram rules. Each such Fermi line that has been slid to the top of the diagram simply connects the two MZM lines j and k, resulting in the joint Fermi parity operator iγ j γ k In which each measurement sequence is In the embodiment where the measurement starts and ends with forced measurement, the Fermi line is not connected to the auxiliary MZM line when pushed to the top of the diagram. Therefore, in such an embodiment, j and k do not correspond to the auxiliary MZM 32.

[0102] Now turn Figure 23 , the Fermi lines that slide to the top of the diagram correspond to the Pauli operators shown in table 500. The complete computation of the effect of a measurement sequence 50 on operator space can be a braiding transformation (and therefore a Clifford gate) determined by which MZMs 32 are measured in the measurement sequence 50, followed by a Pauli gate determined by the measurement results. Figure 23 Equation 502 shows a sequence of single hexon projectors compiled into a Clifford gate G. In Equation 502, the projection channel parity s μ need not all be positive. Equation 504 shows the single hexon projector sequence of Equation 502 when the corresponding parities of all projector operators have been set to positive. Equation 502 can be rewritten as Equation 506, where q is the number of projector operators with negative parity in Equation 502, p is an integer, and P is the Pauli gate. Therefore, the measurement result s in the single hexon projector sequence is μ The effect is to change the resulting logic gate 40 by at most one Pauli gate.

[0103] Figure 24A The sequence of projection operators that can be used to implement any of the Pauli gates is shown in Equation 508. In Equation 508, the resulting Pauli gate P is independent of s1 and s4. Figures 24A-24B This independence is illustrated by diagram 510, which is similar to Figure 24B The difference between diagrams 512 and 514 is only in the overall phase. The isotopes of the MZM lines allow them to be straightened, leaving no non-trivial braiding in diagram 514. Therefore, P + =1, where P + is when all the measurement results s in equation 508 μ = +. In addition, Figures 24A-24B In the example, both ends of the s1 line are connected to the j=5MZM line when straightened, and both ends of the s4 line are connected to the j=1MZM line when straightened, which allows the lines s1 and s4 to be removed without affecting the resulting logic gate 40. μ After the line slides to the top of the diagram, s2 = -contribution operator s3=-contribution operator And s5 = -contribution operator Therefore, the compiled Pauli gate is as shown in equation 508.

[0104] For multi-hexon projector sequences, change the projection channel parity s μ The resulting logic gate 40 is also changed to a multi-qubit Pauli gate at most. In addition, by tracking the projection channel parity s μ The processor 12 may be configured to determine one or more measurements 52 in the measurement sequence 50 for which to perform forced measurements to determine the effect on the resulting compiled gates. For a single hexon projector sequence, when all Fermi lines in the projector sequence are moved to the top of the diagram, each line may be removed or replaced with the Fermi parity operator iγ listed in Table 500. j γ k 506. In this way, the specific Pauli operator that a given measurement contributes to P in the decomposition shown in equation 506 can be determined. Thus, any Clifford gate can be generated from a measurement sequence 50 where three or fewer measurements 52 in the measurement sequence 50 are forced measurements. Of these three or fewer forced measurements, one forced measurement can be used to assign positive parity to the auxiliary pair of MZMs 32, and the other two or fewer forced measurements can be used to obtain the target Pauli gate. For example, by appropriately selecting s2 and s5 via forced measurements, Figures 24A-24B The measurement sequence 50 can generate a specific target Pauli gate for any value of s1, s3 and s4.

[0105] Another approach is described below, which can be used in addition to or as an alternative to forced measurements in topological quantum computations. In this approach, known as Majorana-Pauli tracking, measurements that only change the braiding transformations produced by Pauli gates can be tracked. More generally, a similar tracking strategy can be employed when the measurement results are Abelian anyons. Majorana-Pauli tracking can allow for the use of fewer physical measurement operations and can allow for the use of deterministic measurement sequences 50 for topological gate operations.

[0106] Figure 25 The construction of a measurement sequence 50 compiled as a gate G acting on the computational state space in a system 32 of N Majorana hexacons is shown. First, in equation 516, an auxiliary projection operator 516 is defined for the N hexacons system. Furthermore, equation 518 introduces an inverse operator that flips the state of each auxiliary qubit whose initial and final projections are different. In equation 518, γ a,j is the ath MZM 32 of the jth Majorana hexagram 30. In equation 520, the auxiliary projection operator of equation 516 is expressed using the inverse operator of equation 518. Equation 522 provides a measurement sequence 522 by which the gate G is compiled according to the Majorana-Pauli tracking protocol with the operators defined in equations 516, 518, and 520. The operator G shown in equation 522 is a single operator and therefore does not reduce the rank of the operator space.

[0107] When Majorana-Pauli tracking is used, instead of the convention p used with the forced measurement protocol 34 =+1,p 34 Can take positive or negative values. 34 The value of may change during the process of generating a measurement-only gate. As in the forced-measurement protocol, the computation qubit is represented by p 12 Therefore, when the collective Fermi parity of Majorana hexaplex 30 is even, the residual parity p 56 The corresponding parity check of the other two pairs is calculated according to p 56 =p 12 p 34 For the Majorana hexaplex 30, which may have an even or odd collective Fermi parity p h In the general case, parity check p 56 By p 56 =p 12 p 34 p h given.

[0108] As shown in equation 524, an N-qubit Pauli operator can be applied to gate G of equation 522 to produce the same gate with a different projection sequence. Therefore, if only a measurement sequence of measurement 52 is performed to obtain logic gate 40 and the measurement results are tracked, the resulting logic gate 40 will have a known Pauli gate correction. If the non-Clifford gate utilized in the quantum computation is a single-qubit phase gate (in any Pauli basis), the Pauli gate correction can be implemented by at most a phase gate with a Clifford gate correction. When Clifford gate correction is performed, the Clifford gate of logic gate 40 that is different from the target logic gate can be tracked as the measurement sequence 50 is executed. In such an embodiment, the Clifford gate correction can be handled by updating subsequent Clifford gates in the computation. Such Clifford corrections are typically used when implementing non-Clifford phase gates by injecting states. Therefore, the impact of Clifford corrections on performance will be minimal.

[0109] Discussed below are methods by which the processor 12 may also be configured to determine a first measurement sequence 60 having a lowest estimated total resource cost 66 among a plurality of measurement sequences 50. The lowest estimated total resource cost 66 may be a global minimum estimated total resource cost 66 over all measurement sequences 50 that implement the logic gate 40, or alternatively may be the minimum estimated total resource cost of a subset of all such measurement sequences 50 that the processor 12 searches.

[0110] When performing a topological quantum computation using multiple different logic gates 40, the processor 12 can be configured to select the lowest estimated total resource cost 66 for a subset of the multiple different logic gates 40. In quantum computation, all logic gates 40 involved in the computation may not always be implementable using their corresponding first measurement sequences 60. In some embodiments, the first measurement sequence 60 may be used for one or more logic gates 40 that are used very frequently in topological quantum computation. For example, the one or more logic gates 40 for which the first measurement sequence 60 is determined may be controlled Pauli gates, Hadamard gates, or all single-qubit Clifford gates.

[0111] When the processor 12 searches for the first measurement sequence 60, the processor 12 may perform the search on the measurement sequence 50 used in the Majorana-Pauli tracking protocol or the forced measurement protocol. The determination of the first measurement sequence 60 with the lowest estimated total resource cost 66 is first discussed herein for the Majorana-Pauli tracking protocol. When the measurement sequence 50 is compiled according to the projector sequence shown in equation 522, the physical measurement sequence to be performed is the sequence M1, ..., M specified in the projector sequence. n When the physical measurement result is consistent with the specified projection channel s μ When there is a mismatch, the resulting gate differs from G by at most one Pauli gate, which may be tracked and compensated for at a later time. Thus, a measurement-only implementation of G may be assigned Figure 26 The estimated total resource cost 56 is shown in equation 526.

[0112] When Majorana–Pauli tracing is exploited, Clifford gates can be grouped into Pauli cosets, given by the union of Clifford gates that is equivalent to multiplying the overall multi-qubit Pauli gate. The Pauli coset of an N-qubit Clifford gate G is given by Figure 26 is defined in Equation 528 of . When using Majorana-Pauli tracking, it is not necessary to generate every Clifford gate. Instead, a Clifford gate can be generated for each Pauli coset, because the differences in Pauli gates are handled by the tracking protocol. Therefore, in some embodiments, the easiest-to-implement Clifford gate in a given Pauli coset can be used to implement an entire class of Clifford gates. Therefore, when any Clifford gate in that Pauli coset is called in a computation, the element of each Pauli coset with the lowest estimated total resource cost 66 can be used.

[0113] When using the forced measurement protocol instead, the measurement sequence 50 for compiling gate G can be written as Figure 27 As shown in equation 530 of FIG. Upon determining the first measurement sequence 60 with the lowest estimated total resource cost 66, the processor 12 can be configured to determine the minimum number of projector symbols required to generate a forced measurement for gate G with the forced measurement protocol. The projector symbol sequence can then be converted into a measurement sequence 50 by utilizing a forced measurement for each projector symbol requiring a forced measurement. Standard measurements can be performed on the remaining projector symbols. For each projector symbol for which a forced measurement is performed, the forced measurement protocol used of the two forced measurement protocols described above can be the one with the lower estimated weighted resource cost 54 for the forced measurement.

[0114] When a forced measurement protocol is used, the estimated total resource cost 56 of the measurement sequence 50 can be determined by taking the geometric mean of the possible total resource costs of the measurement sequence 50. Figure 27 As shown in Equation 532 of , this geometric mean can be obtained by starting with the expression for the difficulty weights of the projector sequence from Equation 430 and replacing the weights of the forced projectors with the average difficulty weight corresponding to the forced measurement protocol used. In Equation 532, F1 is the set of projectors in the sequence to be implemented by the first type of forced measurement, and F2 is the set of projectors in the sequence to be implemented by the second type of forced measurement.

[0115] When searching for a measurement sequence 50 that can be used to implement the logic gate 40, the processor 12 can be configured to determine which measurement sequences 50 do not collapse the computational state. For a single-qubit gate, such a measurement sequence 50 can satisfy the following condition: consecutive 2-MZM measurements must have exactly one common MZM 32. Under such a condition, each measurement step can involve selecting one MZM 32 from the previous measurement pair and one MZM 32 from the four remaining MZMs 32, resulting in eight possible measurements 52 to choose from. The nth measurement 52 in the measurement sequence 50 can be constrained to be a measurement of the auxiliary pair (3, 4) of MZMs 32. In addition, the penultimate measurement 52 can be constrained to involve one MZM 32 in the previous pair and one MZM 32 in the auxiliary pair. Thus, there can be four available choices for the penultimate measurement 52. The size of the search space for a single hexagram measurement sequence of length n can be 2 3n-4 Even though this scaling is exponential in n, for single-qubit gates the value of n in the first measurement sequence 60 with the lowest estimated total resource cost 66 is typically low.

[0116] Once one or more measurement sequences 50 are determined that produce the target logic gate 40 without collapsing the computational state, the target logic gate 40 can be generated for all possible measurement results s. μ The resulting logic gate G is evaluated. In some embodiments, the processor 12 may be configured to perform a brute force search by determining a corresponding estimated total resource cost 54 for each measurement sequence 50 that implements the target logic gate 40 and is shorter than a predetermined length 58. For example, the predetermined length 58 may be n=9.

[0117] The example provided below discusses determining a first measurement sequence 60 and a minimum estimated total resource cost 66 for a set {C(X), C(Y), C(Z)} of controlled Pauli gates and a SWAP gate, which are examples of two-qubit Clifford gates. The quantum state 22 of two Majorana hexacons 30 has 510 different non-trivial Fermi parity projectors. In some embodiments, each of the non-trivial Fermi parity projectors can be tested at each measurement step to determine which projectors do not collapse the computational state. In such an embodiment, the processor 12 can be configured to diagonalize the projector sequence after each addition of a projector. When the projector sequence has been diagonalized, the processor 12 can also be configured to discard the projector sequence if the projector sequence collapses the computational state. However, performing the diagonalization of the projector sequence can be computationally expensive.

[0118] Alternatively, for smaller values ​​of n, each of the 510 possible parity projectors can be applied to each step in the projector sequence. The resulting logic gate 40 generated by the projector sequence can then be checked. In an example in which a corresponding first measurement sequence 60 is determined for each of the controlled Pauli gates, the projector sequence that generates the controlled Pauli gates can include at least four projectors. In this example, a search can be performed for each measurement sequence 50 of a predetermined length 58 up to n=4.

[0119] Additionally or alternatively, every possible sequence of projectors comprising a 4-MZM projector may be searched for controlled Pauli gates, up to some predetermined length 58. For example, the predetermined length 58 may be n=5.

[0120] Each projector sequence that compiles to a SWAP gate includes at least two 4-MZM projectors. A search for two 4-MZM projectors can be performed for projector sequences of a predetermined length 58 up to n=4. For a single-sided Majorana hexaconstruction 82, no projector sequence that compiles to a SWAP gate is found for this predetermined length 58. Alternatively, a projector sequence that compiles to a SWAP gate can be formed from a plurality of controlled NOT gates.

[0121] For a two-qubit measurement sequence 50 compiled into a target logic gate 40, it is possible to μ The measurement sequence 50 is evaluated. For each possible projection channel s μ Evaluating each measurement sequence 50 may provide a Pauli correction gate that may be used in a Majorana-Pauli tracking protocol and may also identify the projector for which a forced measurement is performed in a forced measurement protocol.

[0122] Correlations between the remaining measurement results can then be identified. Such correlations can be determined starting from a first projection symbol without a fixed projection channel, which is denoted as s v . We can consider s separately. v = + 1 and s v = -1. Within each subset, the processor 12 may be configured to check whether any subsequent measurement 50 has a fixed result. If a subsequent measurement 50 has a fixed result, the measurement 50 may be forced to correspond to s v If measurement 50 does not have a fixed result, the projection channel of the measurement can be used to replace s. v Apply the above steps recursively.

[0123] In one example of compiling a two-qubit gate from a measurement sequence 50, when s2 = + and s3 = s1, the sequence Compiles to a controlled NOT gate. Therefore, the projection operator sequence and The same logic gate 40 is produced. In this example, forced measurements can be performed for μ=2,3,4.

[0124] In one example of identifying the first measurement sequence 60, the weighting factor w c =1.25, w a =1.01, w t = 1.65 and (N) = (N!) N-1 can be used in equation 306. In this example, when forced measurement or Majorana-Pauli tracking is used with the two-sided Majorana hexaconstruction architecture 80, the MZM tag configuration <3,4,1,2,6,5> produces the lowest estimated total resource cost 66 for each of the single-qubit Hadamard gates, the geometric mean of all single-qubit Clifford gates, the geometric mean of controlled NOT gates acting in all four directions, and the geometric mean of controlled Pauli gates acting in all four directions. For the one-sided Majorana hexaconstruction 82, when forced measurement is used, the MZM tag configuration <1,2,6,3,4,5> yields the lowest estimated total resource cost 66 for the geometric mean of the Hadamard gates and all single-qubit Clifford gates, and the MZM tag configuration <3,4,1,2,6,5> yields the lowest estimated total resource cost 66 for the geometric mean of the controlled NOT gates acting in all four directions and the geometric mean of the controlled Pauli gates acting in all four directions. For the one-sided Majorana hexaconstruction 82, when Majorana-Pauli tracking is used, the MZM tag configuration <1,2,6,3,4,5> yields the lowest estimated total resource cost 66 for each of the single-qubit Hadamard gates, the geometric mean of all single-qubit Clifford gates, the geometric mean of the controlled NOT gates acting in all four directions, and the geometric mean of the controlled Pauli gates acting in all four directions.

[0125] Figure 28 A flow chart of an example method 600 for performing quantum computations by implementing logic gates is shown. The method 600 may be used in conjunction with Figure 1 Quantum computing systems 10, Figure 4 The method 600 may be used together with the example quantum computing system 100 or some other quantum computing system of the topological quantum computing device. At step 602, the method 600 may include: identifying a plurality of measurement sequences that implement the logic gate. Each measurement sequence may include a plurality of measurements of the quantum state of the topological quantum computing device. In some embodiments, the topological quantum computing device may include at least one of the following: a Majorana tetrahedron including four MZMs, a Majorana hexahedron including six MZMs, or a Majorana octahedron including eight MZMs. In some embodiments, the topological quantum computing device may include a plurality of Majorana tetrahedrons, hexahedrons and / or octahedrons. Additionally or alternatively, the topological quantum computing device may include a Majorana tetrahedron including four MZMs and / or a Majorana tetrahedron including eight MZMs. In some embodiments, the measurement sequence may include measurements of a plurality of Majorana tetrahedrons, hexahedrons and / or octahedrons.

[0126] In some embodiments, step 602 may include, at step 604, identifying one or more measurement sequences that implement a logic gate multiplied by a global Pauli operator. When two measurement sequences differ in the global Pauli operator, the Pauli operator can be tracked as measurements in the measurement sequence are performed when the logic gate is implemented in a topological quantum computing device. At the end of the measurement sequence, a correction of the global Pauli operator can be performed. Step 604 can allow for saving computational resources by reducing the number of measurement sequences that need to be examined by more computationally intensive methods.

[0127] At step 606, method 600 may further include determining a corresponding estimated total resource cost for each measurement sequence in the plurality of measurement sequences. For each measurement sequence in the plurality of measurement sequences, step 606 may include, at step 608, determining an estimated weighted resource cost for each measurement included in the measurement sequence. In some embodiments, the estimated weighted resource cost for each measurement may indicate an error rate for the measurement. In embodiments where step 608 is performed, step 606 may further include, at step 610, determining an estimated total resource cost for the measurement sequence based on the plurality of estimated weighted resource costs. For example, the estimated total resource cost may be the product of the estimated weighted resource costs for the measurements. In some embodiments, step 606 may include determining a corresponding estimated total resource cost for each measurement sequence that implements a logic gate and is shorter than a predetermined length.

[0128] In embodiments where the quantum state includes a Majorana tetraparticle, a Majorana hexaparticle, or a Majorana octonite, the MZMs included in the Majorana tetraparticle, the Majorana hexaparticle, or the Majorana octonite may have a labeling order that indicates a plurality of MZMs included in the computational qubit and a plurality of MZMs included in the auxiliary qubit. In such embodiments, step 606 may further include, at step 612, modifying the topological encodings of the computational qubits and the auxiliary qubits. These topological encodings may be modified by relabeling the MZMs included in the Majorana tetraparticle, the Majorana hexaparticle, or the Majorana octonite to change how the computational and auxiliary qubits are encoded in the physical MZMs.

[0129] At step 614, the method 600 may further include determining a first measurement sequence having a lowest estimated total resource cost among the plurality of measurement sequences. At step 616, the method 600 may further include implementing a logic gate at the topological quantum computing device by applying the first measurement sequence to the quantum state. In some embodiments, step 616 may include performing Figure 16B 4. In embodiments where step 604 is performed, step 616 may further include, at step 618, tracking Pauli gate corrections to logic gates as the measurement sequence is performed.

[0130] Although the above examples are provided for a topological quantum computing device 20 including a Majorana hexason 30, the systems and methods discussed above can be used when topological quantum computing is performed using other non-Abelian anyons or defects. In such an embodiment, measurements of fusion channels other than Fermi parity can be performed. When the measurement result corresponds to an Abelian fusion channel, forced measurement and Majorana-Pauli tracking protocols can be used. In addition to MZM, examples of structures that can be used for topological quantum computing devices include Ising anyons and Parafendleyons (paraferminonic zero mode). Although the topological charge discussed in the examples provided above is a joint Fermi parity, when a defect other than MZM is included in a topological quantum computing device, the topological charge can be some other quantity. When the measurement result corresponds to a non-Abelian fusion channel, a forced measurement protocol can also be used. In addition, the above-mentioned resource cost estimation system and method can be applied to other measurement-based operations, such as injection of non-Clifford gates.

[0131] In some embodiments, the methods and processes described herein may be bound to a computing system of one or more computing devices. In particular, such methods and processes may be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0132] Figure 29 A non-limiting embodiment of a computing system 700 is schematically illustrated that can implement one or more of the methods and processes described above. The computing system 700 is shown in simplified form. The computing system 700 can embody Figure 1 The quantum computing system 10 illustrated in FIG and described above can be a computer system 700. The computing system 700 can take the form of one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smartphones), and / or other computing devices, as well as wearable computing devices such as smart watches and head-mounted augmented reality devices.

[0133] The computing system 700 includes a logic processor 702, a volatile memory 704, and a non-volatile storage device 706. The computing system 700 may optionally include a display subsystem 708, an input subsystem 710, a communication subsystem 712, and / or other subsystems. Figure 29 Components not shown.

[0134] Logical processor 702 includes one or more physical devices configured to execute instructions. For example, a logical processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions may be implemented to perform a task, implement a data type, transform the state of one or more components, achieve a technical effect, or otherwise achieve a desired result.

[0135] The logical processor may include one or more physical processors (hardware) configured to execute software instructions. Additionally or alternatively, the logical processor may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. The processor of the logical processor 702 may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel and / or distributed processing. The individual components of the logical processor may optionally be distributed among two or more separate devices that may be remotely located and / or configured for coordinated processing. Various aspects of the logical processor may be virtualized and executed by a remotely accessed networked computing device configured in a cloud computing configuration. In such a case, it will be understood that these virtualized aspects run on different physical logical processors of various different machines.

[0136] The non-volatile storage device 706 includes one or more physical devices that are configured to store instructions executable by a logical processor to implement the methods and processes described herein. When such methods and processes are implemented, the state of the non-volatile storage device 706 can be transformed—for example, to store different data.

[0137] The non-volatile storage device 706 may include a removable and / or built-in physical device. The non-volatile storage device 706 may include an optical memory (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), a semiconductor memory (e.g., ROM, EPROM, EEPROM, flash memory, etc.), and / or a magnetic memory (e.g., a hard disk drive, a floppy disk drive, a tape drive, MRAM, etc.), or other mass storage device technology. The non-volatile storage device 706 may include a non-volatile, dynamic, static, read / write, read-only, sequential access, location addressable, file addressable, and / or content addressable device. It should be understood that the non-volatile storage device 706 is configured to retain instructions even when power to the non-volatile storage device 706 is cut off.

[0138] Volatile memory 704 may include physical devices that include random access memory. Volatile memory 704 is typically used by logical processor 702 to temporarily store information during the processing of software instructions. It should be understood that when volatile memory 704 is powered off, volatile memory 704 typically does not continue to store instructions.

[0139] Aspects of the logic processor 702, volatile memory 704, and non-volatile storage device 706 may be integrated together into one or more hardware logic components. Such hardware logic components may include field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASIC / ASICs), program and application specific standard products (PSSP / ASSPs), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0140] The terms "module," "program," and "engine" may be used to describe an aspect of computing system 700 that is typically implemented in software by a processor to use portions of volatile memory to perform a specific function that involves transformations specifically configured to perform the function. Thus, a module, program, or engine may be instantiated by logical processor 702 executing instructions stored by non-volatile storage device 706 using portions of volatile memory 704. It should be understood that different modules, programs, and / or engines may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Similarly, the same module, program, and / or engine may be instantiated by different applications, services, code blocks, objects, routines, APIs, functions, etc. The terms "module," "program," and "engine" may include individual or a group of executable files, data files, libraries, drivers, scripts, database records, etc.

[0141] When included, the display subsystem 708 can be used to present a visual representation of the data stored by the non-volatile storage device 706. The visual representation can take the form of a graphical user interface (GUI). Since the methods and processes described herein change the data stored by the non-volatile storage device and thus transform the state of the non-volatile storage device, the state of the display subsystem 708 can also be transformed to visually represent the changes in the underlying data. The display subsystem 708 can include one or more display devices utilizing almost any type of technology. Such a display device can be combined with the logical processor 702, the volatile memory 704 and / or the non-volatile storage device 706 in a shared housing, or such a display device can be a peripheral display device.

[0142] When included, the input subsystem 710 may include or interface with one or more user input devices, such as a keyboard, mouse, touch screen, or game controller. In some embodiments, the input subsystem may include or interface with selected natural user input (NUI) components. Such components may be integrated or peripheral, and the transduction and / or processing of input actions may be handled on-board or off-board. Example NUI components may include microphones for speech and / or voice recognition; infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection and / or intent recognition; and electric field sensing components for assessing brain activity; and / or any other suitable sensors.

[0143] When included, the communication subsystem 712 can be configured to communicatively couple the various computing devices described herein to each other, as well as to communicatively couple to other devices. The communication subsystem 712 may include wired and / or wireless communication devices compatible with one or more different communication protocols. As non-limiting examples, the communication subsystem can be configured to communicate via a wireless telephone network, or a wired or wireless local area network or wide area network (such as an HDMI connected via Wi-Fi). In some embodiments, the communication subsystem can allow the computing system 700 to send and / or receive messages to and / or from other devices via a network such as the Internet.

[0144] According to one aspect of the present disclosure, a computing system is provided, comprising a processor configured to identify multiple measurement sequences that implement a logic gate. Each measurement sequence may include multiple measurements of a quantum state of a topological quantum computing device. The processor may also be configured to determine a corresponding estimated total resource cost for each measurement sequence in the multiple measurement sequences. The processor may also be configured to determine a first measurement sequence in the multiple measurement sequences that has a lowest estimated total resource cost. The topological quantum computing device may be configured to implement the logic gate by applying the first measurement sequence to the quantum state.

[0145] According to this aspect, for each measurement sequence in a plurality of measurement sequences, the processor may be configured to determine a corresponding estimated total resource cost at least in part by determining an estimated weighted resource cost for each measurement included in the measurement sequence. The processor may also be configured to determine an estimated total resource cost for the measurement sequence based on the plurality of estimated weighted resource costs.

[0146] According to this aspect, the estimated weighted resource cost for each measurement may be indicative of an error rate for the measurement.

[0147] According to this aspect, the processor may be configured to determine, for each measurement sequence that implements a logic gate and is shorter than a predetermined length, a respective estimated total resource cost.

[0148] According to this aspect, the processor may be configured to determine the first measurement sequence at least in part by modifying the topological encoding of the computation qubits and the ancillary qubits.

[0149] According to this aspect, a topological quantum computing device may include a plurality of Majorana zero modes (MZMs).

[0150] According to this aspect, the topological quantum computing device may include at least one of the following: a Majorana tetrahedron including four MZMs, a Majorana hexahedron including six MZMs, or a Majorana octonary including eight MZMs.

[0151] According to this aspect, a topological quantum computing device can instantiate multiple MZMs in a single-sided architecture or a double-sided architecture.

[0152] According to this aspect, the processor may be configured to identify a plurality of measurement sequences that implement the logic gate at least in part by identifying one or more measurement sequences that implement the logic gate multiplied by a global Pauli operator.

[0153] According to this aspect, the processor may be further configured to track Pauli gate corrections to logic gates when the topological quantum computing device implements the logic gates.

[0154] According to this aspect, a topological quantum computing device can be configured to implement a logic gate at least in part by performing a forced measurement on a projection operator. The forced measurement can include performing a first measurement of a topological charge of a quantum state. The forced measurement can also include determining whether a result of the first measurement is a predetermined target value. When the result of the first measurement is not the predetermined target value, the forced measurement can also include resetting the quantum state and repeating the first measurement of the topological charge.

[0155] According to this aspect, resetting the quantum state may include repeating a second measurement in the measurement sequence that was performed before the first measurement.

[0156] According to this aspect, resetting the quantum state includes measuring a plurality of topological charges, the plurality of topological charges including a symmetric difference between a first plurality of topological charges and a second plurality of topological charges, a first measurement being performed on the first plurality of topological charges, and a second measurement in a measurement sequence preceding the first measurement being performed on the second plurality of topological charges.

[0157] According to another aspect of the present disclosure, a method for performing quantum computing is provided. The method may include identifying multiple measurement sequences that implement a logic gate. Each measurement sequence may include multiple measurements of a quantum state of a topological quantum computing device. The method may also include determining a corresponding estimated total resource cost for each measurement sequence in the multiple measurement sequences. The method may also include determining a first measurement sequence in the multiple measurement sequences that has a lowest estimated total resource cost. The method may also include implementing the logic gate at the topological quantum computing device by applying the first measurement sequence to the quantum state.

[0158] According to this aspect, determining, for each measurement sequence in the plurality of measurement sequences, a corresponding estimated total resource cost may include determining an estimated weighted resource cost for each measurement included in the measurement sequence. The estimated total resource cost for the measurement sequence may be determined based on the plurality of estimated weighted resource costs. The estimated weighted resource cost for each measurement may indicate an error rate for the measurement.

[0159] According to this aspect, a topological quantum computing device may include a plurality of Majorana zero modes (MZMs).

[0160] According to this aspect, a topological quantum computing device can instantiate multiple MZMs in a single-sided architecture or a double-sided architecture. The topological quantum computing device can include at least one of the following: a Majorana tetrahedron including MZMs, a Majorana hexahedron including six MZMs, or a Majorana octahedron including eight MZMs.

[0161] According to this aspect, identifying a plurality of measurement sequences that implement the logic gate may include identifying one or more measurement sequences that implement the logic gate multiplied by a global Pauli operator.

[0162] According to this aspect, implementing the logic gate may include performing a forced measurement on a projection operator included in the logic gate. The forced measurement may include performing a first measurement of a topological charge of the quantum state. The forced measurement may also include determining whether a result of the first measurement is a predetermined target value. When the result of the first measurement is not the predetermined target value, the forced measurement may also include resetting the quantum state and repeating the first measurement of the topological charge.

[0163] According to another aspect of the present disclosure, a computing system is provided, comprising a processor configured to identify multiple measurement sequences that implement a logic gate. Each measurement sequence may include multiple measurements of a quantum state of a topological quantum computing device. The topological quantum computing device may include a Majorana hexaplex having six Majorana zero-energy modes (MZMs). The processor may also be configured to determine an estimated weighted resource cost for each measurement in each measurement sequence included in the multiple measurement sequences. For each measurement sequence, the processor may also be configured to determine an estimated total resource cost of the measurement sequence based on the estimated weighted resource costs of the measurements included in the measurement sequence. The processor may also be configured to determine a first measurement sequence with the lowest estimated total resource cost among the multiple measurement sequences. The topological quantum computing device may be configured to implement a logic gate by applying the first measurement sequence to the quantum state.

[0164] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, as many variations are possible. The specific routines or methods described herein may represent one or more processing strategies in any number of processing strategies. Therefore, the various actions illustrated and / or described may be performed in the order illustrated and / or described, performed in other orders, performed in parallel, or omitted. Likewise, the order of the above-described processes may be changed.

[0165] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.< / n> < / n>

Claims

1. A computing system comprising: A processor configured to: identifying a plurality of measurement sequences that implement a logic gate, each measurement sequence comprising a plurality of measurements of a quantum state of a topological quantum computing device; determining, for each measurement sequence of the plurality of measurement sequences, a corresponding estimated total error rate for implementing the logic gate at the quantum state using the measurement sequence; as well as determining a first measurement sequence of the plurality of measurement sequences having a lowest estimated total error rate, The topological quantum computing device is configured to implement the logic gate by applying the first measurement sequence to the quantum state.

2. The computing system of claim 1, wherein: For each measurement sequence of the plurality of measurement sequences, the processor is configured to determine the corresponding estimated total error rate at least in part by: determining an estimated weighted error rate for each measurement included in the measurement sequence; as well as The estimated total error rate of the measurement sequence is determined based on a plurality of the estimated weighted error rates. 3 . The computing system of claim 1 , wherein the processor is configured to determine, for each measurement sequence that implements the logic gate and is shorter than a predetermined number of measurements, a respective estimated total error rate.

4. The computing system of claim 1 , wherein the processor is configured to determine the first measurement sequence at least in part by modifying a topological encoding of computation qubits and ancillary qubits.

5. The computing system of claim 1, wherein the topological quantum computing device comprises a plurality of Majorana zero-energy modes (MZMs).

6. The computing system according to claim 5, wherein the topological quantum computing device comprises at least one of the following: a Majorana tetrahedron including four MZMs, a Majorana hexahedron including six MZMs, or a Majorana octahedron including eight MZMs.

7. The computing system of claim 5, wherein the topological quantum computing device instantiates the plurality of MZMs in a single-sided architecture or a double-sided architecture.

8. The computing system of claim 5, wherein the processor is configured to identify the plurality of measurement sequences that implement the logic gate at least in part by identifying one or more measurement sequences that implement the logic gate multiplied by a global Pauli operator.

9. The computing system of claim 8, wherein the processor is further configured to track Pauli gate corrections to the logic gate when the topological quantum computing device implements the logic gate.

10. The computing system of claim 1 , wherein the topological quantum computing device is configured to implement the logic gate at least in part by performing a forced measurement on a projection operator, wherein the forced measurement comprises: performing a first measurement of a topological charge of the quantum state; determining whether a result of the first measurement is a predetermined target value; When the result of the first measurement is not the predetermined target value: resetting the quantum state; as well as The first measurement of the topological charge is repeated. 11 . The computing system of claim 10 , wherein resetting the quantum state comprises repeating a second measurement in the sequence of measurements that was performed before the first measurement.

12. The computing system of claim 10 , wherein resetting the quantum state comprises measuring a plurality of topological charges, the plurality of topological charges comprising a symmetric difference of: a first plurality of topological charges on which the first measurement is performed; and A second plurality of topological charges, for which a second measurement in the measurement sequence preceding the first measurement is performed.

13. A method for performing quantum computing, the method comprising: identifying a plurality of measurement sequences that implement the logic gate, each measurement sequence comprising a plurality of measurements of a quantum state of a topological quantum computing device; determining, for each measurement sequence of the plurality of measurement sequences, a corresponding estimated total error rate for implementing the logic gate at the quantum state using the measurement sequence; determining a first measurement sequence of the plurality of measurement sequences having a lowest estimated total error rate; as well as The logic gate is realized at a topological quantum computing device by applying the first measurement sequence to the quantum state.

14. The method of claim 13 , wherein for each measurement sequence in the plurality of measurement sequences, determining the corresponding estimated total error rate comprises: determining an estimated weighted error rate for each measurement included in the measurement sequence; as well as An estimated total error rate for the measurement sequence is determined based on the plurality of estimated weighted error rates.

15. The method of claim 13, wherein the topological quantum computing device comprises a plurality of Majorana zero-energy modes (MZMs).

16. The method of claim 15, wherein the topological quantum computing device instantiates the plurality of MZMs in a single-sided architecture or a double-sided architecture: and The topological quantum computing device includes at least one of the following: a Majorana tetrahedron including an MZM, a Majorana hexahedron including six MZMs, or a Majorana octahedron including eight MZMs.

17. The method of claim 15, wherein identifying the plurality of measurement sequences that implement the logic gate comprises: One or more measurement sequences multiplied by the global Pauli operator that implement the logic gate are identified.

18. The method of claim 13, wherein implementing the logic gate comprises performing a forced measurement on a projection operator included in the logic gate, wherein the forced measurement comprises: performing a first measurement of a topological charge of the quantum state; determining whether a result of the first measurement is a predetermined target value; When the result of the first measurement is not the predetermined target value: resetting the quantum state; as well as The first measurement of the topological charge is repeated.

19. A computing system comprising: A processor configured to: Identifying a plurality of measurement sequences for implementing a logic gate, each measurement sequence comprising a plurality of measurements of a quantum state of a topological quantum computing device, wherein the topological quantum computing device comprises a Majorana hexaplex, and the Majorana hexaplex comprises six Majorana zero-energy modes (MZMs); determining an estimated weighted error rate for each measurement included in each measurement sequence in the plurality of measurement sequences; as well as determining, for each measurement sequence of the plurality of measurement sequences, a respective estimated total error rate for the measurement sequence based on the estimated weighted error rates of the measurements included in the measurement sequence; as well as determining a first measurement sequence of the plurality of measurement sequences having a lowest estimated total error rate, The topological quantum computing device is configured to implement the logic gate by applying the first measurement sequence to the quantum state.

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