Method for manufacturing a composite structure including a single crystal SIC thin layer on a polycrystalline SIC carrier substrate

Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline SiC arranged on a polycrystalline SiC carrier substrate, the method comprising: a step of providing an initial substrate of monocrystalline silicon carbide, a first deposition step at a temperature higher than 1000° C. to form an intermediate layer of polycrystalline silicon carbide on the initial substrate, the thickness of the intermediate layer being greater than or equal to 1.5 micrometers, a step of implanting a light substance through the intermediate layer to form a fragile plane embedded in the initial substrate, thereby forming a boundary of the thin layer between the embedded fragile plane and the intermediate layer, a second deposition step at a temperature higher than 1000° C. to form an additional layer of polycrystalline silicon carbide on the intermediate layer, the intermediate layer and the additional layer forming the carrier substrate, separation being performed along the embedded fragile plane during the second deposition step.

Description

Background Art

[0002] Interest in silicon carbide (SiC) has increased significantly over the past few years due to the semiconductor material's ability to increase energy processing capabilities. SiC is increasingly being used to manufacture innovative power devices to meet the growing demands of electronics, particularly in applications such as electric vehicles.

[0003] Power devices and integrated power systems based on single-crystal silicon carbide are capable of handling significantly higher energy densities than their traditional silicon counterparts, and can do so with smaller active area sizes. To further limit the size of power devices on SiC, it is advantageous to produce vertical components rather than lateral components. To achieve this, the structure must allow vertical conduction between electrodes arranged on the front and rear surfaces of the SiC structure.

[0004] However, single-crystal SiC substrates intended for use in the microelectronics industry are still expensive and difficult to supply in large sizes. Therefore, it is advantageous to utilize thin layer transfer solutions to manufacture composite structures, which typically include a single-crystal SiC thin layer on a cheaper carrier substrate. One well-known thin layer transfer solution is Smart Cut TM A method based on the implantation of light ions and the connection by direct bonding. This method makes it possible, for example, to produce composite structures comprising a thin layer of single-crystalline SiC (c-SiC), taken from a c-SiC donor substrate, in direct contact with a carrier substrate made of polycrystalline SiC (p-SiC), allowing vertical electrical conduction. However, achieving high-quality direct bonding by molecular adhesion between two substrates made of c-SiC and p-SiC remains difficult due to the complexity of managing the surface state and roughness of the substrates.

[0005] Various methods derived from this method are also known from the prior art. For example, F. Mu et al. (ECS Transactions, 86 (5) 3-21, 2018) implemented direct bonding (SAB for “surface activated bonding”) after activating the surfaces to be connected by argon bombardment: this treatment before bonding generates a very high density of dangling bonds, which promote the formation of covalent bonds at the connection interface and thus generate high bonding energy. However, this method has the disadvantage of generating an amorphous layer at the surface of the single-crystalline SiC donor substrate, which adversely affects the vertical conductivity between the c-SiC thin layer and the carrier substrate made of p-SiC.

[0006] Solutions to this problem have been proposed, in particular in document EP 3 168 862, implementing the implantation of dopant species into the amorphous layer in order to restore its electrical properties. The main drawback of this method is its complexity and therefore its cost.

[0007] Also known is document US Pat. No. 8,436,363, which describes a method for producing a composite structure comprising a thin c-SiC layer arranged on a metallic carrier substrate whose thermal expansion coefficient matches that of the thin layer. The production method comprises the following steps:

[0008] - forming a buried fragile plane in the c-SiC donor substrate, defining a thin layer between said buried fragile plane and the front face of the donor substrate,

[0009] - depositing a metal layer, for example a tungsten or molybdenum layer, on the front face of the donor substrate to form a carrier substrate having a sufficient thickness to perform the hardening function,

[0010] - separation along the buried fragile plane, forming a composite structure comprising the metal carrier substrate and the c-SiC thin layer on the one hand and the remaining part of the c-SiC donor substrate on the other hand.

[0011] However, such a manufacturing method is incompatible when the material forming the carrier substrate is p-SiC, which needs to be deposited at temperatures higher than 1000° C. (for example, at 1200° C.): in particular, at these high temperatures, the growth kinetics of the cavities present in the buried fragile planes are faster than those of the p-SiC layer, and the thickness required for the hardening effect is not reached before blistering begins to occur, which is associated with deformations of the layer vertically aligned with the cavities.

[0012] It should be noted that depositing p-SiC at high temperatures (>1000°C) is particularly advantageous because it imparts structural properties (grain size, crystal orientation, etc.) that are conducive to good electrical conductivity, good thermal conductivity, and a thermal expansion coefficient very close to that of the c-SiC on which the p-SiC layer is deposited: properties that are generally desired for SiC-based substrates intended to house power devices. High deposition temperatures are also advantageous because they allow for high growth rates.

[0013] Subject matter of the invention

[0014] The present invention relates to a solution that is an alternative to the solutions of the prior art and aims to completely or partially overcome the above-mentioned disadvantages. The invention specifically relates to a method for producing a composite structure comprising a thin c-SiC layer arranged on a carrier substrate made of p-SiC produced by high-temperature deposition. Summary of the Invention

[0015] The present invention relates to a method for producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate made of polycrystalline SiC. The method comprises:

[0016] - a step of providing an initial substrate made of single-crystalline silicon carbide,

[0017] - a first deposition step at a temperature greater than 1000° C., in order to form on said initial substrate an intermediate layer of polycrystalline silicon carbide, said intermediate layer having a thickness greater than or equal to 1.5 micrometers,

[0018] - a step of implanting light ion species through said intermediate layer so as to form a buried fragile plane in said initial substrate, delimiting said thin layer between said buried fragile plane and said intermediate layer,

[0019] a second deposition step at a temperature greater than 1000° C., to form an additional layer of polycrystalline silicon carbide on the intermediate layer, said intermediate layer and said additional layer forming said carrier substrate, detachment occurring during said second deposition step along said buried fragile plane.

[0020] Other advantageous and non-limiting features according to the invention, considered alone or in any feasible combination:

[0021] The first deposition step and the second deposition step are performed by chemical vapor deposition at a temperature of 1000° C. to 1600° C., preferably 1200° C. to 1600° C.;

[0022] The first deposition step and the second deposition step are performed at the same temperature;

[0023] The first deposition step and / or the second deposition step is performed starting from a chlorinated precursor;

[0024] After completion of the first deposition step, the thickness of the intermediate layer is greater than or equal to 3 microns, or even greater than or equal to 5 microns;

[0025] The implanted light substance is selected from hydrogen and / or helium;

[0026] Hydrogen ions with energies ranging from 260keV to 2000keV and 5 E 16 / cm 2 to 1 E 17 / cm 2 The dose implanted;

[0027] Before the first deposition step, the method comprises a step of preparing the initial substrate, said step comprising at least one operation of deoxidizing the front surface of the initial substrate;

[0028] After said second deposition step, the method comprises a finishing step applied to the composite structure, said step comprising chemical mechanical polishing of the free face of the thin layer and / or chemical mechanical polishing of the free face of the carrier substrate;

[0029] • Chemical mechanical polishing of the thin layer and the carrier substrate is performed simultaneously by using a double-side polishing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features and advantages of the present invention will become apparent from the following detailed description of the invention given with reference to the accompanying drawings, in which:

[0031] [ Figure 1 ] Figure 1 shows a composite structure manufactured according to the manufacturing method according to the present invention;

[0032] [ Figure 2a 、 Figure 2b 、 Figure 2c 、 Figure 2d 、 Figure 2e 、 Figure 2f ] Figures 2a to 2f The steps of the manufacturing method according to the present invention are shown. DETAILED DESCRIPTION

[0033] Throughout the specification, like reference numerals will be used for like elements in the drawings. These drawings are schematic representations and, for the sake of legibility, are not drawn to scale. In particular, the thickness of a layer along the z-axis is not proportional to the lateral dimensions along the x- and y-axes; and the relative thickness of a layer relative to another layer need not be considered in the drawings.

[0034] The invention relates to a method for producing a composite structure 1 comprising a thin layer 10 of monocrystalline silicon carbide arranged on a carrier substrate 20 made of polycrystalline SiC. Figure 1 ).

[0035] The method first comprises the step of providing an initial substrate 11 made of single-crystal silicon carbide ( Figure 2a Throughout the remainder of the specification, “c-SiC” will be used to refer to single crystal silicon carbide.

[0036] The initial substrate 11 preferably takes the form of a wafer having a diameter of 100 mm, 150 mm, or even 200 mm and a thickness typically between 300 and 800 microns. The initial substrate 11 has a front face 11 a and a rear face 11 b. The surface roughness of the front face 11 a is advantageously selected to be less than 1 nm Ra (average roughness), as measured by atomic force microscopy (AFM) in a 20 μm × 20 μm scan.

[0037] After the method of the present invention is completed, the c-Si thin layer 10 of the composite structure 1 is formed starting from an initial substrate 11; therefore, the crystal orientation, crystal quality and doping level of the initial substrate 11 are selected to meet the required specifications of the vertical features formed on the thin layer 10. Typically, the initial substrate 11 made of c-SiC has a 4H or 6H polytype, an offcut angle with respect to the <11-20> crystal axis of less than 4.0°±0.5° and a micropipe density less than or equal to 5 / cm 2 , or even 1 / cm 2 N-(nitrogen-) doped, which preferably exhibits a resistivity of 0.015 ohm.cm to 0.030 ohm.cm. Optionally, depending on the sensitivity of the component to these defects, it may be chosen to exhibit a low density of BPDs (basal plane dislocations) (typically less than or equal to 1500 / cm 2 ) of the initial substrate 11.

[0038] Alternatively, the initial substrate 11 may comprise, on its front face 11a, a surface layer produced, for example, by epitaxy and exhibiting the properties required of the future thin layer 10 to be formed starting from said surface layer after completion of the method of the invention.

[0039] The method comprises a first deposition step at a temperature above 1000° C. to form an intermediate layer 21 ( ) of p-SiC on the front face 11 a of the initial substrate 11. Figure 2b The thickness of the intermediate layer 21 is greater than 1.5 micrometers. Advantageously, the thickness of the intermediate layer 21 is greater than or equal to 3 micrometers, or even greater than or equal to 5 micrometers. This minimum thickness is defined so as to impart to the intermediate layer 21 a hardening function sufficient for the second step later in the method, which will be described further below.

[0040] Preferably, the thickness of the intermediate layer 21 is kept below 30 microns in order to limit the implantation energy required to penetrate said layer in the subsequent steps of the method.

[0041] This first deposition is advantageously carried out using a chemical vapor deposition (CVD) technique based on chlorinated precursors and at a temperature between 1000° C. and 1600° C. Still more advantageously, the deposition temperature is between 1200° C. and 1600° C., as proposed in the literature by Chichignoud et al. (“Chlorinated silicon carbide CVD revisited for polycrystalline bulk growth”, Volume 201, Issues 22–23, 25 September 2007, Pages 8888-8892, Surface and Coatings Technology). The parameters of the first deposition are determined so that the intermediate layer 21 exhibits good electrical conductivity (i.e., 0.015 ohm.cm to 0.03 ohm.cm), high thermal conductivity (i.e., greater than or equal to 200 W·m -1 ·K -1 ) and a thermal expansion coefficient similar to that of the thin layer 10 (ie, typically 3.8E-6 / K to 4.2E-6 / K at ambient temperature).

[0042] To obtain these properties, for example, the intermediate layer 21 may exhibit the following structural features: 3C SiC grains, 111 orientation, average size of 1 μm to 10 μm, N-doped to obtain a final resistivity lower than or equal to 0.03 ohm.cm.

[0043] The manufacturing method according to the present invention further comprises the step of implanting light ion species into the initial substrate 11 to a given depth through the intermediate layer 21. This implantation generates a buried fragile plane 12 ( Figure 2c ).

[0044] The light material to be implanted is preferably hydrogen, helium or both of them. TM As is well known in the art, these light substances will form microcavities around a given depth, distributed in a thin layer parallel to the free surface of the intermediate layer 21 (i.e. parallel to the plane (x, y) in the figure). For simplicity, this thin layer will be called a buried fragile plane.

[0045] The buried fragile plane 12 delimits, together with the front face of the initial substrate 11 , the future thin layer 10 . In other words, at this stage, the thin layer 10 of the composite structure 1 obtained after completion of the manufacturing method is arranged between the buried fragile plane 12 and the intermediate layer 21 .

[0046] The implantation energy of the light species is chosen so that the light species penetrates the intermediate layer 21 and reaches a given depth in the initial substrate 11 , said depth corresponding to the target thickness of the thin layer 10 .

[0047] Typically, the energy between 260keV and 2000keV and 5 E 16 / cm 2 to 1 E 17 / cm 2 The hydrogen ions are implanted at a dose between 1.5 μm and 30 μm to penetrate the intermediate layer 21 and define a thin layer 10 of approximately 100 nm to 1500 nm.

[0048] It should be noted that, before the ion implantation step, a protective layer may be deposited on the free face of the intermediate layer 21. This protective layer may consist of a material such as silicon oxide or silicon nitride.

[0049] The manufacturing method finally comprises a second deposition step at a temperature above 1000° C. to form an additional layer 22 of p-SiC on the intermediate layer 21 ( Figure 2d ).

[0050] This second deposition is advantageously carried out using a chemical vapor deposition (CVD) technique based on chlorinated precursors and at a temperature between 1000° C. and 1600° C. Still more advantageously, similarly to the first deposition, the temperature of the deposition is between 1200° C. and 1600° C. Similar to the first deposition, the parameters of the second deposition are determined so that the additional layer 22 exhibits good electrical conductivity (i.e., 0.015 ohm.cm to 0.03 ohm.cm), high thermal conductivity (i.e., greater than or equal to 200 W.m -1 .K -1 ) and a thermal expansion coefficient similar to that of the thin layer 10 (ie, typically 3.8E-6 / K to 4.2E-6 / K at ambient temperature).

[0051] The temperature and conditions of the second deposition may be the same as or different from those of the first deposition in order to obtain the electrical, thermal and mechanical properties of the additional layer 22 as described above.

[0052] As presented above for the intermediate layer 21 , in order to obtain these properties, the additional layer 22 will likely exhibit the following structural features, for example: 3C SiC grains, 111 orientation, average size 1 to 10 μm, N-doped to obtain a final resistivity lower than or equal to 0.03 ohm.cm.

[0053] The assembly formed by the intermediate layer 21 and the additional layer 22 is intended to form the carrier substrate 20 of the composite structure 1. The carrier substrate 20 will thus be provided with the electrical, thermal and mechanical properties presented above, meeting the expected specifications for a vertical power device.

[0054] The target final thickness of the carrier substrate 20 is typically in the range of 50 microns to 300 microns.

[0055] During the second deposition step, due to the thermal budget applied to the structure formed by the initial substrate 11, the intermediate layer 21 and the grown additional layer 22, separation along the buried fragile plane 12 will occur ( Figure 2e In particular, the microcavities present in the buried fragile plane 12 follow growth kinetics until a fracture wave is initiated which will propagate across the entire extent of the buried fragile plane 12 and lead to the separation of the assembly formed by the thin layer 10, the intermediate layer 21 and the additional layer 22 from the rest of the initial substrate 11 ′.

[0056] According to a first variant, the separation is carried out before the additional layer 22 reaches its target thickness. When the separation occurs, the fracture wave will propagate across the entire extent of the buried fragile plane 12, regardless of the thickness of the additional layer 22, since the intermediate layer 21 itself is thick enough to provide a stiffening effect: the cavities will therefore not deform the layer due to blistering. The second deposition can then be continued until the target thickness of the additional layer 22 is reached and the final composite structure 1 is obtained ( Figure 2f The sum of the target thickness of the additional layer 22 and the thickness of the intermediate layer 21 constitutes the final thickness of the carrier substrate 20 .

[0057] According to a second variant, separation occurs substantially at the moment when the additional layer 22 reaches its target thickness.

[0058] It is well understood that, depending on the implantation parameters, the temperature of the second deposition and the target thickness of the additional layer 22 (which determines the duration of the second deposition), the separation will occur according to the first or second variant described above.

[0059] Advantageously, before the first deposition step and / or before the second deposition step, the manufacturing method includes a step of preparing the initial substrate 11, which includes at least one process of deoxidizing the front face of said initial substrate 11. This process can be performed, for example, by immersion in a hydrofluoric acid (HF) bath or by exposure to HF vapor. The preparation step may also include a cleaning process to remove all or some metallic or organic particle contaminants that may be present on the faces 11a, 11b of the initial substrate 11.

[0060] According to an advantageous embodiment, the manufacturing method comprises finishing steps applied to the final composite structure 1 obtained upon completion of the second deposition step. These finishing steps are particularly intended to improve the roughness of the free face of the thin layer 10 (front face of the final composite structure 1) and potentially of the free face of the additional layer 22 (rear face of the final composite structure 1). In particular, after separation, the free face of the thin layer 10 typically exhibits a roughness between 3 nm Ra and 6 nm Ra (AFM-20 micron x 20 micron scan). The aim of the subsequent manufacture of the parts is to have a roughness lower than 1 nm Ra. As regards the rear face of the final composite structure 1, the roughness after completion of the second deposition is typically higher than 10 nm Ra, or even higher than 100 nm Ra; the target objective is generally to reduce the roughness to less than 3 nm Ra.

[0061] The finishing step can in particular employ known chemical mechanical polishing techniques, which can be applied to the front side, the back side, or both sides of the final composite structure 1 using double-side polishing equipment. The polishing method can differ between the front side and the back side, with different consumables generally being required for smoothing the c-SiC and p-SiC surfaces.

[0062] Example:

[0063] According to one non-limiting exemplary implementation, the initial substrate 11 provided in the first step of the manufacturing method is a wafer made of c-SiC of 4H polytype, oriented 4.0°±0.5° relative to the <11-20> axis, with a diameter of 150 mm and a thickness of 350 μm.

[0064] Before the first deposition step, a conventional RCA cleaning process (Standard Clean 1 + Standard Clean 2) was performed on the initial substrate 11, followed by Caro's acid (a mixture of sulfuric acid and hydrogen peroxide) and then HF (hydrofluoric acid). CVD based on chlorinated precursors was performed on the front face 11a of the initial substrate 11 at a temperature of 1200°C, resulting in an intermediate layer 21 with a thickness of 5 microns after 6 minutes (deposition rate: 50 μm / h).

[0065] Hydrogen ions with an energy of 650keV and 6 E 16 H+ / cm 2 A dose of 100 nm is implanted through the free face of the intermediate layer 21. Thus, a buried fragile plane 12 is produced in the initial substrate 11 at a depth of approximately 600 nm.

[0066] A cleaning process of RCA+Carrot acid is performed on this structure in order to remove possible contaminants from the free face of the intermediate layer 21 .

[0067] A second CVD process is performed on the intermediate layer 21 at a temperature of 1200° C. for 355 minutes to achieve a target thickness of 300 micrometers (the sum of the thicknesses of the intermediate layer 21 and the additional layer 22). During the deposition, separation occurs at the level of the buried fragile plane 12. After the second deposition is completed, the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the rest of the initial substrate 11.

[0068] Double-side polishing may be performed to restore the surface roughness of the thin layer 10 and the rear side of the carrier substrate 20 (the free face of the additional layer 22 ).

[0069] Of course, the invention is not limited to the described embodiments and examples, and various embodiments can be envisaged without departing from the scope of the invention, such as defined by the claims.

Claims

1. A method for producing a composite structure (1), comprising a thin layer (10) of monocrystalline silicon carbide arranged on a carrier substrate (20) made of polycrystalline silicon carbide, the method comprising: - a step of providing an initial substrate (11) made of single-crystalline silicon carbide, - a first deposition step at a temperature greater than 1000° C., in order to form on said initial substrate (11) an intermediate layer (21) of polycrystalline silicon carbide, said intermediate layer (21) having a thickness greater than or equal to 1.5 micrometers, - a step of implanting a light ion substance through said intermediate layer (21) to form a buried fragile plane (12) in said initial substrate (11) defining said thin layer (10) between said buried fragile plane (12) and said intermediate layer (21), said implanted light substance being chosen from hydrogen and / or helium, - a second deposition step at a temperature above 1000° C. to form an additional layer (22) of polycrystalline silicon carbide on said intermediate layer (21), said intermediate layer (21) and said additional layer (22) forming said carrier substrate (20), During the second deposition step, separation occurs along the buried fragile plane (12).

2. The manufacturing method according to claim 1, wherein: The first deposition step and the second deposition step are performed by chemical vapor deposition at a temperature of 1000° C. to 1600° C.

3. The manufacturing method according to claim 2, wherein: The first deposition step and / or the second deposition step are performed starting from a chlorinated precursor.

4. The manufacturing method according to any one of claims 1 to 3, wherein: After completing the first deposition step, the thickness of the intermediate layer (21) is greater than or equal to 3 micrometers.

5. The manufacturing method according to claim 4, wherein: Hydrogen ions have energies ranging from 260keV to 2000keV and 5×10 16 / cm 2 Up to 1×10 17 / cm 2 dose implanted.

6. The manufacturing method according to claim 1, before the first deposition step, comprises a step of preparing the initial substrate (11), and the step of preparing the initial substrate (11) comprises at least one operation of deoxidizing the front surface of the initial substrate (11).

7. The manufacturing method according to claim 2, wherein: The first deposition step and the second deposition step are performed by chemical vapor deposition at a temperature of 1200° C. to 1600° C.

8. The manufacturing method according to claim 4, wherein: After completing the first deposition step, the thickness of the intermediate layer (21) is greater than or equal to 5 micrometers.

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