Semiconductor memory device and method of forming the same

Abstract

Aspects of the present disclosure provide a semiconductor device including a first tube core. The first tube core includes a first layer stack, and the first layer stack includes a semiconductor layer located on the back side of the first tube core. A second layer stack is formed, which includes a gate layer and a first insulating layer alternately stacked on the front side of the first tube core. The front side is opposite to the back side. The vertical structure includes a first portion disposed in the first layer stack and a second portion extending through the second layer stack. The first portion has a different size from the second portion in a direction parallel to the main surface of the first tube core.

Description

Technical Field

[0001] The present application describes embodiments generally related to semiconductor memory devices, and methods for forming semiconductor memory devices. Background Art

[0002] Semiconductor manufacturers have developed vertical device technologies such as three-dimensional (3D) NAND flash memory technology to achieve higher data storage density without the need for smaller memory cells. In some examples, a 3D NAND memory device includes a core region (also referred to as an array region) and a step region. The core region includes an array of channel structures extending through a stack of gate layers and insulating layers. The gate layers and channel structures can form a vertical string of NAND memory cells. The step region is used to form connections to control the vertical NAND memory cell string. Summary of the invention

[0003] Aspects of the present disclosure provide a semiconductor device and a method of forming the same.

[0004] According to a first aspect, a semiconductor device is provided. The semiconductor device includes a first tube core. The first tube core includes a first layer stack, wherein the first layer stack includes a semiconductor layer located on the back side of the first tube core. A second layer stack is formed, wherein the second layer stack includes a gate layer and a first insulating layer alternately stacked on the front side of the first tube core. The front side is opposite to the back side. The vertical structure includes a first portion arranged in the first layer stack and a second portion extending through the second layer stack. The first portion has a different size from the second portion in a direction parallel to the main surface of the first tube core.

[0005] In some embodiments, the vertical structure includes a channel structure in the core region. The channel structure includes a channel layer extending in a first portion and a second portion. In some embodiments, the second portion includes: a tunneling layer surrounding the channel layer, a charge trapping layer surrounding the tunneling layer, and a blocking layer surrounding the charge trapping layer. In some embodiments, the channel layer in the first portion contacts the semiconductor layer.

[0006] In some embodiments, the first lateral periphery of the first portion extends 10-100 nm from the second periphery of the second portion.

[0007] In some embodiments, the first portion has a larger dimension than the second portion in the direction parallel to the main surface of the first die.

[0008] In some embodiments, the semiconductor device further comprises: a first conductive structure disposed on the back side of the first tube core. The first conductive structure is conductively connected to the semiconductor layer. A second conductive structure is disposed on the back side of the first tube core. The second conductive structure is conductively connected to a contact structure disposed on the front side of the first tube core.

[0009] In some embodiments, the vertical structure includes at least one of a gate line slit (GLS) structure or a dummy channel structure.

[0010] In some embodiments, the semiconductor device further comprises: a memory cell on the front side of the first die. The second die is bonded face to face with the first die. The second die comprises a substrate and a peripheral circuit for the memory cell formed on the front side of the substrate.

[0011] According to a second aspect of the present disclosure, a memory system includes a semiconductor device having a tube core. The tube core includes a first layer stack, wherein the first layer stack includes a semiconductor layer located on the back side of the tube core. The second layer stack includes a gate layer and an insulating layer alternately stacked on the front side of the tube core. The front side is opposite to the back side. The vertical structure includes a first part arranged in the first layer stack and a second part extending through the second layer stack. The first part has a different size from the second part in a direction parallel to the main surface of the tube core. The memory system also includes a controller, which is configured to control the operation of the semiconductor device. The controller is connected to the semiconductor device.

[0012] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming an etch stop structure in an initial first layer stack including a sacrificial semiconductor layer above a first substrate. The etch stop structure extends into the sacrificial semiconductor layer. A second layer stack is formed above the initial first layer stack. A hole extending through the second layer stack is formed. The hole exposes a corresponding etch stop structure having a size different from that of the hole in a direction parallel to the main surface of the first substrate. The corresponding etch stop structure is removed through the hole so that the hole extends into the sacrificial semiconductor layer. A vertical structure is formed in the hole. In some embodiments, in the direction parallel to the main surface of the first substrate, the first portion has a larger size than the second portion.

[0013] In some embodiments, the etch stop structure and the second layer stack have different etching characteristics. The etch stop structure and the sacrificial semiconductor layer have different etching characteristics.

[0014] In some embodiments, the vertical structure includes a channel structure. Forming the vertical structure includes: forming a second insulating layer on an exposed surface along the channel hole. Forming a channel layer along the second insulating layer.

[0015] In some embodiments, the first substrate of the first tube core and the sacrificial semiconductor layer are removed from the back side of the first tube core, so that the channel structure is exposed from the back side of the first tube core. The exposed portion of the second insulating layer is removed, so that the channel layer is exposed from the back side of the first tube core. A semiconductor layer covering the channel structure is formed from the back side of the first tube core. A first conductive structure conductively connected to the semiconductor layer is formed. A contact structure is formed from the front side of the first tube core. The front side is opposite to the back side. A second conductive structure is formed from the back side of the first tube core. The second conductive structure is conductively connected to the contact structure.

[0016] In some embodiments, each channel structure is formed using a corresponding etch stop structure.

[0017] In some embodiments, the second layer stack includes a sacrificial gate layer and a first insulating layer alternately stacked above the initial first layer stack. A dummy channel structure is formed in the step region. A gate line (GL) cutting groove extending through the second layer stack is formed. The sacrificial gate layer is replaced with a gate layer through the GL groove. A gate line gap (GLS) structure is formed in the GL cutting groove.

[0018] In some embodiments, forming the vertical structure includes forming at least one of the dummy channel structure or the GLS structure.

[0019] In some embodiments, the first die includes a first substrate, a peripheral circuit is formed on a front side of the second die, and the first die is bonded face-to-face with the second die.

[0020] According to a fourth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming a first layer stack including a semiconductor layer on the back side of a first tube core. Forming a second layer stack, wherein the second layer stack includes a gate layer and a first insulating layer alternately stacked on the front side of the first tube core. The front side is opposite to the back side. Forming a channel structure, wherein the channel structure includes a first portion disposed in the first layer stack and a second portion extending through the second layer stack. The first portion has a larger size than the second portion in a direction parallel to the main surface of the first tube core. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the size of various features may be increased or reduced for clarity of discussion.

[0022] Figure 1A A vertical cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure is shown.

[0023] Figure 1B An exemplary embodiment according to the present disclosure is shown. Figure 1A An expanded view of frame 100B in FIG.

[0024] Figure 1C An exemplary embodiment according to the present disclosure is shown. Figure 1A Layout design of semiconductor devices in .

[0025] Figure 2 A flow chart of an exemplary process for fabricating an exemplary semiconductor device according to an exemplary embodiment of the present disclosure is shown.

[0026] Figure 3A , 3B , 3C, 3D, 3E, 3F, 3G, 3H and Fig. 3I are cross-sectional views of semiconductor devices at various intermediate steps in fabrication according to exemplary embodiments of the present disclosure.

[0027] Figure 4 A block diagram of a memory system device according to an exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely exemplary and not restrictive. For example, forming a first feature above or on a second feature in the subsequent description may include an embodiment in which the first feature and the second feature may directly contact, and may also include an embodiment in which other features may be formed between the first feature and the second feature so that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is only for simplicity and clear illustration purposes, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0029] Additionally, for ease of description to illustrate the relationship of one element or feature to another (or multiple) element or feature as shown in the figures, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0030] According to some aspects of the present disclosure, a vertical structure such as a channel structure in a three-dimensional (3D) NAND flash memory device is formed in a hole etched into a semiconductor layer by front processing. The etching process used to form the hole in the semiconductor layer may affect the depth uniformity of the hole in the semiconductor layer. When the depth uniformity of the hole is low, the uniformity of the end profile of the vertical structure in the semiconductor layer is poor. Some semiconductor technologies use back side processing to form structures such as connection structures on the back side of the semiconductor device. In some examples, the semiconductor layer can be removed by back side processing, and further back side processing can be performed. The poor uniformity of the end profile of the vertical structure may cause difficulties in back side processing.

[0031] The present disclosure provides a method for forming a vertical structure with a well-controlled profile, including a sidewall profile and an end profile. The technology herein includes forming an etch stop structure below the future vertical structure. In some examples, the etch stop structure has a larger size in the horizontal direction than the future vertical structure, so that a hole (for the future vertical structure) with some alignment error tolerance can be formed on the top of the etch stop structure. The etch stop structure may include a material with etching selectivity so that the process of etching the hole can be stopped at the etch stop structure without causing too much surface cutting (gouging) or poor uniformity. The etch stop structure is then removed through the hole, and further processes can be performed, for example, forming a vertical structure in the hole.

[0032] According to some aspects of the present disclosure, multiple etch stop structures can be formed under various future vertical structures. In some embodiments, an etch stop structure is formed under a future channel structure to provide a controlled etch profile for a corresponding channel hole. In some embodiments, an etch stop structure is formed under a future gate line gap (GLS) structure to provide a controlled etch profile for a corresponding gate line (GL) cut groove. In some embodiments, an etch stop structure can be formed under a dummy channel structure to provide a controlled etch profile for a corresponding dummy channel hole.

[0033] According to some aspects of the present disclosure, a pattern of an etch stop structure may be included in an alignment mask, which is a first mask that forms an alignment structure that may be used for alignment by a subsequent mask. Thus, no additional mask is required.

[0034] Figure 1A A vertical cross-sectional view of a semiconductor device 100A according to an exemplary embodiment of the present disclosure is shown. Figure 1B An exemplary embodiment according to the present disclosure is shown. Figure 1A An expanded view of frame 100B in FIG. Figure 1C An exemplary embodiment according to the present disclosure is shown. Figure 1A Some layers in the layout design 100C of the semiconductor device 100A in FIG. It should be noted that, for the sake of explanation, a channel structure is used herein as an example of a vertical structure.

[0035] like Figure 1A-1B As shown in , the semiconductor device 100A includes a first die D1. The first die D1 includes a first layer stack 110, which includes a semiconductor layer 111 on the back side of the first die D1. The first die D1 also includes a second layer stack 120, which includes a gate layer 123 and a first insulating layer 121 alternately stacked on the front side of the first die D1. The front side is opposite to the back side. The first die D1 also includes a channel structure 130 disposed in a core region 101 (also referred to as an array region). The channel structure 130 may include a first portion 131 disposed in the first layer stack 110 and a second portion 132 extending through the second layer stack 120. The first portion 131 of the channel structure 130 has a larger size than the second portion 132 of the channel structure 130 in a direction parallel to the main surface of the first die D1 (e.g., the XY plane). For example, as Figure 1B As shown in , in the X direction in the XZ cross section, the first portion 131 can be wider than the second portion 132. In addition, the first portion 131 can be wider than the second portion 132 in any direction in the XY plane, so that the first portion 131 extends horizontally beyond the second portion 132. For example, the first lateral periphery of the first portion 131 can extend from the second periphery of the second portion 132 by 10-100 nm.

[0036] In some embodiments, the second portion 132 of the channel structure 130 includes a channel layer 135 (e.g., polysilicon) and a second insulating layer 134 surrounding the channel layer 135. For example, the second insulating layer 134 may include a tunneling layer 134i (e.g., silicon oxide) surrounding the channel layer 135, a charge trapping layer 134ii (e.g., silicon nitride) surrounding the tunneling layer 134i, and a blocking layer 134iii (e.g., silicon oxide) surrounding the charge trapping layer 134ii.

[0037] In some embodiments, the first portion 131 of the channel structure 130 includes a channel layer 135 surrounded by a semiconductor layer 111 (e.g., polysilicon) and covered by the semiconductor layer 111 from the back side of the first die D1. As a result, the first portion 131 is in contact with the semiconductor layer 111 and is conductively connected to the semiconductor layer 111. In some embodiments, the semiconductor layer 111 is configured to serve as a source connection layer that connects the channel layer 135 to an array common source (ACS). In one example, the semiconductor layer 111 includes a body portion 112 and a pad portion 113 (e.g., a conformal portion). The pad portion 113 is in contact with the channel layer 135 and may have a doping profile different from that of the body portion 112. In another example, the semiconductor layer 111 includes only the body portion 112 that is in contact with the channel layer 135.

[0038] In some embodiments, the channel structure 130 may further include a dielectric layer 136 located inside the channel layer 135 and surrounded by the channel layer 135. The dielectric layer 136 may include one or more voids 137.

[0039] In some embodiments, the first portion 131 of the channel structure 130 has a lateral dimension of 80-200 nm in a direction parallel to the main surface of the first tube core D1 (e.g., XY plane), and a thickness of 10-500 nm in a direction perpendicular to the main surface of the first tube core D1 (e.g., Z direction). The second portion 132 may have a lateral dimension of 60-150 nm in a direction parallel to the main surface of the first tube core. In addition, the first portion 131 and the second portion 132 may have various shapes. For example, the first portion 131 and the second portion 132 may have a circular, elliptical or polygonal shape in the XY plane, and may have a cylindrical shape in the XZ plane and the YZ plane.

[0040] Figure 1C A layout pattern 131' corresponding to the first portion 131 of the channel structure 130 and a layout pattern 132' corresponding to the second portion 132 of the channel structure are shown. In some examples, the lateral periphery of the layout pattern 131' extends from the lateral periphery of the layout pattern 132' by a layout dimension corresponding to an actual product dimension (e.g., semiconductor device 100A) of 10 nm to 100 nm.

[0041] In some embodiments, the second layer stack 120 of the gate layer 123 and the first insulating layer 121 and the channel structure 130 may form a transistor stack (e.g., an array of vertical memory cell strings). In some embodiments, the transistor stack may include memory cells stacked along the Z direction on the front side of the first die D1. In some embodiments, the transistor stack may further include a selection transistor, such as one or more bottom selection transistors, one or more top selection transistors, and the like. In some embodiments, the transistor stack may further include one or more dummy selection transistors.

[0042] Still reference Figure 1A-1B The first die D1 may further include a plurality of gate line slit (GLS) structures 140 (also referred to as gate line cutting structures in some examples) extending through the second layer stack 120. Figure 1C A layout pattern 140' corresponding to the GLS structure 140 is shown. The GLS structure 140 can be used to facilitate replacing the sacrificial layer with the gate layer 123 in a gate-last process. In one embodiment (not shown), the GLS structure 140 may include a semiconductor material (not shown) and is configured to function as an ACS. The ACS is conductively connected to the channel layer 135 via a source connection layer such as the semiconductor layer 111.

[0043] In such Figure 1A In another embodiment shown, the GLS structure 140 includes one or more dielectric materials. In some examples, the GLS structure 140 extends through the second layer stack 120, and the GLS structure 140 is configured to divide the vertical memory cell string (corresponding to the channel structure 130) into separate blocks. In some examples, the vertical memory cell string is configured to be erased in blocks. In addition, the number and arrangement of the channel structures 130 between the GLS structures 140 can vary.

[0044] exist Figure 1A In the example of the embodiment of the present invention, the GLS structure 140 is shown as having a continuous sidewall profile. In another example (not shown), the GLS structure 140 can have a configuration similar to the channel structure 130. That is, the GLS structure 140 can include a first portion disposed in the first layer stack 110 and a second portion extending through the second layer stack 120. The first portion of the GLS structure 140 can have a larger dimension than the second portion of the GLS structure 140 in a direction parallel to the main surface of the first die D1. Therefore, the sidewall of the first portion has a larger perimeter than the second portion.

[0045] In some embodiments, the first die D1 includes a staircase region 102, in which pairs of gate layers 123 and first insulating layers 121 are arranged in a stair step form, for example, each stair step has a pair of first insulating layers 121 and gate layers 123. Therefore, a gate contact structure (not shown) can be disposed on the stair step and connected to each gate layer 123. The gate contact structure is used to connect a driving circuit to each gate layer 123 to control the stacked memory cells and the select gate.

[0046] In some embodiments, the first die D1 further includes a plurality of dummy channel structures 150. The plurality of dummy channel structures 150 can prevent the second layer stack 120 from collapsing during the replacement of the sacrificial layer with the gate layer 123 in the gate-last process. The dummy channel structures 150 can include one or more dielectric materials. In one example, an array of dummy channel structures 150 can be disposed in the step region 102 between the GLS structures 140. In another example, one or more dummy channel structures 150 can also be disposed in the core region 101.

[0047] exist Figure 1A In the example of the embodiment of the present invention, the dummy channel structure 150 has a continuous sidewall. For example, the dummy channel structure 150 has a rectangular shape or a trapezoidal shape in the XZ plane. In another example (not shown), the dummy channel structure 150 may have a configuration similar to the channel structure 130. That is, the dummy channel structure 150 may include a first portion disposed in the first layer stack 110 and a second portion extending through the second layer stack 120. In a direction parallel to the main surface of the first die D1, the first portion of the dummy channel structure 150 may have a larger size than the second portion of the dummy channel structure 150. Therefore, the sidewall of the first portion has a larger perimeter than the second portion.

[0048] In some embodiments, the first die D1 may further include at least one contact structure 161 extending from the front side of the first die D1 to the back side of the first die D1. In one example, the at least one contact structure 161 extends through the capping layer 125, the third insulating layer 163, and the etch stop layer 115, and extends into the semiconductor layer 111. In another example (not shown), the contact structure 161 extends through the first insulating layer 121 and the third insulating layer 163, and may stop at the etch stop layer 115.

[0049] In some embodiments, the first die D1 further includes a spacer layer 165 (e.g., silicon oxide) covering the semiconductor layer 111 from the back side of the first die D1. A first conductive structure 167a is disposed on the back side of the spacer layer 165, and the first conductive structure 167a is conductively connected to the semiconductor layer 111 through an opening in the spacer layer 165. A second conductive structure 167b is also disposed on the back side of the first die D1, and the second conductive structure 167b is conductively connected to the contact structure 161 through a contact portion called a through-silicon contact portion. In one example, a through-silicon contact portion is formed in the opening in the semiconductor layer 111. The opening in the semiconductor layer 111 may be lined with a spacer layer 165 on the sidewalls. Although not shown, it should be understood that the first conductive structure 167a and the second conductive structure 167b may be conductively connected to an external circuit.

[0050] As previously described, the memory cells may be stacked vertically on the front side of the first die D1. In some embodiments, the second die D2 (not shown) may be bonded face-to-face with the first die D1 (the side with most of the circuitry is the front side, and the side opposite the front side is the back side). In some examples, the second die D2 includes a substrate and peripheral circuits for the memory cells (e.g., address decoders, drive circuits, sense amplifiers, etc.) formed on the front side of the substrate. It should be noted that the first die D1 initially includes a substrate on which the memory cells are formed, and in some examples, the substrate of the first die D1 is removed before forming the first conductive structure 167a and the second conductive structure 167b.

[0051] Typically, the peripheral circuit of the second die D2 can connect the memory cell to an external circuit interface. In some embodiments, the contact structure 161 is conductively connected to the peripheral circuit of the second die D2. Therefore, the peripheral circuit can receive instructions from the external circuit through the second conductive structure 167b and the contact structure 161, provide control signals to the memory cell, receive data from the memory cell, and output data to the external circuit through the contact structure 161 and the second conductive structure 167b.

[0052] In some embodiments, the semiconductor device 100A may include a plurality of array dies (e.g., a first die D1) and a CMOS die (e.g., a second die D2). The plurality of array dies and the CMOS die may be stacked and bonded together. Each array die is coupled to the CMOS die, and the CMOS die may drive the array die individually or together in a similar manner. In addition, in some embodiments, the semiconductor device 100A includes at least a first wafer and a second wafer bonded face to face. The first die D1 and other array dies such as D1 are arranged on the first wafer, and the second die D2 and other CMOS dies such as the second die D2 are arranged on the second wafer. The first wafer and the second wafer are bonded together so that the array die on the first wafer is bonded to the corresponding CMOS die on the second wafer.

[0053] Figure 2 A flow chart of a process 200 for manufacturing an exemplary semiconductor device (e.g., semiconductor device 100A, etc.) according to an exemplary embodiment of the present disclosure is shown. Process 200 begins at step S210, where an etch stop structure is formed in an initial first layer stack including a sacrificial semiconductor layer above a first substrate of a first die. The etch stop structure extends into the sacrificial semiconductor layer. At step S220, a second layer stack is formed. The second layer stack includes a sacrificial gate layer and a first insulating layer alternately stacked on the initial first layer stack. At step S230, a hole (e.g., a channel hole) extending through the second layer stack and stopping at the etch stop structure is formed. The hole exposes a corresponding etch stop structure having a larger size than the hole in a direction parallel to the main surface of the first die. At step S240, the corresponding etch stop structure is removed through the hole so that the hole extends into the sacrificial semiconductor layer. At step S250, a vertical structure (e.g., channel structure 130) is formed in the hole. It should be noted that other steps may be provided before, during, and after process 200, and that some of the described steps may be replaced, removed, or performed in a different order for other embodiments of process 200.

[0054] In some embodiments, the initial first layer stack may be replaced with a first layer stack (eg, first layer stack 110 ) including, for example, a semiconductor layer 111 by performing processing on the back side of the semiconductor device 100A.

[0055] Figure 3A , 3B , 3C, 3D, 3E, 3F, 3G, 3H and Fig. 3I is a cross-sectional view of a semiconductor device 300 at various intermediate steps of manufacturing according to an exemplary embodiment of the present disclosure. In some embodiments, the semiconductor device 300 may eventually become Figure 1A-1BIt should be noted that, for the sake of explanation, a channel structure is used herein as an example of a vertical structure.

[0056] like Figure 3A As shown in , the semiconductor device 300 includes a first die D3 having a first substrate 371. An oxide layer 373 may be disposed on the first substrate 371. The first die D3 includes an initial first layer stack 310 having a sacrificial semiconductor layer 375 and an etch stop layer 315. The etch stop layer 315 may be sandwiched between oxide layers 377 and 379. In some embodiments, an etch stop structure 381 is formed in the initial first layer stack 310 and extends into the sacrificial semiconductor layer 375. Figure 1A In the example of FIG. 3 , an etch stop structure 381 is formed in the core region 301. For example, the etch stop structure 381 can be formed by forming an opening in the initial first layer stack 310 based on a first mask having a pattern corresponding to the layout pattern 131 '. Then, an etch stop material (e.g., tungsten) can be deposited to fill the opening, and excess etch stop material can be removed, for example, by chemical mechanical polishing. As will be discussed later, the etch stop structure 381 can also be formed in another region (e.g., a step region).

[0057] It should be noted that in some examples, the first die D3 may eventually become Figure 1A Thus, the initial first layer stack 310 may eventually become the first layer stack 110. The etch stop layer 315 may correspond to the etch stop layer 115. The core region 301 may correspond to the core region 101. Similarly, the first die D3 may include a front side and a back side (the side with most of the circuitry is the front side, and the side opposite to the front side is the back side).

[0058] exist Figure 3B , a second layer stack 320 is formed above the initial first layer stack 310. The second layer stack 320 may include a first insulating layer 321 and a sacrificial gate layer 322 alternately stacked in the Z direction. A capping layer 325 may also be formed above the second layer stack 320. Then, a channel hole 383 may be formed by etching through the second layer stack 320. In some examples, the channel hole 383 is formed based on a second mask having a pattern corresponding to the layout pattern 132'. Each channel hole 383 may expose a corresponding etch stop structure 381, which has a larger size than the corresponding channel hole 383 in a direction parallel to the main surface of the first die D3 (e.g., the XY plane). In this example, the etch stop structure 381 may extend horizontally beyond the periphery of the corresponding channel hole 383.

[0059] In some embodiments, the etch stop structure 381 has a lateral dimension of 80-200 nm in a direction parallel to the main surface of the first die D3 (e.g., XY plane), and a thickness of 10-500 nm in a direction perpendicular to the main surface of the first die D3 (e.g., Z direction). The corresponding channel hole 383 has a lateral dimension of 60-150 nm in a direction parallel to the main surface of the first die D3.

[0060] In some embodiments, the etch stop structure 381 is configured to have different etching characteristics from the sacrificial semiconductor layer 375 and the second layer stack 320, so that the etching process of forming the channel hole 383 can be stopped at the etch stop structure 381. In a non-limiting example, the etch stop structure 381 includes tungsten. The first insulating layer 321 includes silicon oxide. The sacrificial gate layer 322 includes silicon nitride. The etch stop layer 315 includes polysilicon. The sacrificial semiconductor layer 375 includes polysilicon.

[0061] Furthermore, in some embodiments, the second layer stack 320 may eventually become the second layer stack 120. The first insulating layer 321 may correspond to the first insulating layer 121. The cover layer 325 may correspond to the cover layer 125.

[0062] exist Figure 3C In the embodiment of the present invention, the etching stop structure 381 is removed, for example, by dry etching. As a result, the channel hole 383 extends into the initial first layer stack 310 (particularly into the sacrificial semiconductor layer 375). Therefore, the channel hole 383 has a varying width in the height direction (e.g., the Z direction). More importantly, the channel hole 383 can have a uniform end profile at the bottom of the hole.

[0063] exist Figure 3D In the embodiment of the present invention, a channel structure 330 is formed in the channel hole 383. For example, a second insulating layer 334 of the channel structure 330 may be formed on the exposed surface along the channel hole 383. The second insulating layer 334 may include a tunneling layer, a charge trapping layer, and a blocking layer. Next, a channel layer 335 of the channel structure 330 may be formed along the second insulating layer 334, and a dielectric layer 336 of the channel structure 330 surrounded by the channel layer 335 may be formed. The dielectric layer 336 may include one or more voids 337.

[0064] As shown, the channel structure 330 includes a first portion 331 disposed in the initial first layer stack 310 and a second portion 332 extending through the second layer stack 320. The first portion 331 of the channel structure 330 has a larger size than the second portion 332 of the channel structure 330 in a direction parallel to the main surface of the first die D3 (e.g., XY plane).

[0065] In some embodiments, the channel structure 330 may eventually become the channel structure 130. Therefore, the first portion 331 may eventually become the first portion 131. The second portion 332 may correspond to the second portion 132. The channel layer 335 may correspond to the channel layer 135. The second insulating layer 334 may correspond to the second insulating layer 134. The dielectric layer 336 may correspond to the dielectric layer 136. The one or more voids 337 may correspond to the one or more voids 137.

[0066] In some embodiments, although not shown, the semiconductor device 300 may also include a third stack above the second stack 320. The third stack includes a first insulating layer 121 and a sacrificial gate layer 122 alternately stacked in the Z direction. A channel hole may also be formed by etching through the third stack, which is referred to as an upper channel hole (UCH). Therefore, the channel hole 383 may be referred to as a lower channel hole (LCH). Each UCH may be aligned with a corresponding LCH, so that a corresponding channel structure extending through the second stack 230 and the third stack may be formed. Each channel structure may include a first portion 331 of the channel structure 330 and another portion corresponding to the second portion 332 of the channel structure 330. In one embodiment, each channel structure may be formed in the UCH and the LCH simultaneously. In another embodiment, before forming and etching the third stack to form the UCH, before forming another portion of the corresponding channel structure in the UCH, a portion of the corresponding channel structure may first be formed in the LCH.

[0067] exist Figure 3E In the embodiment of the present invention, a step region 302 is formed in which a pair of first insulating layers 321 and sacrificial gate layers 322 are arranged in the form of steps, for example, each step has a pair of first insulating layers 321 and sacrificial gate layers 322. The step region 302 may be covered by a third insulating layer 363. For example, a plurality of dummy channel structures 350 may be formed in the step region 302. For example, one or more gate line (GL) cutting grooves 385 may be formed in the core region 301. The one or more GL cutting grooves 385 may be used to replace the sacrificial gate layer 322 with a gate layer in a subsequent step, and the plurality of dummy channel structures 350 may prevent the second layer stack 320 from collapsing in such a future replacement step.

[0068] In some embodiments, the plurality of dummy channel structures 350 are formed by etching dummy channel holes (DCH, not shown) through the second layer stack 320 and filling the DCH with one or more dielectric materials. In some embodiments, an etch stop structure 381 may be formed in the step region 302 and used to form the dummy channel structure 350. Each DCH may expose a corresponding etch stop structure 381 having a larger size than the corresponding DCH in a direction parallel to the main surface (e.g., XY plane) of the first die D3. For example, the etch stop structure 381 may extend horizontally beyond the periphery of the corresponding DCH. As a result, the dummy channel structure 350 may have a configuration similar to the channel structure 330.

[0069] In some embodiments, an etch stop structure 381 may also be formed and used to form the GL cut grooves 385. Each GL cut groove 385 may expose a corresponding etch stop structure 381, wherein the etch stop structure 381 has a larger dimension than the corresponding GL cut groove 385 in a direction parallel to the main surface of the first die D3 (e.g., the XY plane). For example, the etch stop structure 381 may extend horizontally beyond the perimeter of the corresponding GL cut groove 385. Therefore, the GL cut groove 385 (and the future gate line gap structure formed in the GL cut groove 385) may have a configuration similar to the channel structure 330.

[0070] In some embodiments, the stepped region 302 may correspond to the stepped region 102. The dummy channel structure 350 may correspond to the dummy channel structure 150. The third insulating layer 363 may correspond to the third insulating layer 163.

[0071] exist Figure 3F In the embodiment, the sacrificial gate layer 322 is replaced by the gate layer 323 by etching away the sacrificial gate layer 322 and forming the gate layer 323, and the sacrificial gate layer 322 is replaced by the gate layer 323 through the GL cutting groove 385. Then, a gate line gap (GLS) structure 340 is formed in the GL cutting groove 385. Next, at least one contact structure 361 is formed extending from the front side of the first tube core D3 to the back side of the first tube core D3. Although not shown, a gate contact structure can also be formed on the step and connected to each gate layer 323. The gate contact structure can be used to connect the drive circuit to each gate layer 323.

[0072] In some embodiments, the gate layer 323 may correspond to the gate layer 123. The GLS structure 340 may correspond to the GLS structure 140. The at least one contact structure 361 may correspond to the at least one contact structure 161. Similarly, the gate layer 323 and the first insulating layer 321 and the second layer stack 320 of the channel structure 330 may form a stack of transistors (e.g., an array of vertical memory cell strings). In some embodiments, the transistor stack may include memory cells stacked along the Z direction.

[0073] In addition, in some embodiments, the second die D4 (not shown) can be bonded to the first die D3 face to face (the side with most of the circuit is the front side, and the side opposite to the front side is the back side). The second die D4 corresponds to the second die D2. Therefore, the second die D4 can include a second substrate and a peripheral circuit for the memory cell of the first die D3 formed on the front side of the second substrate. A detailed description has been provided above, so it will not be repeated here for simplicity.

[0074] exist Figure 3G , the first substrate 371, the oxide layer 373, and the sacrificial semiconductor layer 375 are removed from the back side of the first die D3, so that the channel structure 330 is exposed from the back side of the first die D3. Specifically, the first substrate 371 can be removed by chemical mechanical polishing (CMP). The oxide layer 373 can be etched. The sacrificial semiconductor layer 375 can be selectively etched. As a result, the GLS structure 340 and the dummy channel structure 350 can also be exposed from the back side of the first die D1. In this example, the contact structure 361 is exposed. In another example where the contact structure 361 extends through the third insulating layer 363 and stops at the etch stop layer 315, the contact structure 361 remains covered by the etch stop layer 315.

[0075] exist Figure 3H In the embodiment, the exposed portion of the second insulating layer 334 is removed so that the channel layer 335 is exposed from the back side of the first die D3. As a result, the channel structure 330 can be transformed into the channel structure 130. Specifically, the first portion 331 can be transformed into the first portion 131. This has been described above, so it will not be repeated here for simplicity.

[0076] In some examples, second insulating layer 334 includes a silicon oxide layer surrounded by a silicon nitride layer surrounded by another silicon oxide layer.During the etching process that removes the exposed portion of second insulating layer 334, oxide layer 377 may also be removed accordingly.

[0077] exist Fig. 3IIn the embodiment, a semiconductor layer 311 is formed to cover the channel structure 330 from the back side of the first die D3. In some embodiments, the semiconductor layer 311 may correspond to the semiconductor layer 111. In one embodiment, the semiconductor layer 311 includes a main body portion 312 and a liner portion 313 (e.g., a conformal portion). The liner portion 313 may be formed on the channel layer 335 and doped by ion implantation. Then, the main body portion 312 may be formed, for example, by chemical vapor deposition (CVD) and planarized by CMP. The main body portion 312 may be in-situ doped during CVD or doped by ion implantation after CVD. A post-annealing step (e.g., laser annealing) may be performed to activate the dopant and / or repair crystal damage. In another embodiment, the semiconductor layer 311 includes only the main body portion 312 in contact with the channel layer 335. Therefore, the semiconductor layer 311 may be formed by a single deposition process followed by planarization, and may also be subjected to doping and annealing processes.

[0078] In addition, an opening 387 may be formed in the semiconductor layer 311 to expose the contact structure 361 from the back side of the first tube core D1. Although not shown, a spacer layer corresponding to the spacer layer 165 may be formed from the back side of the first tube core D3. A portion of the spacer layer is removed from the bottom of the opening 387 so that the remaining portion of the spacer layer covers the sidewalls of the opening 387 and exposes the contact structure 361. Next, a conductive layer may be formed from the back side of the first tube core D3 and divided to form separate conductive structures. In one example, a first conductive structure corresponding to the first conductive structure 167a is formed. The first conductive structure is conductively connected to the semiconductor layer 311 through the opening in the spacer layer. In another example, a second conductive structure corresponding to the second conductive structure 167b is formed. The second conductive structure is formed from the back side of the first tube core D3 and conductively connected to the contact structure 361 through the opening 387 in the semiconductor layer 311. The second conductive structure is separated from the semiconductor layer 311 by the remaining portion of the spacer layer disposed on the sidewalls of the opening 387.

[0079] Note that the semiconductor device 100A may be applicable to a memory system.

[0080] Figure 4 A block diagram of a memory system device 400 according to an exemplary embodiment of the present disclosure is shown. The memory system device 400 includes one or more semiconductor memory devices (e.g., as shown by semiconductor memory devices 411, 412, 413, and 414), which are respectively configured similarly to the semiconductor device 100A. In some examples, the memory system device 400 is a solid state drive (SSD).

[0081] The memory system device 400 may include other suitable components. For example, the memory system device 400 includes: Figure 4 4. The memory system device 400 may include a bus 420 coupling the main controller 402 with the semiconductor memory devices 411-414. In addition, the main controller 402 is connected to the semiconductor memory devices 411-414, respectively, as shown by corresponding control lines 421, 422, 423 and 424.

[0082] The interface 401 is appropriately configured mechanically and electrically to be connected between the memory system device 400 and the host device, and may be used to transfer data between the memory system device 400 and the host device.

[0083] The main controller 402 is configured to connect the semiconductor memory devices 411-414 to the interface 401 for data transmission. For example, the main controller 402 is configured to provide enable / disable signals to the semiconductor memory devices 411-414 to activate / deactivate one or more semiconductor memory devices 411-414 for data transmission.

[0084] The main controller 402 is responsible for completing various instructions within the memory system device 400. For example, the main controller 402 can perform bad block management, error checking and correction, garbage collection, and the like.

[0085] In some embodiments, a processor chip is used to implement the main controller 402. In some examples, the main controller 402 is implemented using multiple microcontroller units (MCUs).

[0086] As used herein, "device" or "semiconductor device" generally refers to any appropriate device, such as a memory circuit, a semiconductor chip (or die) having a memory circuit formed on a semiconductor chip, a semiconductor wafer having multiple semiconductor dies formed on a semiconductor wafer, a semiconductor chip stack, a semiconductor package including one or more semiconductor chips assembled on a packaging substrate, and the like.

[0087] As used herein, "substrate" or "target substrate" generally refers to an object processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (e.g., a semiconductor wafer, a mask), or a layer on or covering a base substrate structure (e.g., a thin film). Thus, a substrate is not limited to any particular base structure, underlying or covering layer, patterned or unpatterned, but is intended to include any such layer or base structure, and any combination of layers and / or base structures. This specification may refer to a specific type of substrate, but this is for illustrative purposes only.

[0088] The substrate may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and / or a silicon on insulator (SOI) substrate. The substrate may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.

[0089] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions and modifications to this document without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: The first die comprises: a first layer stack including a semiconductor layer on a back side of the first die; A second layer stack including gate layers and first insulating layers alternately stacked on a front side of the first die, the front side being opposite to the back side; and a vertical structure comprising a first portion disposed in the first layer stack and a second portion extending through the second layer stack, the first portion having a different dimension than the second portion in a direction parallel to a major surface of the first die, Wherein, the vertical structure includes a channel structure in the core area, the channel structure includes a channel layer extending in the first part and the second part, and the channel layer in the first part is surrounded by the semiconductor layer and the bottom surface and side surfaces of the channel layer in the first part are in direct contact with the semiconductor layer.

2. The semiconductor device according to claim 1, wherein The second part includes: a tunneling layer surrounding the channel layer; a charge trapping layer surrounding the tunneling layer; and A blocking layer surrounds the charge trapping layer.

3. The semiconductor device according to claim 1, wherein: The first portion has a larger dimension than the second portion in the direction parallel to the major surface of the first die.

4. The semiconductor device according to claim 1, wherein: The first lateral periphery of the first portion extends 10-100 nm from the second periphery of the second portion.

5. The semiconductor device according to claim 1, further comprising: A first conductive structure disposed on the back surface of the first tube core, wherein the first conductive structure is conductively connected to the semiconductor layer; as well as A second conductive structure is disposed on the back side of the first die, and the second conductive structure is conductively connected to a contact structure disposed on the front side of the first die.

6. The semiconductor device according to claim 1, wherein The vertical structure includes at least one of a gate line gap (GLS) structure or a dummy channel structure.

7. The semiconductor device according to claim 1, further comprising: a memory cell on the front side of the first die; as well as A second tube die is bonded face-to-face with the first tube die, wherein the second tube die includes a substrate and a peripheral circuit for the memory cell formed on a front side of the substrate.

8. A memory system comprising: Semiconductor equipment, including: a die comprising a first layer stack, wherein the first layer stack comprises a semiconductor layer on a back side of the die; A second layer stack including gate layers and insulating layers alternately stacked on a front side of the die, the front side being opposite to the back side; and a vertical structure, comprising a first portion disposed in the first layer stack and a second portion extending through the second layer stack, the first portion having a different size from the second portion in a direction parallel to the main surface of the die, wherein the vertical structure comprises a channel structure of a core region, the channel structure comprising a channel layer extending in the first portion and the second portion, and the channel layer in the first portion is surrounded by the semiconductor layer and a bottom surface and a side surface of the channel layer in the first portion are in direct contact with the semiconductor layer; and A controller is configured to control the operation of the semiconductor device, and the controller is connected to the semiconductor device.

9. A method for manufacturing a semiconductor device, the method comprising: forming an etch stop structure in an initial first layer stack including a sacrificial semiconductor layer over a first substrate, wherein the etch stop structure extends into the sacrificial semiconductor layer; forming a second layer stack over the initial first layer stack; forming a hole extending through the second layer stack, wherein the hole exposes a corresponding etch stop structure having a different dimension than the hole in a direction parallel to a major surface of the first substrate; removing the corresponding etch stop structure through the hole so that the hole extends into the sacrificial semiconductor layer; forming a vertical structure in the hole, wherein the vertical structure comprises a channel structure, and forming the vertical structure comprises: forming a second insulating layer on an exposed surface along the channel hole; and forming a channel layer along the second insulating layer; and removing the first substrate and the sacrificial semiconductor layer of the first die from a back side of the first die so that the channel structure is exposed from the back side of the first die; removing the exposed portion of the second insulating layer so that the bottom surface and the side surface of the channel layer are exposed from the back side of the first die; A semiconductor layer covering the exposed bottom and side surfaces of the channel structure is formed from the back side of the first die.

10. The method according to claim 9, wherein: The etch stop structure has different etching characteristics than the second layer stack, and The etch stop structure has different etching characteristics than the sacrificial semiconductor layer.

11. The method according to claim 9, wherein: In the direction parallel to the main surface of the first substrate, the etch stop structure has a larger dimension than the hole.

12. The method according to claim 9, further comprising: forming a first conductive structure conductively connected to the semiconductor layer; forming a contact structure from a front side of the first die, the front side being opposite to the back side; as well as A second conductive structure conductively connected to the contact structure is formed from the back side of the first die.

13. The method of claim 9, wherein: Each channel structure is formed using a corresponding etch stop structure.

14. The method according to claim 9, wherein: The second layer stack includes sacrificial gate layers and first insulating layers alternately stacked above the initial first layer stack, and the method further includes: forming a dummy channel structure in the step region; forming a gate line (GL) cutting groove extending through the second layer stack; Cutting a groove through the gate line and replacing the sacrificial gate layer with a gate layer; and A gate line slit (GLS) structure is formed in the gate line cutting groove.

15. The method according to claim 14, wherein: Forming the vertical structure includes forming at least one of the dummy channel structure or the gate line gap structure.

16. The method according to claim 9, wherein: The first die includes the first substrate, and the method further includes: forming peripheral circuitry on the front side of the second die; and The first die is bonded face-to-face with the second die.

17. A method for manufacturing a semiconductor device, the method comprising: forming a first layer stack including a semiconductor layer on a back side of the first die; forming a second layer stack, the second layer stack comprising gate layers and first insulating layers alternately stacked on a front side of the first die, the front side being opposite to the back side; as well as A channel structure is formed, the channel structure comprising a first portion arranged in the first layer stack and a second portion extending through the second layer stack, the first portion having a larger size than the second portion in a direction parallel to the main surface of the first tube core, wherein the channel structure comprises a channel layer extending in the first portion and the second portion, and the channel layer in the first portion is surrounded by the semiconductor layer and the bottom surface and side surfaces of the channel layer in the first portion are in direct contact with the semiconductor layer.

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