System on chip and method for regulating voltage and frequency

Abstract

Provided are a system on chip and a method for adjusting voltage and frequency. A processing unit is used to generate a frequency configuration instruction and a frequency modulation and voltage regulation instruction; a DVFS controller is used to generate at least one frequency voltage pair according to the frequency configuration instruction, and when the target frequency of the frequency modulation and voltage regulation instruction matches the first frequency in the at least one frequency voltage pair, a frequency modulation signal is generated based on the first frequency, and a voltage regulation signal is generated based on the voltage corresponding to the first frequency, the frequency modulation signal is used to adjust the clock frequency of the system on chip, and the voltage regulation signal is used to adjust the power supply voltage of the system on chip; an on-chip bus couples the processing unit and the DVFS controller. The present application configures an allowable value range for the clock frequency and power supply voltage of the system, and frequency modulation and voltage regulation operations within the allowable value range can be performed normally, and frequency modulation and voltage regulation operations outside the allowable value range are rejected, thereby improving the safety of frequency modulation and voltage regulation operations.

Description

Technical Field

[0001] The present disclosure relates to the field of chips, and in particular to a system on chip and a method for adjusting voltage and frequency. Background Art

[0002] The trend of miniaturization of integrated circuits has made processor manufacturers enthusiastic about how to reduce power consumption. Dynamic Voltage and Frequency Scaling (DVFS) is one of the ways to reduce power consumption of processors. Dynamic voltage and frequency scaling dynamically adjusts the system's clock frequency and supply voltage according to the different computing power requirements of the applications running on the processor, thereby achieving the purpose of energy saving.

[0003] In the DVFS system, applications can initiate frequency and voltage modulation requests through the system interface, and the DVFS controller adjusts the system's clock frequency and power supply voltage according to the frequency and voltage modulation requests. Attack software can take advantage of this and bring security risks to the system. For example, attack software can initiate frequency and voltage modulation requests with large frequencies and voltages. If the system's clock frequency is set to this frequency and voltage, it may cause the system to crash. Summary of the invention

[0004] In view of this, an object of the present disclosure is to provide a system on chip and a method for adjusting voltage and frequency to solve the potential safety hazards of frequency and voltage regulation operations of the system on chip.

[0005] In a first aspect, an embodiment of the present disclosure provides a system on chip, including:

[0006] A processing unit, used for generating frequency configuration instructions and frequency and voltage modulation instructions;

[0007] The DVFS controller is used to configure at least one frequency-voltage pair according to a frequency configuration instruction, and when a target frequency of the frequency-voltage modulation instruction matches a first frequency in the at least one frequency-voltage pair, generate a frequency modulation signal based on the first frequency, and generate a voltage modulation signal based on a voltage corresponding to the first frequency, wherein the frequency modulation signal is used to adjust a clock frequency of the system on chip, and the voltage modulation signal is used to adjust a power supply voltage of the system on chip;

[0008] An on-chip bus couples the processing unit and the DVFS controller.

[0009] Optionally, the DVFS controller generates an alarm signal when the target frequency does not match any frequency in the at least one frequency-voltage pair.

[0010] Optionally, the alarm signal is an interrupt signal, a reset signal or a bus error signal.

[0011] Optionally, the processing unit includes a secure environment and a non-secure environment divided in hardware, and the processing unit generates the frequency configuration instruction in the secure environment, and generates the frequency and voltage modulation instruction in the non-secure environment.

[0012] Optionally, the processing unit switches between a user state and a kernel state, and generates the frequency configuration instruction in the kernel state, and generates the frequency and voltage modulation instruction in the user state.

[0013] Optionally, the frequency configuration instruction includes an indication bit, and the indication bit is used to indicate state information when the processing unit generates the frequency configuration instruction. The DVFS controller is further used to determine whether to generate an alarm signal according to the indication bit in the frequency configuration instruction.

[0014] Optionally, the DVFS controller includes:

[0015] A plurality of register groups for storing at least one frequency-voltage pair;

[0016] A frequency conversion register, used for storing the target frequency;

[0017] a comparator, configured to compare the target frequency with the at least one frequency-voltage pair, respectively, and output a result signal;

[0018] A frequency conversion generating unit, used for generating the frequency modulation signal according to the result signal;

[0019] A voltage generating unit is used to generate the voltage regulating signal according to the result signal.

[0020] Optionally, the DVFS controller includes:

[0021] An interrupt generation unit, used for generating an interrupt signal;

[0022] A reset generating unit, used for generating a reset signal;

[0023] A bus response unit, configured to generate a bus error signal;

[0024] The error detection unit is used to sample the result signal and instruct one of the interrupt generation unit, the reset generation unit and the bus response unit to start according to the result signal.

[0025] Optionally, any one voltage in the at least one frequency-voltage pair is a minimum voltage that enables the processing unit to operate at a corresponding frequency.

[0026] Optionally, the system on chip further includes a static storage unit for storing a plurality of frequency-voltage pairs, and the processing unit generates the at least one frequency-voltage pair according to the plurality of frequency-voltage pairs.

[0027] In a second aspect, an embodiment of the present disclosure provides a method for adjusting voltage and frequency, including:

[0028] Generate frequency configuration instructions and frequency and voltage regulation instructions;

[0029] generating at least one frequency-voltage pair according to the frequency configuration instruction;

[0030] Comparing the target frequency in the frequency and voltage modulation instruction with the at least one frequency-voltage pair;

[0031] In a case where the target frequency matches the first frequency, the clock frequency of the system is adjusted according to the first frequency, and the power supply voltage of the system is adjusted according to the voltage corresponding to the first frequency.

[0032] Optionally, the method further includes: generating an alarm signal and performing alarm processing when the target frequency does not match any frequency in the at least one frequency-voltage pair.

[0033] Optionally, the frequency configuration instruction includes an indication bit, and the indication bit is used to indicate status information when the processing unit generates the frequency configuration instruction. The method also includes: determining whether to generate an alarm signal according to the indication bit in the frequency configuration instruction.

[0034] In a third aspect, an embodiment of the present disclosure provides a computing device, including:

[0035] The system on chip as described in any one of the above items;

[0036] bus;

[0037] a storage device coupled to the system on chip via the bus;

[0038] A power management circuit is coupled to the DVFS controller in the system on chip.

[0039] According to the system on chip of the embodiment of the present disclosure, an allowable range of values ​​is configured for the system's clock frequency and power supply voltage. Frequency and voltage modulation operations within the allowable range of values ​​can be performed normally, while frequency and voltage modulation operations outside the allowable range of values ​​are rejected, thereby improving the safety of frequency and voltage modulation operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0041] Figure 1 is a schematic diagram of the structure of a system on a chip provided by an embodiment of the present disclosure;

[0042] Figure 2 is a graph of frequency and voltage;

[0043] Figure 3 yes Figure 1 An exemplary structural diagram of a DVFS controller in FIG.

[0044] Figure 4 is a flow chart of a method for adjusting voltage and frequency provided by an embodiment of the present disclosure;

[0045] Figure 5 is a schematic diagram of the structure of a general computer system used in the embodiments of the present disclosure;

[0046] Figure 6 It is a schematic diagram of the structure of the embedded system used in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0048] The system on chip of the present disclosure

[0049] Figure 1 Schematic diagram of the structure of the system on chip 100 used in the embodiment of the present disclosure.

[0050] As shown in the reference figure, the on-chip bus 102 couples various components to the processing unit 101. The on-chip bus 102 is, for example, an AXI bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 and above protocols proposed by ARM. It is an on-chip bus oriented to high performance, high bandwidth, and low latency. The AIX bus separates the address / control and data phases, supports unaligned data transmission, and supports burst transmission and out-of-order transmission, thereby meeting the requirements of ultra-high performance and complex on-chip system design.

[0051] As shown in the figure, the DVFS controller 103 and the high-speed memory 104 are coupled to the processing unit 101 through the bus 102. The DVFS controller 103 is coupled to the clock management unit 105 and the power management circuit 211 located outside the chip. In some embodiments, the power management circuit 211 may also be located in the system on chip 100. The system on chip 100 may also include an interface circuit not shown, which is coupled to an external device outside the chip through the interface circuit. The external device may be, for example, an input / output device for text, audio and video and various other memories. The system on chip 100 may access the external device outside the chip through the interface circuit. Different from the high-speed memory 104 set in the system on chip, the memory located outside the chip may have a larger capacity but a slower speed and a lower cost. In some implementations, the high-speed memory 104 may be a static random access memory (SRAM), while the memory outside the chip is a DRAM (dynamic random access memory) and a flash memory. Designers may also configure the SoC architecture so that the communication between the various components in the system on chip is secure.

[0052] As shown in the figure, basic software (such as embedded control system 121) and application programs (such as application program AN) are embedded in system on chip 100. Other application programs not shown can be stored in a memory outside system on chip 100, and these application programs can be copied to high-speed memory 104 in system on chip 100 through interface circuits and executed by processing unit 101, or access resources on system on chip 100 through interface circuits.

[0053] When the DVFS controller 103 is working, it receives frequency configuration instructions and frequency modulation and voltage regulation instructions from the on-chip bus 102. The frequency configuration instruction includes at least one frequency voltage pair. The frequency modulation and voltage regulation instruction includes a target frequency. The DVFS controller 103 reads at least one frequency voltage pair from the frequency configuration instruction and stores it as the frequency voltage table 106 in the figure. Each frequency voltage pair represents the clock frequency and the corresponding power supply voltage that can be set by the system. At the same time, the DVFS controller 103 will obtain the target frequency from the frequency modulation and voltage regulation instruction. The DVFS controller 103 compares the target frequency with each frequency voltage pair in the frequency voltage table 106. When the frequency in a certain frequency voltage pair matches the target frequency, the corresponding voltage is taken out, and a voltage regulation signal REGV is generated and sent to the power management circuit 211. The power management circuit 211 adjusts the power supply voltage VCPU provided to the system accordingly. At the same time, the DVFS controller 103 generates a frequency modulation signal REGF and sends it to the clock management unit 105. The clock management unit 105 generates the clock signal FCPU of the system. The DVFS controller 103 also refuses to perform frequency and voltage regulation operations and generates an alarm signal ALARM when the target frequency does not match any frequency in the frequency and voltage table 106 , and an alarm processing unit (not shown) performs alarm processing according to the alarm signal ALARM.

[0054] The processing unit 101 is used to generate frequency configuration instructions and frequency and voltage regulation instructions. More specifically, the processing unit 101 generates frequency configuration instructions and frequency and voltage regulation instructions when executing executable code from the embedded control system 121 or the application AN. For example, the embedded control system 121 may include computer code of the following process: first, collect signals related to the system load and calculate the current system load; then, according to the current load of the system, predict the performance required by the system in the next time period; then convert the predicted performance into the required frequency, and then call the system interface to modify the system clock frequency to the required frequency. The system interface is an interface provided by the embedded control system for calling the underlying hardware unit. When decoding and executing the above computer code, the processing unit 101 generates a frequency and voltage regulation instruction sent to the hardware DVFS controller by calling the system interface. . For another example, the processing unit 101 generates a frequency and voltage regulation instruction when executing the executable code in the application AN. In addition, the frequency configuration instruction is also generated when executing the boot program. The boot program is used to load the embedded operating system 121 after the computer is powered on. That is, during the period from when the computer is powered on to when the embedded operating system 121 works normally, the boot program is executed and generates the frequency configuration instruction. The advantage of this is that when the boot program is running, various interface circuits may not work properly yet, so it is not easy for external attack software to attack the frequency configuration instructions.

[0055] It should be noted that the frequency-voltage pair specified in the frequency configuration instruction is a verified frequency-voltage pair that enables the system to work normally.

[0056] In one implementation, the SoC 100 includes a static storage unit, which includes a plurality of frequency-voltage pairs, and the frequency-voltage pair specified in the frequency configuration instruction is included in the plurality of frequency-voltage pairs.

[0057] In another implementation, Figure 2 For example. Figure 2 The frequency and voltage curve Curve1 is shown. Each point of Curve1 represents a frequency and the minimum voltage corresponding to the frequency. The frequency configuration instruction can use the operating points (f0, v0)-(f4, v4) on Curve1 to configure the frequency-voltage pair in the DVFS controller 103. The frequency configuration instruction can also select, for example, (f0, V11) and (f2, v12) in the figure to configure the frequency-voltage pair in the DVFS controller 103, where V11 is greater than V0 and V12 is greater than V2. In this case, the power supply voltage provided to the system will have a margin. Of course, the voltage range that the power management circuit can provide also needs to be considered.

[0058] In a further implementation, the execution environment of the computer instructions of the processing unit 101 can be divided into a secure environment 1011 and a non-secure environment 1012 based on hardware. The secure environment 1011 is a more trusted instruction execution environment than the non-secure environment 1012. For example, the secure environment 1011 cannot be accessed from the outside, and the non-secure environment 1012 is accessible from the outside. The secure environment includes a hardware protection mechanism at the input and output interfaces, and the hardware protection mechanism is, for example, a register for filtering authenticated or unauthenticated data, and communication with the secure environment can be based on an encryption algorithm, etc. Optionally, the processing unit 101 generates a frequency configuration instruction in the secure environment 1011 and generates a frequency and voltage modulation instruction in the non-secure environment 1012.

[0059] In a further implementation, the execution environment of the processing unit 101 for computer instructions can be divided into user state and kernel state based on software. User state and kernel state come from the multi-user management mode. The multi-user management mode includes at least two types of users: ordinary privilege users and highest privilege users. Based on the multi-user management mode, the addressing space of the memory is divided into kernel space and user space in software logic. For example, for the Linux operating system, the highest 1G bytes (from virtual address 0xC0000000 to 0xFFFFFFFF) are used as kernel space, and the lower 3G bytes (from virtual address 0x00000000 to 0xBFFFFFFF) are used as user space. If an application is executed by an ordinary user, the code and data of the application will be loaded into the user space for execution. If an application is executed by the highest privilege user, the code and data of the application will be loaded into the kernel space for execution. Thus, when the processor processes the code in the kernel space, its working mode is called kernel state, and when the processor processes the code in the user space, its working mode is called user state. Optionally, the processing unit 101 generates a frequency configuration instruction in kernel mode, and generates a frequency and voltage adjustment instruction in user mode.

[0060] Under normal circumstances, the processing unit 101 only generates frequency configuration instructions in a secure environment or kernel mode, and only generates frequency and voltage modulation instructions in a non-secure environment or user mode, thereby ensuring the security of frequency and voltage modulation operations. However, an attack program can still destroy the generation process of the frequency configuration instruction, for example, through illegal computer instructions, the processing unit 101 generates a frequency configuration instruction in a non-secure environment, and tampering with the frequency-voltage pair in the frequency configuration instruction.

[0061] To this end, in a further implementation, the frequency configuration instruction includes an indicator bit, which is used to indicate the state information of the processing unit 101 when the frequency configuration instruction is generated. For example, when it is 0, it indicates that the processing unit 101 is in a secure environment, when it is 1, it indicates that the processing unit 101 is in a non-secure environment, or when it is 0, it indicates that the processing unit 101 is in a kernel state, and when it is 1, it indicates that the processing unit 101 is in a user state. Thus, the DVFS controller 103 can determine whether the processing unit 101 generates the frequency configuration instruction in the correct state (i.e., the secure environment or the kernel state) by detecting the indicator bit. If the AVFS controller 103 determines that the processing unit 101 generates the frequency configuration instruction in the correct state according to the indicator bit, the frequency configuration is performed. If the AVFS controller 103 determines that the processing unit 101 generates the frequency configuration instruction in the wrong state according to the indicator bit, the frequency configuration is refused to be executed and an alarm signal is given, and then the alarm processing unit performs an alarm processing according to the alarm signal. In this way, even if the attack program can destroy the generation process of the frequency configuration instruction, the AVFS controller 103 cannot complete the frequency configuration.

[0062] Figure 3 It is a schematic diagram of the structure of an exemplary DVFS controller 300. As shown in the figure, register F is used to store the target frequency. Register group FV is used to store multiple frequency voltage pairs. Multiple comparators 303 are used to compare the target frequency in register F with the frequency voltage in register group FV. If they match, the voltage generation unit 302 generates a voltage regulation signal REGV, and the frequency conversion generation unit 301 generates a frequency modulation signal FCPU. If the error detection unit 304 detects that the target frequency does not match the frequency in any frequency voltage pair, the interrupt generation unit 305, the reset generation unit 306 or the bus response unit 307 can generate an interrupt signal SINT, a reset signal RESET or a bus error signal SBUS. The error detection unit 304 is also used to detect the indication bit in the frequency configuration instruction. The interrupt signal SINT, the reset signal RESET or the bus error signal SBUS is given according to the indication bit.

[0063] The interrupt signal SINT is processed by an interrupt controller (not shown in the figure). The interrupt controller can be set inside or outside the processing unit 301. The interrupt controller defines various processing routines for various interrupt signals. When the corresponding interrupt signal occurs, the corresponding processing routine is started to perform corresponding processing. The reset signal RESET will be sent to the reset circuit (not shown), and the reset circuit will reset the system on chip 300 and restart it. The bus error signal SBUS will be sent to the bus 302 for processing.

[0064] In one implementation, the error detection unit 304 is also used to detect the indicator bit of the frequency configuration instruction to determine whether the processing unit is in a normal state when generating the frequency configuration instruction. If not, the interrupt generation unit 305, the reset generation unit 306 or the bus response unit 307 is enabled to generate an interrupt signal SINT, a reset signal RESET or a bus error signal SBUS.

[0065] According to the system on chip of the embodiment of the present disclosure, an allowable range of values ​​is configured for the system's clock frequency and power supply voltage. Frequency and voltage modulation operations on the clock frequency and power supply voltage within the allowable range of values ​​can be performed normally. Frequency and voltage modulation operations outside the allowable range of values ​​are rejected and an alarm signal is generated.

[0066] Method for adjusting voltage and frequency according to the embodiment of the present disclosure

[0067] Figure 4 The flowchart of the method for adjusting voltage and frequency according to the embodiment of the present disclosure is shown. The method can be implemented by a software program, or by a software program and a hardware module. As shown in the figure, the method includes the following steps.

[0068] In step S400, a frequency configuration instruction is generated in a safe environment. This step is completed by a processing unit, and the frequency configuration instruction is generated by acquiring a plurality of pre-stored frequency-voltage pairs, and the frequency configuration instruction includes at least one frequency-voltage pair.

[0069] In step S401, at least one frequency-voltage pair is generated according to the frequency configuration instruction. This step can be completed by the DVFS controller, that is, the DVFS controller receives the frequency configuration instruction, reads at least one frequency-voltage pair therefrom, and stores it in the DVFS controller.

[0070] In step S402, a frequency and voltage modulation instruction is generated in a non-secure environment. This step is completed by the processing unit, for example, by predicting the load of the next cycle of the system, determining the clock frequency required by the processing unit, generating a frequency and voltage modulation instruction according to the required clock frequency, and using the required clock frequency as the target frequency in the frequency and voltage modulation instruction.

[0071] In step S403, the target frequency in the frequency and voltage regulation instruction is compared with at least one frequency-voltage pair. This step can be performed by the DVFS controller. The target frequency is compared with the frequency in the frequency-voltage pair obtained in step S401 by a comparator.

[0072] In step S404, it is determined whether the target frequency matches the first frequency. The first frequency is any one of the at least one frequency-voltage pair. If the target frequency matches the first frequency, step S405 is executed, otherwise step S406 is executed.

[0073] In step S405, the clock frequency is adjusted according to the first frequency, and the supply voltage is adjusted according to the voltage corresponding to the first frequency.

[0074] In step S406, an alarm signal is generated and alarm processing is performed.

[0075] In this embodiment, at least one frequency-voltage pair is configured to limit the allowable range of values ​​of the system clock frequency and the power supply voltage provided to the system. If the frequency and voltage regulation instructions for adjusting the system clock frequency are within the allowable range, the frequency and voltage regulation can be carried out normally. If they are outside the allowable range, they are rejected and an alarm is issued, thereby improving the security of the system. At the same time, since the frequency configuration instructions are generated in a secure environment, it is not easy for attack software to destroy the generation process of the frequency configuration instructions, which also helps to improve the security of frequency and voltage regulation operations.

[0076] Furthermore, the alarm signal generated in step S406 may be an interrupt signal, a reset signal or a bus error signal. Different alarm signals are processed differently. For example, an interrupt processing routine in an embedded control system may be used to process interrupt signals and reset signals.

[0077] As another implementation method, frequency configuration instructions and frequency voltage regulation instructions are generated in different modes of the processor (including a central processing unit, a microprocessor, and a digital signal processing unit), for example, the operation of generating frequency configuration instructions is generated in kernel mode, and the operation of generating frequency voltage regulation instructions is generated in user mode.

[0078] Specific Applications of System-on-Chip

[0079] Figure 5 The general computer architecture used in the embodiments of the present disclosure is shown. As shown in the figure, the computer system 500 may include one or more processors 12 and a memory 14. The system on chip provided in the above embodiments may be used as the processor 12.

[0080] The memory 14 in the computer system 500 may be a main memory (hereinafter referred to as main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor 12, and may also be used to implement data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0081] In some cases, the processor 12 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 500 also includes a cache memory 18 coupled to the bus 11, and the cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor 12 or integrated with the processor 12 in the same system on a chip.

[0082] Based on this, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and other parts. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory. The write access request specifies the write data and the corresponding physical address that need to be written into the memory; the memory management unit 122 is used to translate the virtual addresses specified by these instructions into the physical addresses mapped by the virtual addresses. The physical address specified by the write access request may be consistent with the physical address specified by the corresponding instruction.

[0083] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0084] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 500.

[0085] In addition, the computer system 500 may also include input / output devices such as a storage device 16, a display device 13, an audio device 19, and a mouse / keyboard 15. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled to the bus 11 through a corresponding interface. The display device 13 is, for example, coupled to the bus 11 through a corresponding graphics card, and is used to display according to a display signal provided by the bus 11.

[0086] The computer system 500 also typically includes a communication device 17, so that it can communicate with a network or other devices in various ways. The communication device 17 may include, for example, one or more communication modules. As an example, the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication that complies with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication that complies with cellular or other wireless wide area protocols; the communication device 17 may also include a communication module that uses other protocols, such as a Bluetooth module, or other custom types of communication modules; the communication device 17 may also be a port for serial transmission of data.

[0087] Of course, the structure of different computer systems may vary according to the motherboard, operating system and instruction set architecture. For example, many computer systems are currently provided with an input / output control center connected between the bus 11 and various input / output devices, and the input / output control center can be integrated into the processor 12 or independent of the processor 12.

[0088] Figure 6 601 is a structural diagram of an embedded system used in the embodiment of the present disclosure. The system on chip provided in the above embodiment can be used as the processor 601.

[0089] Although embedded systems are highly similar to computer systems in hardware structure, the characteristics of embedded system applications make them quite different from general computer systems in hardware composition and implementation.

[0090] First, in order to meet the requirements of the embedded system 600 in terms of speed, volume and power consumption, the operating system, application software, special data and other data that need to be stored for a long time usually do not use storage media such as disks with large capacity and slow speed, but mostly use random access memory 602 or flash memory (Flash Memory) 603.

[0091] In addition, in the embedded system 600, an A / D (analog / digital conversion) interface 605 and a serial interface 606 are required for the needs of measurement and control, which are rarely used in general-purpose computers. The A / D interface 605 mainly completes the conversion of analog signals to digital signals and the conversion of digital signals to analog signals required in the test. When the embedded system 600 is applied to industrial production, it often needs to be tested. Since the single-chip microcomputer generates digital signals, it needs to be converted into analog signals for testing during testing. Therefore, unlike general-purpose computers, an A / D (analog / digital conversion) interface 605 is required to complete the relevant conversion. In addition, in industry, multiple embedded systems are often required to be connected in series to complete relevant functions, so a serial interface 606 is required for connecting multiple embedded systems in series, which is mostly not required in general-purpose computers.

[0092] In addition, as a basic processing unit, the embedded system 600 often needs to connect multiple embedded systems 600 into a network in industrial design, so a network interface 607 is needed to connect the embedded system 600 to the network. This is also not needed in general-purpose computers. In addition, according to the actual application and scale, some embedded systems 600 need to use external buses 604. With the rapid expansion of the application field of embedded systems 600, embedded systems 600 are becoming more and more personalized, and the types of buses used according to their own characteristics are also increasing. In addition, in order to test the internal circuits of the embedded processor 601, the processor chip generally adopts boundary scan test technology. In order to adapt to this test, a debug interface 608 is adopted.

[0093] With the rapid development of very large scale integration (VLSI) and semiconductor technology, part or all of the above embedded systems can be implemented on a silicon chip, namely, an embedded system on chip (SoC).

[0094] The commercial value of the disclosed embodiments

[0095] The system-on-chip provided by the embodiment of the present disclosure reduces the system power consumption on the basis of ensuring the safety of frequency and voltage modulation operations, and can form a computing device used in a variety of scenarios, such as a large number of cloud servers in a data center. In this scenario, by reducing the power consumption of the processor, the power consumption of each cloud server is reduced, thereby reducing the operating cost of each cloud server and the entire data center; for example, ultra-small electronic products used in daily life, such electronic products have limited battery capacity due to size limitations, so it is necessary to reduce the power consumption of electronic products to help extend the use time of electronic products. Therefore, the system-on-chip of the embodiment of the present disclosure and the computing device constructed by the system-on-chip have commercial value and economic value on the basis of practical value.

[0096] Those skilled in the art will appreciate that the present disclosure may be implemented as systems, methods, and computer program products. Therefore, the present disclosure may be specifically implemented in the following forms, namely complete hardware, complete software (including firmware, resident software, microcode), and may also be implemented in the form of a combination of software and hardware. In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, which contains computer-readable program code.

[0097] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media include: an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this article, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by a processing unit, a device or a device, or used in combination with the program.

[0098] Computer readable signal media may include data signals propagated in baseband or as part of a chopped wave, which carry computer readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer readable signal media may also be any computer readable medium other than a computer readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction system, apparatus, or device.

[0099] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

[0100] The computer program code for executing the disclosed embodiments may be written in one or more programming languages ​​or combinations. The programming languages ​​include object-oriented programming languages, such as JAVA, C++, and may also include conventional procedural programming languages, such as C. The program code may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet).

[0101] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A system on chip, comprising: A processing unit, used for generating frequency configuration instructions and frequency and voltage modulation instructions; The DVFS controller is used to configure at least one frequency-voltage pair according to a frequency configuration instruction, and when a target frequency of the frequency-voltage modulation instruction matches a first frequency in the at least one frequency-voltage pair, generate a frequency modulation signal based on the first frequency, and generate a voltage modulation signal based on a voltage corresponding to the first frequency, wherein the frequency modulation signal is used to adjust a clock frequency of the system on chip, and the voltage modulation signal is used to adjust a power supply voltage of the system on chip; an on-chip bus coupling the processing unit and the DVFS controller, The DVFS controller includes: A plurality of register groups for storing at least one frequency-voltage pair; A frequency conversion register, used for storing the target frequency; a comparator, configured to compare the target frequency with the at least one frequency-voltage pair, respectively, and output a result signal; An interrupt generation unit, used for generating an interrupt signal; A reset generating unit, used for generating a reset signal; A bus response unit, configured to generate a bus error signal; An error detection unit is used to sample the result signal, and when the result signal indicates that the target frequency does not match any frequency in the at least one frequency-voltage pair, instruct one of the interrupt generation unit, the reset generation unit and the bus response unit to start.

2. The system on chip according to claim 1, wherein: The processing unit includes a secure environment and a non-secure environment divided in hardware. The processing unit generates the frequency configuration instruction in the secure environment and generates the frequency and voltage modulation instruction in the non-secure environment.

3. The system on chip according to claim 1, wherein: The processing unit switches between the user state and the kernel state, and generates the frequency configuration instruction in the kernel state, and generates the frequency and voltage modulation instruction in the user state.

4. The system on chip according to claim 1, wherein the frequency configuration instruction includes an indication bit, and the indication bit is used to indicate status information when the processing unit generates the frequency configuration instruction, and the DVFS controller is further used to determine whether to generate an alarm signal according to the indication bit in the frequency configuration instruction.

5. The system on chip according to claim 1, wherein the DVFS controller further comprises: A frequency conversion generating unit, used for generating the frequency modulation signal according to the result signal; A voltage generating unit is used to generate the voltage regulating signal according to the result signal. 6 . The system on chip according to claim 1 , wherein any one voltage in the at least one frequency-voltage pair is a minimum voltage that enables the processing unit to operate at a corresponding frequency. 7 . The system on chip according to claim 1 , further comprising a static storage unit for storing a plurality of frequency-voltage pairs, wherein the processing unit generates the at least one frequency-voltage pair according to the plurality of frequency-voltage pairs.

8. A computing device, comprising: The system on chip according to any one of claims 1 to 7; bus; a storage device coupled to the system on chip via the bus; A power management circuit is coupled to the DVFS controller.

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