A multiplierless transform circuit based on an optimized RAG-n algorithm

Abstract

The application relates to a multiplier-free transform circuit based on an optimized RAG-n algorithm. The circuit comprises an input module for transforming input data according to a preset number of points and delivering the input data to an SAU module; the SAU module is connected with the input module and is used for calculating the product of the input data and a preset coefficient and sending the product of the input data and the preset coefficient to an addition tree module; the addition tree module is connected with the SAU module and is used for receiving the output result of the SAU module and selecting and accumulating the output result based on a transform matrix to obtain a transform result; and an output module is connected with the addition tree module and is used for outputting the transform result. The several transform circuits based on the optimized RAG-n algorithm provided by the application have small circuit areas, low resource consumption and universality and can be easily transplanted into various encoding protocols.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of coding and circuit, more specifically, the present application relates to a kind of multiplication-free transform circuit based on optimization RAG-n algorithm. BACKGROUND

[0002] Transform module plays a crucial role in video codec, and is one of the important tools to improve the compression performance of encoder. In the new generation of video coding protocol AVS3, position-based transform (PBT) is used, which introduces two new transform types in addition to the traditional discrete cosine transform type II (DCT-II): discrete sine transform type VII (DST-VII) and discrete cosine transform type VIII (DCT-VIII), which further improves the compression performance. It is worth noting that the introduction of new transform types brings not only coding gain but also very high computational complexity, increasing the encoding time and the circuit area of the transform module.

[0003] To overcome the above difficulties, some existing inventions and research have made certain contributions. In 1965, J.W. Cooley and T.W. Tukey proposed the butterfly algorithm, which can save at least 2 / 3 of the number of multipliers by using the symmetry of the coefficients in the DCT-II transform matrix. However, since the DST-VII / DCT-VIII transform matrix does not have similar properties, the butterfly algorithm cannot be used for optimization design of these two transform types. Later, someone proposed a highly parallel transform framework in a paper that can support DCT-II, DST-VII, and DCT-VIII in VVC. And using N-dimensional reduced adder graph algorithm (RAG-n) to optimize the design of DST-VII / DCT-VIII type shift accumulation unit, a multiplication-free DST-VII / DCT-VIII module is realized, reducing the computational complexity and circuit area. However, since the DCT-II transform matrix does not have similar properties as DST-VII / DCT-VIII, this method only uses DST-VII / DCT-VIII in the paper, and the DCT-II type still uses the traditional butterfly algorithm, resulting in a large number of multipliers in the entire transform module and wasting circuit area. It is not difficult to find that using existing methods to implement the transform module of AVS3 will face problems such as large circuit area and excessive resource consumption. SUMMARY

[0004] Based on the above technical problems, the present application aims to provide SAU circuit structures of various sizes based on the optimized RAG-n algorithm, including circuits of DCT-II transform type, circuits of DST-VII transform type and circuits of DCT-VIII transform type.

[0005] The embodiments of the present application provide various implementations of the multiplierless transform circuit based on the optimized RAG-n algorithm. In order to have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This part is not a general review, nor is it intended to determine the key / important components or delineate the protection scope of these embodiments. Its only purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0006] The first aspect of the present application provides a multiplierless transform circuit based on the optimized RAG-n algorithm, comprising:

[0007] An input module configured to transform input data according to a preset number of points and pass the input data to an SAU module;

[0008] An SAU module connected to the input module, configured to calculate the product of the input data and a preset coefficient and send the product of the input data and the preset coefficient to an addition tree module;

[0009] An addition tree module connected to the SAU module, configured to receive the output result of the SAU module and select and accumulate the output result based on a transform matrix to obtain a transform result;

[0010] An output module connected to the addition tree module, configured to output the transform result.

[0011] Specifically, the preset number is four, and the SAU module is composed of five adders and four shifters.

[0012] Specifically, the preset number is eight, and the SAU module is composed of seven adders and five shifters.

[0013] Specifically, the preset number is sixteen, and the SAU module is composed of thirteen adders and six shifters.

[0014] Further, the input module is further configured to fine-tune the input data, and the output module is further configured to fine-tune the transform result, wherein the output module fine-tunes the transform result while the input module fine-tunes the input data.

[0015] Further, the input module fine-tunes the input data by passing the input data to the SAU module in reverse order, and the output module fine-tunes the transformation result by negating the odd-indexed result of the transformation result, where the index starts from 0.

[0016] The second aspect of the present application provides a multiplier-free transformation circuit based on an optimized RAG-n algorithm, which comprises, sequentially connected, an input module, an SAU module, an addition tree module, and an output module, wherein the SAU module is formed by cascading SAUs of different sizes, and the SAUs of different sizes receive data passed by the input module or data output by the upper-level SAU in the cascade.

[0017] Specifically, the SAUs of different sizes include two-point SAUs, four-point SAUs, eight-point SAUs, sixteen-point SAUs, and thirty-two-point SAUs.

[0018] The third aspect of the present application provides an optimized RAG-n algorithm, which is applied to the multiplier-free transformation circuit described in the embodiments of the present application, and the execution steps of the optimized RAG-n algorithm are as follows:

[0019] S1, divide all coefficients by 2 or -2 to obtain corresponding positive odd numbers, and store the results in an incomplete set;

[0020] S2, look up a table to obtain the optimal cost of all individual coefficients;

[0021] S3, remove the coefficients with a cost of zero and the repeated coefficients in the incomplete set;

[0022] S4, remove the coefficients with a cost of 1 in the incomplete set and store them in a graph set;

[0023] S5, calculate all positive integers with a cost of 0 that can be generated by the elements of the graph set within a limited word length, store them in a cost0 set, then add or subtract them two by two, and if a coefficient in the incomplete set is obtained, remove the coefficient from the incomplete set and store it in the graph set;

[0024] S6, repeat S5 until no coefficient is added to the graph set;

[0025] wherein the incomplete set is initially empty, the initial element of the graph set is only 1, and cost represents the cost of the adder.

[0026] Further, the optimized RAG-n algorithm further comprises: adding new coefficients, and selecting the optimal coefficients from the added new coefficients by traversing S1 to S6.

[0027] The DCT-VIII type of circuit provided in the application can realize the DST-VII type of circuit by fine-tuning the input module and the output module, thereby improving the multiplexing rate of the circuit and saving resources. The SAU module in the DCT-II type of transform circuit is formed by cascading SAUs of different sizes, and also uses a smaller circuit area, which greatly improves the transform efficiency. The optimized RAG-n algorithm adds new coefficients, and selects the optimal coefficients from the added new coefficients by traversing, so as to reduce the number of adders. In summary, the several transform circuits designed based on the optimized RAG-n algorithm provided in the application have smaller circuit area, less resource consumption, and universality, and can be easily transplanted into various coding protocols. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which form a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0029] The present application can be more clearly understood and appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 Fig. 1 shows a DCT-VIII / DST-VII type of circuit structure schematic diagram of an exemplary embodiment of the present application;

[0031] Figure 2 Fig. 2 shows an internal circuit structure schematic diagram of the SAU module in an exemplary embodiment of the present application;

[0032] Figure 3 Fig. 3 shows a schematic diagram of a circuit composed of four adders and a circuit composed of three adders in an exemplary embodiment of the present application;

[0033] Figure 4 Fig. 4 shows a circuit optimization comparison schematic diagram after introducing the RAG-n algorithm in an exemplary embodiment of the present application;

[0034] Figure 5 Fig. 5 shows a DCT-II type of transform circuit structure schematic diagram of an exemplary embodiment of the present application;

[0035] Figure 6 Fig. 6 shows a schematic diagram of several different sizes of SAU structures in the DCT-II type of transform circuit in an exemplary embodiment of the present application;

[0036] Figure 7A structural schematic diagram of an electronic device according to an example embodiment of the present application is shown.

[0037] Figure 8 A schematic diagram of a storage medium according to an example embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present application, and is not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known functions and constructions are omitted to avoid obscuring the concept of the present application. It will be obvious to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, well-known features are not described in detail to avoid obscuring this application. In addition, it should be understood that the terms "comprise" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0039] It is to be understood that the terms used herein are merely exemplary based on the example embodiments of the present application, and are not intended to limit the scope of the present application. As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0040] The example embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. The example embodiments may, however, be implemented in many different ways, and should not be construed as being limited to the embodiments set forth herein. The drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and others omitted in order not to obscure the concept of the present application. The shapes and relative sizes of the various regions, layers, and elements illustrated in the drawings are exemplary only, and may vary as a matter of design or engineering choice, and depending on manufacturing processes or technical limitations. The same reference numerals in different drawings represent the same or similar elements.

[0041] The example embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. The example embodiments may, however, be implemented in many different ways, and should not be construed as being limited to the embodiments set forth herein. The drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and others omitted in order not to obscure the concept of the present application. The shapes and relative sizes of the various regions, layers, and elements illustrated in the drawings are exemplary only, and may vary as a matter of design or engineering choice, and depending on manufacturing processes or technical limitations. The same reference numerals in different drawings represent the same or similar elements. Figures 1-8 Several embodiments will be given to describe the example embodiments according to the present application. It is to be noted that the following application scenarios are merely exemplary to facilitate understanding of the spirit and principles of the present application, and the embodiments of the present application are not limited in this respect. On the contrary, the embodiments of the present application can be applied to any applicable scenario.

[0042] Embodiment 1:

[0043] This embodiment provides a multiplier-free transformation circuit based on an optimized RAG-n algorithm, such as... Figure 1 As shown, it includes:

[0044] The input module is used to transform the input data according to a preset number of points and pass the input data to the SAU (Addition Shift Unit) module;

[0045] The SAU module, connected to the input module, is used to calculate the product of the input data and preset coefficients, and send the product of the input data and preset coefficients to the addition tree module;

[0046] The addition tree module, connected to the SAU module, is used to receive the output of the SAU module, and select and accumulate the output based on the transformation matrix to obtain the transformation result;

[0047] The output module, connected to the addition tree module, is used to output the transformation result.

[0048] Specifically, such as Figure 2 In the SAU4 module, the preset number is four, and the SAU module consists of five adders and four shifters.

[0049] Specifically, such as Figure 2 The SAU8 in the example has a preset number of eight, and the SAU module consists of seven adders and five shifters.

[0050] Specifically, such as Figure 2 The SAU16 in the example has a preset number of sixteen, and the SAU module consists of thirteen adders and six shifters.

[0051] It should be noted that the conversion circuit implemented here is of the DST-VII type, and the 4-point SAU consists of 5 adders and 4 shifters. As a convertible implementation, if a DCT-II type conversion circuit is used, the 4-point SAU consists of 4 adders and 4 shifters.

[0052] Example 2:

[0053] This embodiment provides an optimized RAG-n algorithm. The full name of the N-Dimensional Reduced Adder Graph algorithm is N-Dimensional Reduced Adder Graph algorithm, abbreviated as RAG-n. The RAG-n algorithm is often used to design multiplier-free multiplication units with the fewest adders. For example, when the input is x, the output is {x, 7x, 16x, 21x, 33x}. A multiplication-free multiplication unit is as follows: Figure 3(a) shows, the module uses 4 adders. When we use the RAG-n algorithm to optimize the module, only 3 adders are needed, as shown in Figure 3 (a). Wherein, the circular table adder, rectangular table shifter, and the circle inside minus sign are also considered as adders, i.e. the subtractor is considered as an adder by default. The circuit based on the RAG-n algorithm can reduce the circuit area of one adder compared with the general implementation.

[0054] The optimized RAG-n algorithm in the embodiment is executed as follows:

[0055] S1, divide all coefficients by 2 or -2 to get corresponding positive odd numbers, and store the results in the incomplete set;

[0056] S2, look up the table to get the optimal cost of all individual coefficients;

[0057] S3, remove the coefficients with cost of zero and repeated coefficients in the incomplete set;

[0058] S4, remove the coefficients with cost = 1 in the incomplete set and store them in the graph set;

[0059] S5, calculate all positive integers with cost = 0 that can be generated by the elements of the graph set within the limited word length, store them in the cost0 set, and then add or subtract them two by two. If a coefficient in the incomplete set is obtained, remove the coefficient from the incomplete set and store it in the graph set;

[0060] S6, repeat S5 until no coefficient is added to the graph set;

[0061] Wherein, the incomplete set is initially empty, the initial element of the graph set is only 1, and cost represents the cost of the adder.

[0062] In the above steps, if the incomplete set is empty, i.e. all coefficients have been synthesized, the algorithm ends. The above steps belong to the optimal part of the algorithm, in addition to which there is a heuristic part S7 searching for two distance = 2 cases. If a coefficient is not synthesized in the optimal part, it means that the coefficient cannot be obtained by only one adder of the existing node, indicating that the addition distance of the coefficient and the existing node is greater than or equal to 2, i.e. distance ≥ 2. First, search for two distance = 2 cases: one is whether the difference between the coefficient and the value of the existing node exists a number with cost = 1; the other is whether the difference between the coefficient and the value of any two nodes exists a number with cost = 0. Both of the above two cases can obtain the coefficient by adding two adders.

[0063] S6 and S7 are repeatedly executed until no coefficient is synthesized. If this step is reached, it means that there are coefficients with distance > 2 from the existing nodes or the case of distance = 2 is not searched in S7, at this time, some nodes need to be added to increase the search range. Until all the coefficients are synthesized, if all the coefficients can be synthesized in the optimal part, the result can guarantee that the total number of adders is the least, otherwise, the remaining coefficients will be synthesized in the heuristic part, which cannot guarantee the optimal result. The heuristic part has large calculation amount, long calculation time and randomness.

[0064] Therefore, further, the optimized RAG-n algorithm further comprises: adding new coefficients, and selecting the optimal coefficient from the added new coefficients by traversing S1 to S6. Some additional coefficients are added in the original coefficient set, which satisfy: cost = 1, that is, can be obtained by 1 adder, the value of the added additional coefficient does not exceed 17, and the number of the added additional coefficients does not exceed 2. Specifically, a coefficient list {3, 5, 6, 7, 9, 10, 14, 15, 17} satisfying the above two conditions is given, and the best additional coefficient value is selected from the list by traversal. Taking the coefficient {15, 21, 27, 37, 42} as an example, the result of the original RAG-n algorithm is shown on the left of Figure 4 . After the traversal process of the original RAG-n algorithm is performed, it can be known that when 6 is added to the coefficient list, the resources of the circuit can be minimized. At this time, the series list is updated to {6, 15, 21, 27, 37, 42}. The result of the optimized RAG-n algorithm is shown on the right of Figure 4 . It can be seen that compared with the original RAG-n algorithm, the optimized RAG-n algorithm can save one adder.

[0065] Embodiment 3:

[0066] The embodiment provides a multiplier-free transformation circuit based on an optimized RAG-n algorithm, which comprises an input module configured to input data according to a preset number of points and transmit the input data to an SAU module; the SAU module is connected with the input module and is configured to calculate the product of the input data and a preset coefficient and transmit the product of the input data and the preset coefficient to an adder tree module; the adder tree module is connected with the SAU module and is configured to receive the output result of the SAU module and select and accumulate the output result based on a transformation matrix to obtain a transformation result; and an output module connected with the adder tree module and configured to output the transformation result.

[0067] Further, the input module is further configured to fine-tune the input data, and the output module is further configured to fine-tune the transform result, wherein the output module fine-tunes the transform result while the input module fine-tunes the input data.

[0068] Further, the input module fine-tunes the input data by inputting the input data to the SAU module in reverse order, and the output module fine-tunes the transform result by inverting the result of the odd index of the transform result, wherein the index starts from 0.

[0069] The DST-VII transform type circuit and the DCT-VIII transform type circuit can be converted through the above fine-tuning, in other words, the DST-VII transform type circuit and the DCT-VIII transform type circuit can reuse the same SAU circuit structure. The transform matrices of the two have the following relationship:

[0070]

[0071]

[0072] The even row value sequence of the DCT-VIII is reversed from left to right, the sign is unchanged, and the odd row value sequence of the DCT-VIII is reversed from left to right, the sign is opposite, and the transform matrix of the DST-VII can be obtained. Wherein, the index starts from 0. From the above two points, combined with the process of one-dimensional transform, if the DCT-VIII circuit has been designed, only the following two operations on the input and output of the circuit can obtain the transform result of the DST-VII: input the input in reverse order into the DCT-VIII circuit, and invert the output result of the DCT-VIII at the odd position. Without increasing additional calculation resources, only the fine-tuning of the input and output is needed, the DCT-VIII circuit can be used to realize the function of the DST-VII, the reuse rate of the circuit is improved, and the circuit area is reduced.

[0073] For example, as shown in the input module: Figure 1 The number of input data of the DST-VII / DCT-VIII 4-point transform is 4, and the 4 residual data {X0, X1, X2, X3} are input into the subsequent module in a certain order (DST-VII is forward input, and DCT-VIII is reverse input).

[0074] The SAU module is the key in the DST-VII / DCT-VIII circuit structure. The function is to output the product of the input data and the corresponding coefficient. The DST-VII and the DCT-VIII reuse the same SAU circuit structure. Taking the DST-VII 4-point transform as an example, the internal circuit of SAU-4 is as follows:Figure 2 As shown, the internal circuit of SAU-8 is composed of 5 adders and 4 shifters. Similarly, when 8-point transform, the internal circuit of SAU-8 is composed of 7 adders and 5 shifters. When 16-point transform, the internal circuit of SAU-8 is composed of 13 adders and 6 shifters.

[0075] The function of the adder tree module is to select and accumulate the output results of different SAUs in the previous stage. The input of this module is all the output results of the SAU module in the previous stage, and the output is the accumulated data. The selection method is determined according to the calculation process of one-dimensional transform, such as Figure 1 As shown, taking DST-VII 4-point transform as an example, the input selection of the first accumulator is {15X0, 27X1, 37X2, 42X3}, which corresponds to the multiplication and accumulation result of the input data and the first row of the transform matrix. The input selection of the second accumulator is {37X0, 37X1, 0, 37X3}, which corresponds to the multiplication and accumulation result of the input data and the second row of the transform matrix, and so on. The absolute values of all the coefficients of the input data after DST-VII 4-point transform can be obtained.

[0076] The output module is to select and fine-tune the output of the adder tree module to obtain the final result of the DST-VII / DCT-VIII transform circuit. The input is the four outputs of the adder tree module, and the four final output transform coefficient results {Y0, Y1, Y2, Y3} are obtained after fine-tuning. The fine-tuning rule is that for DST-VII transform, the result of the adder tree is directly output as the final result, and for DCT-VIII, the even-indexed result remains unchanged, and the odd-indexed result is inverted and output, where the index starts from 0. When fine-tuning in the output module, the premise is that the input module also fine-tunes the input data, i.e. the input data is passed to the adder tree module in the opposite order.

[0077] Embodiment 4:

[0078] This embodiment provides a multiplierless transform circuit based on an optimized RAG-n algorithm, as shown in Figure 5 As shown, the circuit includes sequentially connected input module, SAU module, adder tree module and output module, the SAU module is cascaded by SAUs of different sizes, and the SAUs of different sizes receive data passed by the input module or receive data output by the SAU in the previous stage in the cascade.

[0079] The above circuit is the structure of the DCT-II transform circuit. For the design of the DCT-II circuit, the design method of the DST-VII / DCT-VIII cannot be directly used because the transform matrix does not have the characteristics of the transform matrix of the latter. However, through our exploration, after the use of the butterfly algorithm optimization for the DCT-II, the internal calculation circuit can still be optimized and designed using the RAG-n algorithm. Therefore, the application provides a unified transform architecture that supports a maximum of 64-point size and is compatible with various small sizes (referring to sizes less than 64). The architecture can greatly reduce the circuit area.

[0080] The circuit includes SAUs of five sizes. As shown in Figure 6 The different sizes of the SAUs include a two-point size SAU, a four-point size SAU, an eight-point size SAU, a sixteen-point size SAU, and a thirty-two-point size SAU. The different sizes of the SAUs are cascaded, and the input data source of each SAU can come from two parts, the output of the previous stage or the input data of the overall module.

[0081] Next, the running process of the circuit architecture is briefly introduced by taking a 64-point transform as an example. First, after the odd-even decomposition (basic calculation rule of the butterfly transform) of the 64 input data, two parts of data, 32 E (even) data and 32 O (odd) data, are obtained. The O data enters the SAU32 to obtain 32 final output coefficient results. The E data continues to be decomposed, and 16 EE data and 16 EO data are obtained. The EO data enters the SAU16 to obtain 16 final transform coefficient results. The EE data continues to be decomposed. In this way, the final 64 transform coefficient results are obtained.

[0082] Next, the data source of the SAU module is explained by taking a 32-point transform as an example.

[0083] For a 32-point transform, there are only 32 data in total. After the odd-even decomposition of the 32 input data, 16 E data and 16 O data are obtained. The O data enters the SAU16 to obtain the final output coefficient result, and the E data continues to be decomposed and operated. At this time, the data source of the SAU16 is no longer the previous stage, but is obtained from the input data. It is worth noting that the input data of the SAU32 in the overall architecture is 0, and the output is 0, that is, the data of the SAU unit is invalid.

[0084] The DCT-VIII transform type circuit provided in the application can realize the DST-VII transform type circuit by fine tuning the input module and the output module, thereby improving the multiplexing rate of the circuit and saving resources. The SAU module in the DCT-II type transform circuit is formed by cascading SAUs of different sizes, and a smaller circuit area is also used, which greatly improves the transform efficiency. The optimized RAG-n algorithm increases new coefficients and selects the optimal coefficient from the increased new coefficients by using the traversal method, so as to reduce the number of adders. In summary, the several transform circuits designed based on the optimized RAG-n algorithm provided in the application have smaller circuit area, less resource consumption, and universality, and can be easily transplanted into various encoding protocols.

[0085] Please refer to Figure 7 , which shows a schematic diagram of an electronic device provided by some embodiments of the application. As Figure 7 shown, the electronic device 2 includes a processor 200, a memory 201, a bus 202 and a communication interface 203, the processor 200, the communication interface 203 and the memory 201 are connected through the bus 202; the memory 201 stores a computer program executable on the processor 200, and the processor 200 executes the computer program to perform the optimized RAG-n algorithm in any of the preceding embodiments of the application.

[0086] The memory 201 can include a high-speed random access memory (RAM) and can also include a non-volatile memory such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 203 (which can be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. can be used.

[0087] The bus 202 can be an ISA bus, a PCI bus or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs, and the processor 200 executes the programs after receiving execution instructions. The open big data processing method disclosed in any of the preceding embodiments of the application can be applied to the processor 200 or implemented by the processor 200.

[0088] The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 200 or by instructions in software form. The processor 200 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 201. The processor 200 reads the information in memory 201 and, in conjunction with its hardware, completes the steps of the optimized RAG-n algorithm described above.

[0089] This application also provides a computer-readable storage medium, please refer to... Figure 8 , Figure 8 The computer-readable storage medium shown is an optical disc 30, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it executes the open big data processing method provided in any of the foregoing embodiments. Examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other optical or magnetic storage media, which will not be elaborated further here.

[0090] The computer-readable storage medium provided in the above embodiments of this application and the quantum key distribution channel allocation method in the space division multiplexing optical network provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0091] This application also provides a computer program product, including a computer program that, when executed by a processor, implements an optimized RAG-n algorithm.

[0092] It should be noted that the algorithms and displays presented herein are not inherently related to any particular computer, virtual apparatus, or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the present application is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the application as described herein, and any references below to specific languages are provided for disclosure of enablement only.

[0093] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to avoid obscuring the understanding of this description.

[0094] Similarly, it is to be understood that the mechanical details of the application that have been set forth above in the context of a few illustrative embodiments are for purposes of example only and that various modifications, changes and adaptations will be apparent to those skilled in the art. Number of specific details given herein are meant to be illustrative only and therefore specific embodiments of the application have been shown by way of example in the drawings and will be described in detail in the text which follows. Other embodiments of the application encompass any and all modifications, variations and / or combinations thereof within the scope of the claims.

[0095] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and further can be divided into more sub-modules or sub-units or sub-components. Any combination of all disclosed features in the specification (including the accompanying claims, abstract and drawings) and all processes or units of any method or apparatus disclosed so disclosed can be taken, except that at least some of such features and / or processes or units are mutually exclusive. Unless explicitly stated otherwise, each feature disclosed in the specification (including the accompanying claims, abstract and drawings) can be replaced by alternative features that serve the same, equivalent or similar purpose.

[0096] Furthermore, those skilled in the art will recognize that, in keeping with the scope of the present application, the

[0097] Various component embodiments of the present application can be implemented in hardware, or as software modules running in one or more processors, or in combinations thereof. As will be appreciated by those skilled in the art, a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functionality of some or all of the components of the virtual machine creation apparatus according to embodiments of the present application. The present application can also be implemented as a program of instructions for performing part or all of the methods described herein, e.g., a computer program and a computer program product. Such program of the present application can be stored on a computer readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or in any other form.

[0098] The above description is only preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An optimized RAG-n algorithm, characterized in that, The optimized RAG-n algorithm is applied to a multiplierless transform circuit, and the multiplierless transform circuit comprises: an input module configured to transform input data according to a preset number of points and deliver the input data to an SAU module; the SAU module is connected to the input module and configured to calculate the product of the input data and a preset coefficient and send the product of the input data and the preset coefficient to an addition tree module; the addition tree module is connected to the SAU module and configured to receive the output result of the SAU module and select and accumulate the output result based on a transform matrix to obtain a transform result, wherein the transform matrix is a mutual transform matrix between a DST-VII transform type circuit and a DCT-VIII transform type circuit; an output module connected to the addition tree module and configured to output the transform result; wherein the input module, the SAU module, the addition tree module and the output module are sequentially connected, the SAU module is cascaded by SAUs of different sizes, and the SAUs of different sizes receive data delivered by the input module or data output by the SAU of the previous stage in the cascade; the execution steps of the optimized RAG-n algorithm are as follows: S1, divide all coefficients by 2 or -2 to obtain corresponding positive odd numbers, and store the results in an incomplete set; S2, look up a table to obtain the optimal cost of all individual coefficients; S3, remove the coefficients with a cost of zero and the repeated coefficients in the incomplete set; S4, remove the coefficients with a cost of 1 in the incomplete set and store them in a graph set; S5, calculate all positive integers with a cost of 0 that can be generated by the elements of the graph set within a limited word length, store them in a cost0 set, and then add or subtract them two by two, if a coefficient in the incomplete set is obtained, remove the coefficient from the incomplete set and store it in the graph set; S6, repeat S5 until no coefficient is added to the graph set; wherein the incomplete set is initially empty, the initial element of the graph set is only 1, and cost represents the cost of an adder; The optimized RAG-n algorithm further comprises adding new coefficients and selecting the optimal coefficients from the added new coefficients by traversing S1 to S6; wherein the added new coefficients need to satisfy that the cost is equal to 1, i.e., it can be obtained by one adder, and the value of the added new coefficient is not more than 17, and the number of added new coefficients is not more than 2.

2. The optimized RAG-n algorithm of claim 1, wherein, The preset number is four, and the SAU module is composed of five adders and four shifters.

3. The optimized RAG-n algorithm of claim 1, wherein, The preset number is eight, and the SAU module is composed of seven adders and five shifters.

4. The optimized RAG-n algorithm of claim 1, wherein, The preset number is sixteen, and the SAU module is composed of thirteen adders and six shifters.

5. The optimized RAG-n algorithm of claim 1, wherein, The input module is further configured to fine-tune the input data, and the output module is further configured to fine-tune the transformation result, wherein the output module fine-tunes the transformation result while the input module fine-tunes the input data.

6. The optimized RAG-n algorithm of claim 5, wherein, The input module fine-tunes the input data by passing the input data to the SAU module in a reverse order, and the output module fine-tunes the transformation result by inverting the result of the odd-indexed result of the transformation result, wherein the index starts from 0.

7. The optimized RAG-n algorithm of claim 1, wherein, The different sizes of the SAU include a two-point size SAU, a four-point size SAU, an eight-point size SAU, a sixteen-point size SAU and a thirty-two-point size SAU.

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