Semiconductor memory devices

Abstract

This invention relates to a semiconductor memory device including a drive voltage supply circuit adapted to selectively supply a first drive voltage, a second drive voltage, a third drive voltage, a ground voltage, and a precharge voltage to a first drive line and a second drive line in response to an activation signal, a cell feature information signal, and a precharge signal. The semiconductor memory device also includes a sense amplifier adapted to operate by being applied voltages supplied from the first and second drive lines.

Description

[0001] This application is a divisional application of a patent application with an application date of October 10, 2017, application number 201710935388.8, and invention name “Semiconductor Memory Device”. Technical Field

[0002] Various embodiments relate generally to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device. Background Art

[0003] The semiconductor memory device is configured to store data and output the stored data.

[0004] Memory cells storing data in a semiconductor memory device may have different times for retaining the stored data according to their characteristics.

[0005] It is inefficient to read and amplify memory cells with different characteristics under the same conditions. Summary of the invention

[0006] In an embodiment, a semiconductor memory device may include: a driving voltage supply circuit adapted to selectively supply a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an activation signal, a cell characteristic information signal, and a precharge signal; and a read-out amplifier adapted to operate by being applied with a voltage supplied from the first driving line and the second driving line.

[0007] In an embodiment, a semiconductor memory device may include: a plurality of mats; a plurality of read amplifiers electrically connected to the plurality of mats, respectively; and a plurality of driving voltage supply circuits adapted to selectively supply driving voltages to the plurality of read amplifiers, respectively, in response to a plurality of cell characteristic information signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a configuration diagram showing a representation of an example of a semiconductor memory device according to an embodiment.

[0009] Figure 2 It is shown Figure 1 The shown diagram is a configuration diagram showing an example of a voltage supply circuit.

[0010] Figure 3 It is shown Figure 1 A configuration diagram showing an example of a precharge voltage generating circuit is shown.

[0011] Figure 4 is a configuration diagram showing a representation of an example of a semiconductor memory device according to an embodiment.

[0012] Figure 5Show that the above Figures 1 to 4 A block diagram of an example of a system representation of a semiconductor memory device of the various embodiments discussed. DETAILED DESCRIPTION

[0013] Hereinafter, a semiconductor memory device will be described with reference to the accompanying drawings through various examples of embodiments.

[0014] like Figure 1 As shown, the semiconductor memory device according to the embodiment may include a driving voltage supply circuit 100 , a cell characteristic information storage circuit 200 , a precharge voltage generation circuit 300 , and a sense amplifier 400 .

[0015] The driving voltage supply circuit 100 may selectively apply at least one of the first driving voltage V_A, the second driving voltage V_B, the third driving voltage V_C, the ground voltage VSS and the pre-charge voltage V_pcg to at least one of the first driving line RTO and the second driving line SB in response to at least one of the activation signal ACT, the cell characteristic information signal C_inf and the pre-charge signal PCG. For example, the driving voltage supply circuit 100 may selectively supply two driving voltages of the first to third driving voltages V_A, V_B and V_C to the first driving line RTO in response to the activation signal ACT and the cell characteristic information signal C_inf, and supply the ground voltage VSS to the second driving line SB. The driving voltage supply circuit 100 may supply the pre-charge voltage V_pcg to the first driving line RTO and the second driving line SB in response to the pre-charge signal PCG. The first driving voltage V_A may be a first external voltage (VDD), the second driving voltage V_B may be a core voltage (VCORE), and the third driving voltage V_C may be a second external voltage (VSOD). The first driving voltage V_A may be equal to or higher than the voltage level of the second driving voltage V_B. The third driving voltage V_C may be equal to or higher than the voltage level of the first driving voltage V_A. The third driving voltage V_C may be higher than the voltage level of the second driving voltage V_B.

[0016] The driving voltage supply circuit 100 may include a control signal generation circuit 110 , a voltage selection signal generation circuit 120 , and a voltage supply circuit 130 .

[0017] The control signal generating circuit 110 may generate a first sense amplifier driving control signal SAP1, a second sense amplifier driving control signal SAP2, and a third sense amplifier driving control signal SAN in response to the activation signal ACT. For example, if the activation signal ACT is enabled, the control signal generating circuit 110 enables the first sense amplifier driving control signal SAP1 at a first predetermined time, and when the first sense amplifier driving control signal SAP1 is disabled, the control signal generating circuit 110 enables the second sense amplifier driving control signal SAP2 at a second predetermined time. The control signal generating circuit 110 enables the third sense amplifier driving control signal SAN during a period in which at least one of the first sense amplifier driving control signal SAP1 and the second sense amplifier driving control signal SAP2 is enabled. That is, the control signal generating circuit 110 enables the third sense amplifier driving control signal SAN in a time obtained by adding the first predetermined time and the second predetermined time.

[0018] The voltage selection signal generating circuit 120 may output the second sense amplifier driving control signal SAP2 as one of the first voltage selection signal V_sel1 and the second voltage selection signal V_sel2 in response to the cell feature information signal C_inf. For example, when the cell feature information signal C_inf is enabled, the voltage selection signal generating circuit 120 may output the second sense amplifier driving control signal SAP2 as the first voltage selection signal V_sel1, and when the cell feature information signal C_inf is disabled, the voltage selection signal generating circuit 120 may output the second sense amplifier driving control signal SAP2 as the second voltage selection signal V_sel2. The voltage selection signal generating circuit 120 may include a multiplexer.

[0019] The voltage supply circuit 130 may selectively supply at least one of the first to third driving voltages V_A, V_B and V_C, the ground voltage VSS and the precharge voltage V_pcg to at least one of the first driving line RTO and the second driving line SB in response to at least one of the first and third sense amplifier driving control signals SAP1 and SAN, the first and second voltage selection signals V_sel1 and V_sel2 and the precharge signal PCG. For example, during the activation of the first sense amplifier driving control signal SAP1, the voltage supply circuit 130 may supply the first driving voltage V_A to the first driving line RTO. The voltage supply circuit 130 may apply the ground voltage VSS and the precharge voltage V_pcg to the second driving line SB in response to the third sense amplifier driving control signal SAN and the precharge signal PCG. During the activation of the first voltage selection signal V_sel1, the voltage supply circuit 130 may supply the second driving voltage V_B to the first driving line RTO. During the activation of the second voltage selection signal V_sel2, the voltage supply circuit 130 may supply the third driving voltage V_C to the first driving line RTO. During the activation of the precharge signal PCG, the voltage supply circuit 130 may supply the precharge voltage V_pcg to the first driving line RTO and the second driving line SB.

[0020] The cell characteristic information storage circuit 200 may store and provide information according to the characteristics of the memory cell as a cell characteristic information signal C_inf. The cell characteristic information storage circuit 200 may include a fuse circuit that determines whether to cut the fuse according to the characteristics of the memory cell and generates the cell characteristic information signal C_inf according to whether the fuse is cut. The cell characteristic information storage circuit 200 may include a register circuit that stores information according to the characteristics of the memory cell as the cell characteristic information signal C_inf. The characteristics of the memory cell may indicate whether the time for which the memory cell can retain data is longer than a reference time or shorter than a reference time. For example, when the data retention time of the memory cell is longer than the reference time, the cell characteristic information storage circuit 200 is configured to enable the cell characteristic information signal C_inf. When the data retention time of the memory cell is shorter than the reference time, the cell characteristic information storage circuit 200 is configured to disable the cell characteristic information signal C_inf.

[0021] The precharge voltage generating circuit 300 may select a voltage level of the precharge voltage V_pcg in response to the cell feature information signal C_inf. For example, when the cell feature information signal C_inf is disabled, the precharge voltage generating circuit 300 may generate a precharge voltage V_pcg having a higher voltage level than when the cell feature information signal C_inf is enabled. Therefore, when the cell feature information signal C_inf is enabled, the precharge voltage generating circuit 300 may generate a precharge voltage V_pcg having a lower voltage level than when the cell feature information signal C_inf is disabled.

[0022] The sense amplifier 400 may operate by being supplied with a voltage transmitted from the first driving line RTO and the second driving line SB.

[0023] like Figure 2 As shown, the voltage supply circuit 130 may include a first voltage applying circuit 131 , a second voltage applying circuit 132 , a third voltage applying circuit 133 , a fourth voltage applying circuit 134 and a pre-charge voltage applying circuit 135 .

[0024] When the first sense amplifier driving control signal SAP1 is enabled, the first voltage applying circuit 131 may apply the first driving voltage V_A to the first driving line RTO.

[0025] The first voltage applying circuit 131 may include a first transistor N1. The first transistor N1 has a gate to which the first sense amplifier driving control signal SAP1 is input, a drain to which the first driving voltage V_A is applied, and a source coupled to the first driving line RTO.

[0026] When the first voltage selection signal V_sel1 is enabled, the second voltage applying circuit 132 may apply the second driving voltage V_B to the first driving line RTO.

[0027] The second voltage applying circuit 132 may include a second transistor N2. The second transistor N2 has a gate to which the first voltage selection signal V_sel1 is input, a drain to which the second driving voltage V_B is applied, and a source coupled to the first driving line RTO.

[0028] When the second voltage selection signal V_sel2 is enabled, the third voltage applying circuit 133 may apply the third driving voltage V_C to the first driving line RTO.

[0029] The third voltage applying circuit 133 may include a third transistor N3. The third transistor N3 has a gate to which the second voltage selection signal V_sel2 is input, a drain to which the third driving voltage V_C is applied, and a source coupled to the first driving line RTO.

[0030] When the third sense amplifier driving control signal SAN is enabled, the fourth voltage applying circuit 134 may apply the ground voltage VSS to the second driving line SB.

[0031] The fourth voltage applying circuit 134 may include a fourth transistor N4. The fourth transistor N4 has a gate to which the third sense amplifier driving control signal SAN is input, a drain coupled to the second driving line SB, and a source to which the ground voltage VSS is applied.

[0032] When the precharge signal PCG is enabled, the precharge voltage applying circuit 135 may couple the first driving line RTO and the second driving line SB and apply the precharge voltage V_pcg to the first driving line RTO and the second driving line SB.

[0033] The precharge voltage applying circuit 135 may include fifth to seventh transistors N5, N6 and N7. The fifth transistor N5 has a gate to which the precharge signal PCG is input, a drain coupled to the first driving line RTO, and a source coupled to the second driving line SB. The sixth transistor N6 has a gate to which the precharge signal PCG is input, a drain to which the precharge voltage V_pcg is applied, and a source coupled to the first driving line RTO. The seventh transistor N7 has a gate to which the precharge signal PCG is input, a drain to which the precharge voltage V_pcg is applied, and a source coupled to the second driving line SB.

[0034] like Figure 3 As shown, the pre-charge voltage generating circuit 300 may include a first pre-charge voltage generating circuit 310 , a second pre-charge voltage generating circuit 320 and a voltage selection output circuit 330 .

[0035] The first pre-charge voltage generating circuit 310 may generate a first pre-charge voltage V_pcgp1 having a voltage level lower than that of the second driving voltage V_B. For example, the first pre-charge voltage generating circuit 310 may generate a first pre-charge voltage V_pcgp1 having a voltage level corresponding to 1 / 2 of that of the second driving voltage V_B.

[0036] The first pre-precharge voltage generating circuit 310 may include a first reference voltage generating circuit 311 and a first pre-voltage generating circuit 312 .

[0037] The first reference voltage generating circuit 311 may generate a first reference voltage V_ref1 having a voltage level lower than that of the second driving voltage V_B. For example, the first reference voltage generating circuit 311 may generate a first reference voltage V_ref1 having a voltage level corresponding to ½ of that of the second driving voltage V_B.

[0038] The first reference voltage generating circuit 311 may include a first resistance element R1 and a second resistance element R2. One end of the first resistance element R1 is applied with a second driving voltage V_B. One end of the second resistance element R2 is connected to the other end of the first resistance element R1, and the other end of the second resistance element R2 is connected to a terminal of a ground voltage VSS. The first reference voltage V_ref1 is output from a node connected to the first resistance element R1 and the second resistance element R2. The resistance levels of the first resistance element R1 and the second resistance element R2 may be the same.

[0039] The first pre-voltage generating circuit 312 may generate a first pre-charge voltage V_pcgp1 corresponding to a voltage level of the first reference voltage V_ref1. For example, the first pre-voltage generating circuit 312 may generate a first pre-charge voltage V_pcgp1 having the same voltage level as the first reference voltage V_ref1.

[0040] The second pre-charge voltage generating circuit 320 may generate a second pre-charge voltage V_pcgp2 having a voltage level lower than that of the third driving voltage V_C. For example, the second pre-charge voltage generating circuit 320 may generate a second pre-charge voltage V_pcgp2 having a voltage level corresponding to 1 / 2 of the voltage level of the third driving voltage V_C.

[0041] The second pre-charge voltage generating circuit 320 may include a second reference voltage generating circuit 321 and a second pre-voltage generating circuit 322 .

[0042] The second reference voltage generating circuit 321 may generate a second reference voltage V_ref2 having a voltage level lower than that of the third driving voltage V_C. For example, the second reference voltage generating circuit 321 may generate a second reference voltage V_ref2 having a voltage level corresponding to 1 / 2 of the voltage level of the third driving voltage V_C.

[0043] The second reference voltage generating circuit 321 may include a third resistance element R3 and a fourth resistance element R4. One end of the third resistance element R3 is applied with a third driving voltage V_C. One end of the fourth resistance element R4 is connected to the other end of the third resistance element R3, and the other end of the fourth resistance element R4 is connected to a terminal of a ground voltage VSS. The second reference voltage V_ref2 is output from a node connected to the third resistance element R3 and the fourth resistance element R4. The resistance levels of the third resistance element R3 and the fourth resistance element R4 may be the same.

[0044] The second pre-voltage generating circuit 322 may generate a second pre-charge voltage V_pcgp2 corresponding to a voltage level of the second reference voltage V_ref2. For example, the second pre-voltage generating circuit 322 may generate a second pre-charge voltage V_pcgp2 having the same voltage level as the second reference voltage V_ref2.

[0045] The voltage selection output circuit 330 may output one of the first pre-precharge voltage V_pcgp1 and the second pre-precharge voltage V_pcgp2 as the pre-charge voltage V_pcg in response to the cell characteristic information signal C_inf. For example, when the cell characteristic information signal C_inf is enabled, the voltage selection output circuit 330 may output the first pre-precharge voltage V_pcgp1 as the pre-charge voltage V_pcg. When the cell characteristic information signal C_inf is disabled, the voltage selection output circuit 330 may output the second pre-precharge voltage V_pcgp2 as the pre-charge voltage V_pcg.

[0046] The operation of the semiconductor memory device configured as described above according to the embodiment will be described below.

[0047] If the memory cell is capable of retaining data for a time longer than a reference time, the cell characteristic information storage circuit 200 may provide an enabled cell characteristic information signal C_inf.

[0048] If the activation signal ACT is enabled, the control signal generation circuit 110 may enable the first sense amplifier drive control signal SAP1 at a first predetermined time, and when the first sense amplifier drive control signal SAP1 is disabled, the control signal generation circuit 110 may enable the second sense amplifier drive control signal SAP2 at a second predetermined time. The control signal generation circuit 110 may enable the third sense amplifier drive control signal SAN during a period in which one of the first sense amplifier drive control signal SAP1 and the second sense amplifier drive control signal SAP2 is enabled.

[0049] The voltage selection signal generating circuit 120 may output the second sense amplifier driving control signal SAP2 as the first voltage selection signal V_sel1 in response to the enabled cell characteristic information signal C_inf.

[0050] During the activation of the first sense amplifier driving control signal SAP1, the voltage supply circuit 130 may apply the first driving voltage V_A to the first driving line RTO. During the activation of the first voltage selection signal V_sel1, the voltage supply circuit 130 may apply the second driving voltage V_B to the first driving line RTO. During the activation of the third sense amplifier driving control signal SAN, the voltage supply circuit 130 may apply the ground voltage VSS to the second driving line SB. During the activation of the precharge signal PCG, the voltage supply circuit 130 may apply the precharge voltage V_pcg to the first driving line RTO and the second driving line SB.

[0051] The precharge voltage generating circuit 300 may provide the precharge voltage V_pcg having a lower voltage level to the voltage supply circuit 130 in response to the enabled cell characteristic information signal C_inf than when the cell characteristic information signal C_inf is disabled.

[0052] The sense amplifier 400 may operate by being applied with a voltage applied through the first driving line RTO and the second driving line SB.

[0053] If the memory cell is capable of retaining data for a time shorter than a reference time, the cell characteristic information storage circuit 200 may provide an disabled cell characteristic information signal C_inf.

[0054] If the activation signal ACT is enabled, the control signal generation circuit 110 may enable the first sense amplifier drive control signal SAP1 at a first predetermined time, and when the first sense amplifier drive control signal SAP1 is disabled, the control signal generation circuit 110 may enable the second sense amplifier drive control signal SAP2 at a second predetermined time. The control signal generation circuit 110 may enable the third sense amplifier drive control signal SAN during a period in which one of the first sense amplifier drive control signal SAP1 and the second sense amplifier drive control signal SAP2 is enabled.

[0055] The voltage selection signal generating circuit 120 may output the second sense amplifier driving control signal SAP2 as the second voltage selection signal V_sel2 in response to the disabled cell characteristic information signal C_inf.

[0056] During the activation of the first sense amplifier driving control signal SAP1, the voltage supply circuit 130 may apply the first driving voltage V_A to the first driving line RTO. During the activation of the second voltage selection signal V_sel2, the voltage supply circuit 130 may apply the third driving voltage V_C to the first driving line RTO. During the activation of the third sense amplifier driving control signal SAN, the voltage supply circuit 130 may apply the ground voltage VSS to the second driving line SB. During the activation of the precharge signal PCG, the voltage supply circuit 130 may apply the precharge voltage V_pcg to the first driving line RTO and the second driving line SB.

[0057] The precharge voltage generating circuit 300 may provide the precharge voltage V_pcg with a higher voltage level to the voltage supply circuit 130 in response to the disabled cell characteristic information signal C_inf than when the cell characteristic information signal C_inf is enabled.

[0058] The sense amplifier 400 may operate by being applied with a voltage applied through the first driving line RTO and the second driving line SB.

[0059] The semiconductor memory device according to the embodiment may determine a voltage level to be provided to the sense amplifier 400 during the enabling of the second sense amplifier driving control signal SAP2 in response to the cell feature information signal C_inf. That is, because the second driving voltage V_B is lower in voltage level than the third driving voltage V_C, when the cell feature information signal C_inf is enabled, a voltage having a lower voltage level than when the cell feature information signal C_inf is disabled may be provided to the sense amplifier 400 through the first driving line RTO.

[0060] Therefore, when the memory cell is able to retain data for a time longer than the reference time during the period in which the second sense amplifier drive control signal SAP2 is enabled, the semiconductor memory device according to an embodiment can provide a voltage of a lower voltage level to the sense amplifier, compared to when the memory cell retains data for a time shorter than the reference time during the period in which the second sense amplifier drive control signal SAP2 is enabled.

[0061] A semiconductor memory device according to an embodiment may provide a voltage of a higher voltage level to the sense amplifier when the memory cell retains data for a time shorter than the reference time during the enable period of the second sense amplifier drive control signal SAP2, compared to when the memory cell retains data for a time longer than the reference time during the enable period of the second sense amplifier drive control signal SAP2.

[0062] like Figure 4As shown, the semiconductor memory device according to the embodiment may include first to third driving voltage supply circuits 100-1, 100-2 and 100-3, a cell characteristic information storage circuit 200-1, first to third precharge voltage generation circuits 300-1, 300-2 and 300-3, first to third sense amplifiers 400-1, 400-2 and 400-3, and first to third pads 500-1, 500-2 and 500-3. Each of the first to third driving voltage supply circuits 100-1, 100-2 and 100-3 may be connected to Figure 1 The driving voltage supply circuit 100 is configured in a substantially similar manner, and each of the first to third pre-charge voltage generating circuits 300-1, 300-2 and 300-3 can be connected to Figure 3 Configured in a substantially similar manner as shown.

[0063] The first pad 500 - 1 may be electrically coupled to the first sense amplifier 400 - 1 , the first sense amplifier 400 - 1 may be electrically coupled to the first driving voltage supply circuit 100 - 1 , and the first precharge voltage generating circuit 300 - 1 may be electrically coupled to the first driving voltage supply circuit 100 - 1 .

[0064] The second pad 500 - 2 may be electrically coupled to the second sense amplifier 400 - 2 , the second sense amplifier 400 - 2 may be electrically coupled to the second driving voltage supply circuit 100 - 2 , and the second precharge voltage generating circuit 300 - 2 may be electrically coupled to the second driving voltage supply circuit 100 - 2 .

[0065] The third pad 500 - 3 may be electrically coupled to the third sense amplifier 400 - 3 , the third sense amplifier 400 - 3 may be electrically coupled to the third driving voltage supply circuit 100 - 3 , and the third precharge voltage generating circuit 300 - 3 may be electrically coupled to the third driving voltage supply circuit 100 - 3 .

[0066] The cell characteristic information storage circuit 200-1 may store information about the characteristics of the memory cell included in the first pad 500-1 as a first cell characteristic information signal C_inf1. The cell characteristic information storage circuit 200-1 may store information about the characteristics of the memory cell included in the second pad 500-2 as a second cell characteristic information signal C_inf2. The cell characteristic information storage circuit 200-1 may store information about the characteristics of the memory cell included in the third pad 500-3 as a third cell characteristic information signal C_inf3. The cell characteristic information storage circuit 200-1 may provide the first cell characteristic information signal C_inf1 to the first driving voltage supply circuit 100-1 and the first precharge voltage generation circuit 300-1. The cell characteristic information storage circuit 200-1 may provide the second cell characteristic information signal C_inf2 to the second driving voltage supply circuit 100-2 and the second precharge voltage generation circuit 300-2. The cell characteristic information storage circuit 200 - 1 may provide the third cell characteristic information signal C_inf3 to the third driving voltage supply circuit 100 - 3 and the third precharge voltage generation circuit 300 - 3 .

[0067] For example, if the first to third unit characteristic information signals C_inf1, C_inf2 and C_inf3 have the same information, that is, have the same level, then the first to third driving voltage supply circuits 100-1, 100-2 and 100-3 can selectively provide the driving voltage of the same level to the first to third read-out amplifiers 400-1, 400-2 and 400-3 through the driving lines RTO1, SB1, RTO2, SB2, RTO3 and SB3, and the first to third pre-charge voltage generating circuits 300-1, 300-2, 300-3 can provide the pre-charge voltage of the same level to the first to third read-out amplifiers 400-1, 400-2 and 400-3 through the driving lines RTO1, SB1, RTO2, SB2, RTO3 and SB3. Further, when the corresponding cell characteristic information signal is enabled, each of the respective first to third driving voltage supply circuits 100 - 1 , 100 - 2 , and 100 - 3 may supply a driving voltage of a lower level than when the corresponding cell characteristic information signal is disabled.

[0068] If there is a signal including different information in the first to third cell characteristic information signals C_inf1, C_inf2, and C_inf3, that is, there is a signal having a level different from other signals, the driving voltage supply circuit and the precharge voltage generation circuit to which the cell characteristic information signals of different levels are input provide driving voltages and precharge voltages of different levels from other driving voltage supply circuits and other precharge voltage generation circuits to the corresponding sense amplifiers. The first to third precharge voltage generation circuits 300-1, 300-2, and 300-3 may determine a voltage level in response to the respective cell characteristic information signals C_inf1, C_inf2, and C_inf3, and output the precharge voltages of the determined voltage levels to the driving voltage supply circuits 100-1, 100-2, and 100-3, respectively. Further, when at least one of the corresponding cell feature information signals C_inf1, C_inf2 and C_inf3 is enabled, each of the first to third precharge voltage generating circuits 300-1, 300-2 and 300-3 may generate a precharge voltage having a voltage level lower than when the corresponding cell feature information signals C_inf1, C_inf2 and C_inf3 are disabled.

[0069] Therefore, the cell characteristic information storage circuit 200-1 may transmit voltages of different voltage levels according to characteristics of memory cells included in the first to third pads 500-1, 500-2, and 500-3 to the respective sense amplifiers 400-1, 400-2, and 400-3.

[0070] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are only examples. Therefore, the semiconductor memory device described herein should not be limited based on the described embodiments.

[0071] The semiconductor memory device (see Figure 1-4 ) is particularly useful in the design of memory devices, processors, and computer systems. For example, see Figure 5 , a block diagram of a system employing a semiconductor memory device according to various embodiments is shown and generally indicated by the reference numeral 1000. The system 1000 may include one or more processors (i.e., processors) or, for example but not limited to, a central processing unit ("CPU") 1100. The processor (i.e., CPU) 1100 may be used alone or in combination with other processors (i.e., CPUs). Although the processor (i.e., CPU) 1100 will be primarily indicated in the singular, it will be understood by those skilled in the art that the system 1000 may be implemented with any number of physical or logical processors (i.e., CPUs).

[0072] Chipset 1150 may be operably coupled to processor (i.e., CPU) 1100. Chipset 1150 is a communication path for signals between processor (i.e., CPU) 1100 and other components of system 1000. Other components of system 1000 may include memory controller 1200, input / output (“I / O”) bus 1250, and disk drive controller 1300. Depending on the configuration of system 1000, any of a number of different signals may be transmitted through chipset 1150, and those skilled in the art will appreciate that the routing of signals throughout system 1000 may be easily adjusted without changing the basic features of system 1000.

[0073] As described above, the memory controller 1200 may be operably coupled to the chipset 1150. The memory controller 1200 may include at least one Figure 1-4 The semiconductor memory device discussed. Therefore, the memory controller 1200 can receive a request provided from the processor (i.e., CPU) 1100 through the chipset 1150. In an alternative embodiment, the memory controller 1200 can be integrated into the chipset 1150. The memory controller 1200 can be operably connected to one or more memory devices 1350. In an embodiment, the memory device 1350 may include at least one or more memory devices 1350. Figure 1-4 As discussed above, the memory device 1350 may include a plurality of word lines and a plurality of bit lines for defining a plurality of memory cells. The memory device 1350 may be any of a number of industry standard memory types, including but not limited to a single in-line memory module (“SIMM”) and a dual in-line memory module (“DIMM”). In addition, the memory device 1350 may facilitate the safe removal of an external data storage device by storing both instructions and data.

[0074] Chipset 1150 may also be coupled to an I / O bus 1250. I / O bus 1250 may serve as a communication path for signals from chipset 1150 to I / O devices 1410, 1420, and 1430. I / O devices 1410, 1420, and 1430 may include, for example, but not limited to, a mouse 1410, a video display 1420, or a keyboard 1430. I / O bus 1250 may employ any of a number of communication protocols to communicate with I / O devices 1410, 1420, and 1430. In an embodiment, I / O bus 1250 may be integrated into chipset 1150.

[0075] The disk drive controller 1300 may be operably coupled to the chipset 1150. The disk drive controller 1300 may serve as a communication path between the chipset 1150 and an internal disk drive 1450 or multiple internal disk drives 1450. The internal disk drive 1450 may facilitate disconnection of external data storage devices by storing both instructions and data. The disk drive controller 1300 and the internal disk drives 1450 may communicate with each other or with the chipset 1150 using virtually any type of communication protocol, such as, but not limited to, all of the protocols mentioned above for the I / O bus 1250.

[0076] It is important to note that the above Figure 5 The system 1000 described above is only used as described above Figure 1-4 An example of a system 1000 of semiconductor memory devices is discussed. In alternative embodiments, such as but not limited to a cellular phone or a digital camera, the components may be different from Figure 5 The embodiment shown.

Claims

1. A semiconductor memory device, comprising: Multiple pads; a plurality of sense amplifiers electrically connected to the plurality of pads, respectively; as well as a plurality of driving voltage supply circuits adapted to selectively supply driving voltages to the plurality of sense amplifiers in response to a plurality of cell characteristic information signals, respectively; Wherein, each of the plurality of unit characteristic information signals defines whether a data retention time of a corresponding pad among the plurality of pads is longer than a reference time.

2. The semiconductor memory device according to claim 1 , wherein among the driving voltages, a voltage level of a driving voltage provided by each of the plurality of driving voltage providing circuits when a corresponding cell characteristic information signal is enabled is lower than a voltage level of a driving voltage provided when the corresponding cell characteristic information signal is disabled.

3. The semiconductor memory device according to claim 2, wherein each of the cell characteristic information signals includes information according to characteristics of the memory cells of each of the pads.

4. The semiconductor memory device according to claim 3, further comprising: The cell characteristic information storage circuit is adapted to provide the plurality of cell characteristic information signals.

5. The semiconductor memory device according to claim 1, further comprising: A plurality of pre-charge voltage generating circuits are adapted to determine voltage levels in response to the plurality of cell characteristic information signals, respectively, and output pre-charge voltages of the determined voltage levels to the driving voltage supply circuits, respectively.

6. A semiconductor memory device according to claim 5, wherein the voltage level of the pre-charge voltage generated by each of the multiple pre-charge voltage generating circuits when the corresponding cell characteristic information signal is enabled is lower than the voltage level of the pre-charge voltage generated when the corresponding cell characteristic information signal is disabled.

7. The semiconductor memory device according to claim 1, if the plurality of cell characteristic information signals have the same level, the plurality of driving voltage supply circuits are configured to supply driving voltages having the same level to the plurality of sense amplifiers.

8. A semiconductor memory device according to claim 7, wherein if the plurality of cell characteristic information signals have the same level, the plurality of precharge voltage generating circuits are configured to respectively provide the precharge voltages having the same level to the plurality of read-out amplifiers through a plurality of driving lines.

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