Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a plurality of discrete nanostructures on the substrate, with grooves between adjacent nanostructures; forming a first dielectric layer and an initial isolation structure on the substrate, wherein the top surface of the first dielectric layer is lower than the top surface of the nanostructures and the first dielectric layer is located on the sidewall surface of the initial isolation structure, and the initial isolation structure is located within at least one of the grooves; and etching the initial isolation structure exposed by the first dielectric layer to form an isolation structure. The semiconductor structure formed by this method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component or line that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] In some IC designs, as technology nodes shrink, one advantage realized is replacing the typical polysilicon gate with a metal gate to improve device performance as feature sizes shrink. One process for forming the metal gate is called a replacement gate or "gate-last" process, in which the metal gate is manufactured "last," which allows for a reduction in the number of subsequent processes, including high-temperature processing that must be performed after the gate is formed.

[0004] However, implementing these IC manufacturing processes also presents a series of challenges, especially for scaled-down IC components in advanced process nodes, such as N10, N5, etc. One challenge is how to effectively isolate the metal gate after replacement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of discrete nanostructures on the substrate, with grooves between adjacent nanostructures; forming a first dielectric layer and an initial isolation structure on the substrate, wherein the top surface of the first dielectric layer is lower than the top surface of the nanostructure, and the first dielectric layer is located on the sidewall surface of the initial isolation structure, and the initial isolation structure is located in at least one of the grooves; and etching the initial isolation structure exposed by the first dielectric layer to form an isolation structure.

[0007] Optionally, the method for forming the initial isolation structure and the first dielectric layer includes: forming an initial first dielectric layer on a substrate, the initial first dielectric layer being located in the groove; forming a patterned mask structure on the initial first dielectric layer, the mask structure exposing a portion of the surface of the initial first dielectric layer in the groove; etching the initial first dielectric layer using the mask structure as a mask until the substrate surface is exposed, thereby forming an isolation opening in the initial first dielectric layer; forming the initial isolation structure in the isolation opening; after forming the initial isolation structure, etching back the initial first dielectric layer to form a first dielectric layer, the first dielectric layer exposing a portion of the initial isolation structure, and the top surface of the first dielectric layer is lower than the top surface of the nanostructure.

[0008] Optionally, the initial isolation structure has a first size in the arrangement direction of the nanostructures, and the isolation structure has a second size in the arrangement direction of the nanostructures, and the second size is smaller than the first size.

[0009] Optionally, the first size ranges from greater than 10 nanometers; and the second size ranges from 1 nanometer to 5 nanometers.

[0010] Optionally, the process of etching the initial isolation structure includes an isotropic dry etching process or an isotropic wet etching process.

[0011] Optionally, the etching gas of the isotropic dry etching process includes: carbon tetrafluoride and argon, or carbon tetrafluoride and helium.

[0012] Optionally, the nanostructure includes: a first region, a second region located on the first region, and a third region located on the second region; the first region includes a bottom layer of nanowires, the first dielectric layer is located on the sidewall of the first region and the first dielectric layer is lower than the bottom plane of the second region; the second region includes several composite layers, the composite layers include a sacrificial layer and nanowires located on the sacrificial layer; the third region includes a top sacrificial layer.

[0013] Optionally, the thickness of the top sacrificial layer is greater than the thickness of the sacrificial layer; the thickness of the top sacrificial layer is greater than the thickness of the sacrificial layer by 3 nanometers to 10 nanometers.

[0014] Optionally, after forming the isolation structure, the method further includes: forming a gate structure on the substrate, wherein the gate structure spans the nanostructure, and the isolation structure isolates adjacent gate structures.

[0015] Optionally, the material of the gate structure includes metal.

[0016] Optionally, the method for forming the gate structure includes: after forming the isolation structure, forming a dummy gate structure on the first dielectric layer, the dummy gate structure spanning the nanostructure and the isolation structure; forming a second dielectric layer on the sidewall of the dummy gate structure; removing the dummy gate structure to form a first opening in the second dielectric layer; removing the sacrificial layer and the top sacrificial layer exposed by the first opening to form a second opening between adjacent nanowires and between bottom nanowires and nanowires; and forming a gate structure in the first opening and in the second opening.

[0017] Optionally, the method for forming the gate structure includes: before forming the isolation structure, forming a dummy gate structure on the first dielectric layer, the dummy gate structure spanning the nanostructure and the initial isolation structure; forming a second dielectric layer on the sidewall of the dummy gate structure; removing the dummy gate structure, and forming a first opening in the second dielectric layer, the first opening exposing the initial isolation structure.

[0018] Optionally, the method for forming the gate structure includes: after forming the isolation structure, removing the sacrificial layer and the top sacrificial layer exposed by the first opening, forming a second opening between adjacent nanowires and between bottom nanowires and nanowires; and forming a gate structure within the first opening and the second opening.

[0019] Optionally, the material of the initial first dielectric layer and the material of the initial isolation structure have different etching rates.

[0020] Optionally, the material of the initial first dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

[0021] Optionally, the material of the initial isolation structure includes a dielectric material, and the dielectric material includes silicon nitride.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] The semiconductor structure formation method of the present invention first forms a relatively large initial isolation structure, and then etches the initial isolation structure to form an isolation structure. The isolation structure formed by this method is relatively small in size, breaking through the limitations of photolithography. On the one hand, it can obtain a smaller isolation structure to meet the needs of semiconductor structures. On the other hand, the isolation structure has high dimensional accuracy. The position of the isolation structure can be adjusted so that it can be located between adjacent nanostructures, thereby ensuring that the gate structure formed subsequently has better dimensional uniformity and more uniform performance.

[0024] Furthermore, the thickness of the top sacrificial layer is greater than that of the sacrificial layer. Thus, after the gate structure is subsequently formed, the height of the isolation structure can be higher than the height of the nanostructure, ensuring that the isolation structure effectively isolates adjacent gate structures. This prevents the isolation structure from being lost during the gate structure formation process, which could cause a short circuit between adjacent gate structures if the height of the isolation structure is lower than the height of the nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure in one embodiment;

[0026] Figures 2 to 7 is a schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present invention;

[0027] Figure 8 and Figure 9 It is a schematic cross-sectional structural diagram of a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, the current metal gate manufacturing process still faces many challenges, which will now be analyzed and explained in conjunction with specific embodiments.

[0029] Figure 1 FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor structure in one embodiment.

[0030] Please refer to Figure 1 , comprising: a substrate 100; a first nanostructure located on the substrate 100, the first nanostructure comprising a plurality of stacked first nanowires 101; a second nanostructure located on the substrate 100, the second nanostructure comprising a plurality of stacked second nanowires 102, the first nanostructure and the second nanostructure being adjacent to each other; a dielectric layer 103 located on the substrate 100, the dielectric layer 103 being located on sidewalls of the first nanostructure and sidewalls of the second nanostructure; a first gate structure 104 located on the substrate, the first gate structure 104 surrounding the first nanostructure and being located between the first nanowires 101; a second gate structure 105 located on the substrate, the second gate structure 105 surrounding the second nanostructure and being located between the second nanowires 102; and an isolation structure 106 located between the first nanostructure and the second nanostructure.

[0031] In the semiconductor structure, the isolation structure 106 is used to electrically isolate the first gate structure 104 from the second gate structure 105. The isolation structure 106 can be formed before or after the gate-last process. Due to the small size of the semiconductor structure, a smaller isolation structure 106 is required. However, due to the limitations of photolithography, existing photolithography technology cannot form the required small-sized isolation structure 106 pattern. As a result, the resulting isolation structure 106 is relatively large and cannot meet device requirements.

[0032] Furthermore, the position of the isolation structure 106 formed by the existing photolithography technology is prone to displacement, which makes the size uniformity of the first gate structure 104 and the second gate structure 105 formed poor, and also causes the problem of uneven pressure, thereby making the first gate structure 104 and the second gate structure 105 have different electrical properties, affecting the performance of the semiconductor structure.

[0033] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure by first forming a relatively large initial isolation structure and then etching the initial isolation structure to form an isolation structure. This method results in a smaller isolation structure, thus overcoming the limitations of photolithography and enabling the production of smaller isolation structures to meet the needs of semiconductor structures.

[0034] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 7 Schematic diagram of the cross-sectional structure of the semiconductor structure in an embodiment of the present invention.

[0036] Please refer to Figure 2 , providing a substrate 200.

[0037] In this embodiment, the substrate 200 is made of silicon.

[0038] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0039] Please continue to refer to Figure 2 , a plurality of discrete nanostructures are formed on the substrate 200 , with grooves 205 between adjacent nanostructures.

[0040] The nanostructure includes: a first region, a second region located on the first region, and a third region located on the second region; the first region includes a bottom layer of nanowires 201, the second region includes several composite layers, the composite layers include a sacrificial layer 202 and nanowires 203 located on the sacrificial layer 202; the third region includes a top layer of sacrificial layer 204.

[0041] The method for forming the nanostructure and groove 205 includes: forming a nanostructure material layer on the substrate 200, the nanostructure material layer including a bottom fin material layer (not shown), a plurality of composite structures located on the bottom fin material layer, the composite structures including a sacrificial material layer (not shown) and a fin material layer (not shown) located on the sacrificial material layer, and a top sacrificial material layer (not shown) located on the composite structure; forming a patterned mask layer (not shown) on the nanostructure material layer; etching the nanostructure material layer using the patterned mask layer as a mask to form the nanostructure and groove 205 on the substrate 200.

[0042] The bottom fin material layer provides a material layer for forming the bottom nanowire 201; the fin material layer provides a material layer for forming the nanowire 203; the sacrificial material layer provides a material layer for forming the sacrificial layer 202; and the top sacrificial material layer provides a material layer for forming the top sacrificial layer 204. The bottom fin material layer and the fin material layer are made of silicon or silicon germanium; and the sacrificial material layer and the top sacrificial material layer are made of silicon or silicon germanium.

[0043] In this embodiment, the bottom fin material layer and the fin material layer are made of silicon, and the sacrificial material layer and the top sacrificial material layer are made of silicon germanium. Silicon germanium and silicon have a large etching selectivity, so that when the sacrificial layer 202 and the top sacrificial layer 204 are subsequently removed, the removal process causes minimal damage to the bottom nanowires 201 and the nanowires 203.

[0044] In this embodiment, the thickness of the top sacrificial layer 204 is greater than that of the sacrificial layer 202. Therefore, after the gate structure is subsequently formed, the height of the isolation structure formed can be higher than the height of the nanostructure, ensuring that the isolation structure effectively isolates adjacent gate structures. This prevents the isolation structure from being lost during the gate structure formation process, which could result in a short circuit between adjacent gate structures if the isolation structure's height is lower than the height of the nanostructure.

[0045] In this embodiment, the thickness of the top sacrificial layer 204 is greater than the thickness of the sacrificial layer 202 and is in the range of 3 nanometers to 10 nanometers.

[0046] In other embodiments, the thickness of the top sacrificial layer is the same as the thickness of the sacrificial layer.

[0047] Next, a first dielectric layer and an initial isolation structure are formed on the substrate 200. The top surface of the first dielectric layer is lower than the top surface of the nanostructure, and the first dielectric layer is located on the sidewall surface of the initial isolation structure. The initial isolation structure is located in at least one of the grooves. The formation process of the first dielectric layer and the initial isolation structure can be found in Figure 3 and Figure 4 .

[0048] Please refer to Figure 3 , an initial first dielectric layer 206 is formed on the substrate 200 , and the initial first dielectric layer 206 is located in the groove 205 ; an initial isolation structure 207 is formed in the initial first dielectric layer 206 .

[0049] The method for forming the initial first dielectric layer 206 includes: forming a dielectric material layer (not shown) on the substrate 200 and in the groove 205 ; and planarizing the dielectric material layer until the top surface of the nanostructure is exposed to form the initial first dielectric layer 206 .

[0050] The material of the initial first dielectric layer 206 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the initial first dielectric layer 206 includes silicon oxide.

[0051] The method for forming the initial isolation structure 207 includes: forming a patterned mask structure (not shown) on the initial first dielectric layer 206, wherein the mask structure exposes a portion of the surface of the initial first dielectric layer 206 within the groove 205; etching the initial first dielectric layer 206 using the mask structure as a mask until the surface of the substrate 200 is exposed, thereby forming an isolation opening (not shown) in the initial first dielectric layer 206; forming an isolation material layer (not shown) in the isolation opening and on the initial first dielectric layer 206; and planarizing the isolation material layer until the surface of the initial first dielectric layer 206 is exposed, thereby forming the initial isolation structure 207.

[0052] The material of the initial isolation structure 207 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the initial isolation structure 207 includes silicon nitride.

[0053] The initial isolation structure 207 is used to subsequently form an isolation structure, and the isolation structure is used to isolate adjacent gate structures that are subsequently formed.

[0054] The initial isolation structure 207 has a first size in the arrangement direction of the nanostructures.

[0055] In this embodiment, the first dimension is larger than 10 nanometers.

[0056] Please refer to Figure 4 After forming the initial isolation structure 207, the initial first dielectric layer 206 is etched back to form a first dielectric layer 208, wherein the first dielectric layer 208 exposes a portion of the initial isolation structure 207, and the top surface of the first dielectric layer 208 is lower than the top surface of the nanostructure.

[0057] In this embodiment, the first dielectric layer 208 is located on the sidewalls of the first region and is lower than the bottom plane of the second region. That is, the first dielectric layer 208 is located on the sidewalls of the bottom nanowires 201 and is lower than the bottom plane of the sacrificial layer 202 at the bottom of the second region. Therefore, when the sacrificial layer 202 and the top sacrificial layer 204 are subsequently removed, the first dielectric layer 208 will not hinder the removal process.

[0058] The etching rate of the initial isolation structure 207 material in the process of etching back the initial first dielectric layer 206 is lower than the etching rate of the initial first dielectric layer 206. Therefore, the process of etching back the initial first dielectric layer 206 to form the first dielectric layer 208 has a larger etching selectivity ratio for the initial isolation structure 207, thereby causing less damage to the initial isolation structure 207.

[0059] Please refer to Figure 5 , the initial isolation structure 207 exposed by the first dielectric layer 208 is etched to form an isolation structure 209 .

[0060] The isolation structure 209 has a second size in the arrangement direction of the nanostructures, and the second size is smaller than the first size.

[0061] In this embodiment, the second size ranges from 1 nanometer to 5 nanometers.

[0062] The process of etching the initial isolation structure 207 includes an isotropic dry etching process or an isotropic wet etching process.

[0063] In this embodiment, the process of etching the initial isolation structure 207 includes an isotropic dry etching process, and the etching gas of the isotropic dry etching process includes: carbon tetrafluoride and argon, or carbon tetrafluoride and helium.

[0064] The etching rate of the first dielectric layer 208 during the process of etching the initial isolation structure 207 is lower than the etching rate of the material of the initial isolation structure 207 . Therefore, the damage to the first dielectric layer 208 during the process of etching the initial isolation structure 207 is relatively small.

[0065] Thus, the isolation structure 209 is formed by first forming a larger initial isolation structure 207 and then etching the initial isolation structure 207 to form the isolation structure 209. The isolation structure 209 formed by this method is smaller in size, which can break through the limitations of photolithography. On the one hand, it can obtain a smaller isolation structure 209 to meet the requirements of semiconductor structures; on the other hand, the isolation structure 209 formed has high dimensional accuracy. At the same time, the position of the isolation structure 209 can be adjusted so that the isolation structure 209 can be located between adjacent nanostructures, thereby ensuring that the gate structure formed later has better dimensional uniformity and more uniform performance.

[0066] Next, after forming the isolation structure 209, the process further includes forming a gate structure on the substrate 200, wherein the gate structure spans the nanostructure, and the isolation structure 209 isolates adjacent gate structures. Figure 6 and Figure 7 .

[0067] In this embodiment, the gate structure is a metal gate.

[0068] In other embodiments, the gate structure may be made of polysilicon.

[0069] Please refer to Figure 6 A dummy gate structure 211 is formed on the first dielectric layer 208 , and the dummy gate structure 211 spans the nanostructure and the isolation structure 209 ; a second dielectric layer 212 is formed on the sidewall of the dummy gate structure.

[0070] The dummy gate structure 211 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not labeled) located on the dummy gate dielectric layer.

[0071] The material of the dummy gate dielectric layer includes silicon oxide or a low-K (K less than 3.9) material; the material of the dummy gate layer includes polysilicon.

[0072] The material of the second dielectric layer 212 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the second dielectric layer 212 includes silicon oxide.

[0073] Please refer to Figure 7, remove the dummy gate structure 211, and form a first opening (not shown) in the second dielectric layer 212; remove the sacrificial layer 202 and the top sacrificial layer 204 exposed by the first opening, and form a second opening (not shown) between adjacent nanowires 203 and between the nanowire 203 and the bottom nanowire 201; and form a gate structure 213 in the first opening and the second opening.

[0074] The process of removing the dummy gate structure 211 includes a dry etching process and a wet etching process or a combination of one or more of the above.

[0075] The gate structure 213 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer. In this embodiment, the gate structure further includes a work function layer (not shown) located between the gate dielectric layer and the gate layer.

[0076] The material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0077] The method for forming a gate structure 213 in the first opening and the second opening includes: forming a gate structure material layer (not shown) in the first opening, in the second opening, on the nanostructure and on the isolation structure 209; and flattening the gate structure material layer until the top surface of the isolation structure 209 is exposed to form the gate structure 213.

[0078] Because the thickness of the top sacrificial layer 204 is greater than that of the sacrificial layer 202, the height of the isolation structure 209 formed after the gate structure 213 is formed can be higher than the height of the nanostructure, ensuring that the isolation structure 209 effectively isolates the adjacent gate structure 213. This prevents the isolation structure 209 from being lost significantly during the process of planarizing the gate structure material layer, which could cause a short circuit between adjacent gate structures 213 if the height of the isolation structure 209 is lower than the height of the nanostructure.

[0079] Figure 8 and Figure 9 It is a schematic cross-sectional structural diagram of a semiconductor structure in another embodiment of the present invention.

[0080] In this embodiment, after the dummy gate structure and the first opening are formed, the initial isolation structure 207 is etched to form an isolation structure.

[0081] Please refer to Figure 8 , Figure 8 For Figure 4 Based on the structural diagram, a dummy gate structure 311 is formed on the first dielectric layer 208 , and the dummy gate structure 311 spans the nanostructure and the initial isolation structure 207 ; a second dielectric layer 312 is formed on the sidewall of the dummy gate structure 311 .

[0082] The methods, processes and materials used in forming the dummy gate structure 311 and the second dielectric layer 311 are described in detail in the accompanying drawings. Figure 6 , I will not go into details here.

[0083] Please refer to Figure 9 , remove the dummy gate structure 311, form a first opening 313 in the second dielectric layer 312, and expose the initial isolation structure 207 by etching the first opening 313 to form an isolation structure 307.

[0084] The process of removing the dummy gate structure 311 includes a dry etching process and a wet etching process or a combination of one or more of the above.

[0085] For the process and steps of etching the initial isolation structure 207 to form the isolation structure 307, please refer to Figure 5 , I will not go into details here.

[0086] After forming the isolation structure 307, the following steps are further included: removing the sacrificial layer 202 and the top sacrificial layer 204 exposed by the first opening 313, forming second openings between adjacent nanowires 203 and between the nanowires 203 and the bottom nanowire 201; and forming a gate structure within the first opening and the second opening. For the steps, processes, and materials for removing the sacrificial layer 202 and the top sacrificial layer 204 and forming the gate structure, please refer to Figure 7 , I will not go into details here.

[0087] In other embodiments, after removing the sacrificial layer and the top sacrificial layer exposed by the first opening, the initial isolation structure may be etched to form an isolation structure. The isolation structure can be formed in different process steps, thus providing a high degree of process flexibility and compatibility with other processes, thereby improving production efficiency.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Forming a plurality of discrete nanostructures on a substrate, with grooves between adjacent nanostructures, the nanostructures comprising: a first region, a second region located on the first region, and a third region located on the second region, the first region comprising bottom nanowires, the second region comprising a plurality of composite layers, the composite layers comprising a sacrificial layer and nanowires located on the sacrificial layer; forming a first dielectric layer and an initial isolation structure on the substrate, wherein a top surface of the first dielectric layer is lower than a top surface of the nanostructure, the first dielectric layer is located on a sidewall surface of the initial isolation structure, and the initial isolation structure is located in at least one of the grooves; Etching the initial isolation structure exposed by the first dielectric layer to form an isolation structure; A gate structure is formed on the substrate, wherein the gate structure spans the nanostructures, and the isolation structure isolates adjacent gate structures. The gate structure is also located between adjacent nanowires and between a nanowire and an underlying nanowire.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the initial isolation structure and the first dielectric layer includes: forming an initial first dielectric layer on a substrate, wherein the initial first dielectric layer is located in the groove; forming a patterned mask structure on the initial first dielectric layer, wherein the mask structure exposes a portion of the surface of the initial first dielectric layer in the groove; etching the initial first dielectric layer using the mask structure as a mask until the substrate surface is exposed, thereby forming an isolation opening in the initial first dielectric layer; forming the initial isolation structure in the isolation opening; after forming the initial isolation structure, etching back the initial first dielectric layer to form a first dielectric layer, wherein the first dielectric layer exposes a portion of the initial isolation structure, and the top surface of the first dielectric layer is lower than the top surface of the nanostructure.

3. The method for forming a semiconductor structure according to claim 1, wherein: The initial isolation structure has a first size in the arrangement direction of the nanostructures, and the isolation structure has a second size in the arrangement direction of the nanostructures, where the second size is smaller than the first size.

4. The method for forming a semiconductor structure according to claim 3, wherein: The first size is greater than 10 nanometers; the second size is between 1 nanometer and 5 nanometers.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the initial isolation structure includes an isotropic dry etching process or an isotropic wet etching process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The etching gas of the isotropic dry etching process includes: carbon tetrafluoride and argon, or carbon tetrafluoride and helium.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first region includes bottom nanowires, the first dielectric layer is located on a sidewall of the first region and is lower than a bottom plane of the second region; and the third region includes a top sacrificial layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The thickness of the top sacrificial layer is greater than the thickness of the sacrificial layer; the thickness of the top sacrificial layer is greater than the thickness of the sacrificial layer by 3 nanometers to 10 nanometers.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate structure includes metal.

10. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the gate structure includes: after forming the isolation structure, forming a dummy gate structure on the first dielectric layer, the dummy gate structure spanning the nanostructure and the isolation structure; forming a second dielectric layer on the sidewall of the dummy gate structure; removing the dummy gate structure to form a first opening in the second dielectric layer; removing the sacrificial layer and the top sacrificial layer exposed by the first opening to form second openings between adjacent nanowires and between bottom nanowires and nanowires; and forming a gate structure within the first opening and the second opening.

11. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the gate structure includes: before forming the isolation structure, forming a dummy gate structure on a first dielectric layer, wherein the dummy gate structure spans the nanostructure and the initial isolation structure; forming a second dielectric layer on the sidewall of the dummy gate structure; removing the dummy gate structure and forming a first opening in the second dielectric layer, wherein the first opening exposes the initial isolation structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the gate structure includes: after forming the isolation structure, removing the sacrificial layer and the top sacrificial layer exposed by the first opening, forming a second opening between adjacent nanowires and between bottom nanowires and nanowires; and forming a gate structure in the first opening and the second opening.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial first dielectric layer and the material of the initial isolation structure have different etching rates.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the initial first dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

15. The method for forming a semiconductor structure according to claim 13, wherein: The material of the initial isolation structure includes a dielectric material, and the dielectric material includes silicon nitride.

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