Chip package structure and method

Abstract

The application provides a chip packaging structure, which comprises a substrate and a chip, wherein the substrate comprises a substrate body, a solder resist layer on the substrate body, and an etch-back filling structure on the substrate body and formed by an insulating material; the chip is fixed to the substrate and located on the solder resist layer and covers the etch-back filling structure. According to the technical scheme, the problem that the chip is delaminated after being bonded to the substrate due to the recess caused by etching back of the plating wire windowing and then the chip is failed is solved. In addition, the thickness of the substrate of the chip packaging structure is the same as that of the substrate etched back by a common plating line, and the raw material cost can be basically consistent with that of a conventional design substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to a chip packaging structure and method. Background Technology

[0002] High-density products typically use substrates as the carrier for packaging, and nickel-gold process is the mainstream technology for substrate surface treatment. It is suitable for substrates with fine-pitch gold-plated fingers on the front and gold-plated spherical pads on the back.

[0003] Surface treatment of high-density packaging substrates typically employs electroplating line etching-back technology. This process utilizes the principle of an electrolytic cell, using the area of ​​the substrate to be plated as the cathode to electroplat nickel and gold layers onto the substrate surface. Therefore, to perform nickel-gold plating on the substrate surface, the nickel-gold plating area must be connected to electroplating wires. These wires connect the nickel-gold plating area to the cathode of the rectifier, thus achieving nickel-gold plating. After electroplating, to prevent leakage or static electricity accumulation, a metal etching-back process is performed to remove these electroplating wires.

[0004] Because memory chips are relatively large, approaching the final package size, the etch-back windows can only be designed on the chip surface of the substrate, specifically below the chip. When bonding the substrate surface to the chip, a thin film such as a DAF (Die Attach Film) attached to the back of the chip is typically heated to secure the chip to the substrate. However, because the chip's film may not completely fill the recesses in the etch-back windows, the recess depth can reach or exceed 30µm. This can result in voids remaining at the bottom of the chip's film after the chip is bonded to the substrate. During subsequent assembly of the package with the motherboard, temperature changes can cause delamination between the chip and the substrate, leading to chip failure.

[0005] In related technologies, the above problems are solved by filling the etch-back depression area by, for example, recoating the solder resist material on the substrate surface. However, recoating the solder resist material can increase the board thickness and the corresponding cost of the solder resist material will also increase. Summary of the Invention

[0006] On one hand, embodiments of this application provide a chip packaging structure, which includes a substrate and a chip, wherein the substrate may include: a substrate body; a solder resist layer located on the substrate body; and an etch-back filling structure located on the substrate body and formed of an insulating material; the chip may be fixed to the substrate, and the chip may be located on the solder resist layer and cover the etch-back filling structure.

[0007] In one embodiment, the etch-back filling structure may have a circular cross-section, the diameter of which may be in the range of 100 μm to 500 μm.

[0008] In one embodiment, the chip packaging structure may further include a chip bonding film, through which the chip can be attached to the substrate.

[0009] In one embodiment, the etch-back filling structure can be distributed on the substrate body in a preset array pattern.

[0010] In one embodiment, the etch-back filling structure may have a recess on its surface away from the substrate body.

[0011] In one embodiment, the recess depth of the etch-back filling structure can be in the range of 1µm to 10µm.

[0012] In one embodiment, the substrate may include an organic substrate.

[0013] In one embodiment, the chip package structure may further include pads and bonding contacts, the surface material of which may include at least one of nickel and gold.

[0014] In one embodiment, the chip package structure may further include bonding wires for electrically connecting the chip to the bonding contacts.

[0015] In one embodiment, the chip may include a three-dimensional memory chip.

[0016] On the other hand, embodiments of this application provide a chip packaging method, which may include: forming a solder resist layer and an etch-back window on a substrate body of a substrate; filling the etch-back window with an insulating material to form an etch-back filling structure; and fixing a chip on the solder resist layer such that the chip covers the etch-back filling structure.

[0017] In one embodiment, the cross-section of the etch-back filling structure in a direction parallel to the surface of the substrate body can be a circular cross-section, and the diameter of the circular cross-section can be in the range of 100um to 500um.

[0018] In one embodiment, attaching the chip to the solder resist layer may include attaching the chip to the solder resist layer via a chip adhesive film.

[0019] In one embodiment, the step of forming the etch-back filling structure may include: forming the etch-back filling structure and distributing the etch-back filling structure on the substrate body in a preset array pattern.

[0020] In one embodiment, the step of forming the etch-back filling structure may further include: forming a recess in the etch-back filling structure on its surface away from the substrate body.

[0021] In one embodiment, the recess depth of the etch-back filling structure can be in the range of 1µm to 10µm.

[0022] In one embodiment, the substrate may include an organic substrate.

[0023] In one embodiment, the chip packaging method may further include: electroplating a metal layer on the pads and bonding contacts of the substrate, wherein the metal layer comprises at least one of nickel and gold.

[0024] In one embodiment, the chip packaging method may further include electrically connecting the chip to the bonding contacts via metal wires.

[0025] In one embodiment, the chip packaging method may further include: injection molding the substrate and the chip.

[0026] In one embodiment, the chip may be a three-dimensional memory chip.

[0027] This application provides a chip packaging structure in which insulating material is filled into the etch-back opening of the electroplating wire to form an etch-back filling structure. The concavity of the etch-back filling structure is controlled to ensure reliable chip bonding. This method not only solves the problem of chip and substrate delamination and subsequent chip failure caused by the concavity of the etch-back opening of the electroplating wire, but also does not increase the substrate thickness. Specifically, the substrate thickness of the chip packaging structure according to the exemplary embodiment of this application can be substantially the same as that of a conventional electroplating line etch-back substrate. Furthermore, the chip packaging method according to the embodiment of this application only requires an additional etch-back opening filling process before conventional packaging operations, offering the advantage of simplified process flow, and the raw material cost can remain largely consistent with conventionally designed substrates. Therefore, the chip packaging structure and packaging method according to the embodiment of this application can effectively serve as an alternative solution to lineless designs, nickel-palladium-gold substrates, or organic solder mask substrates. Attached Figure Description

[0028] The above and other advantages of embodiments of this application will become apparent from the following detailed description with reference to the accompanying drawings, which are intended to illustrate exemplary embodiments of this application and not to limit them. In the drawings:

[0029] Figure 1 This is a schematic structural diagram of a chip packaging structure according to an exemplary embodiment of this application;

[0030] Figure 2 yes Figure 1 Enlarged view of section A in the middle;

[0031] Figure 3 This is a top view of a chip packaging structure according to an exemplary embodiment of this application;

[0032] Figure 4 This is a schematic diagram of an arrayed chip packaging structure according to an exemplary embodiment of this application;

[0033] Figure 5 This is a schematic diagram of a fixture for back-etching window filling according to an exemplary embodiment of this application;

[0034] Figure 6 This is a schematic flowchart of a chip packaging method according to an exemplary embodiment of this application;

[0035] Figures 7a to 7h This is a schematic diagram of the fabrication process of the etch-back substrate; and

[0036] Figures 8 to 12 This is a schematic diagram of the manufacturing process of a chip packaging structure according to an exemplary embodiment of this application. Detailed Implementation

[0037] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Throughout the accompanying drawings and detailed embodiments, the same reference numerals refer to the same elements. For purposes of clarity, illustration, and convenience, the drawings may not be drawn to scale, and the relative dimensions, scale, and depiction of elements in the drawings may be exaggerated.

[0039] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this application, the first metal layer discussed below may also be referred to as the second metal layer, and vice versa.

[0040] As used herein, the terms “approximately,” “about,” and similar terms are used as terms indicating approximation, not as terms indicating degree, and are intended to describe inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0041] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] High-density products typically employ substrate-based packaging. Surface treatments for these substrates include nickel-gold (Ni / Au), nickel-palladium-gold (ENEPIG), and organic solder resist (OSP). While Ni / Au technology is relatively easy to design, its bonding is more challenging, making it unsuitable for fine-pitch bonding pads and limiting its application. OSP technology is also relatively easy to design, but it's unsuitable for chip-side bonding pads, only for ball pads. Furthermore, OSP-treated substrates have a shorter shelf life and are prone to oxidation; some chip manufacturers even specify that they should not use OSP. Therefore, Ni / Au is the mainstream substrate surface treatment, suitable for designs with fine-pitch gold-plated fingers on the front and gold-plated ball pads on the back. The chip packaging structure described below uses a Ni / Au substrate as an example, but the substrate used in this application is not limited to Ni / Au substrates.

[0045] In addition, the common technologies for nickel-gold plating on packaging substrates are line-back etching and lineless plating. Among them, lineless plating is more difficult, has a longer process, and is prone to quality problems such as gold plating over-plating, so it is less commonly used. Line-back etching, on the other hand, is a relatively mature high-density nickel-gold plating process for packaging substrates. The process is mature and simple, and the etched substrate does not require electrical testing, giving it a certain cost advantage.

[0046] The inventors of this application discovered in their research that the depth of the etch-back openings in the substrate can reach or exceed 30 μm. After the chip is bonded to the substrate, voids still exist at the bottom of the chip film. During subsequent assembly of the package and the motherboard, when temperature changes occur, these voids can easily lead to delamination between the chip and the substrate, resulting in chip failure. The inventors further noted that in related technologies, recoating the substrate surface with a solder resist layer can also fill the etch-back depression area. However, this secondary solder resist coating increases the board thickness, and consequently, the cost of the solder resist material also increases. Therefore, this application proposes a more advantageous chip packaging structure.

[0047] Figure 1 This is a schematic structural diagram of a chip packaging structure 1000 according to an exemplary embodiment of this application. Figure 2 yes Figure 1 Enlarged view of part A in the middle.

[0048] refer to Figure 1 The chip packaging structure 1000 according to an exemplary embodiment of this application may include a substrate 1 and a chip 3. The substrate 1 may be an organic substrate and may include any chip packaging substrate that requires surface electroplating treatment. The chip 3 may be, for example, a three-dimensional memory chip, and this application is not limited thereto.

[0049] refer to Figure 1 The substrate 1 includes a substrate body 10, a metal circuit layer 11, and a solder mask layer 12. The metal circuit layer 11 and the solder mask layer 12 can be disposed on the front and back sides of the substrate body 10. For example, the metal circuit layer 11 may include a plurality of bonding contacts 110 and a plurality of pads 112, with the bonding contacts 110 located on the front side of the substrate body 10 and the pads 112 located on the back side of the substrate body 10.

[0050] The surfaces of the bonding contact 110 and the pad 112 include a first metal layer 4 and a second metal layer 5. Exemplarily, the first metal layer 4 may contain nickel, and the second metal layer 5 may contain gold. The first metal layer 4 and the second metal layer 5 on the surfaces of the bonding contact 110 and the pad 112 are formed using a surface electroplating technique. This electroplating technique typically involves forming electroplating conductors, such as copper conductors, on one side of the area to be electroplated. These electroplating conductors serve as current conduction paths during electroplating. After electroplating, to prevent leakage or static electricity accumulation, a metal back etching process is performed to remove these electroplating conductors, thus forming an etch-back window.

[0051] The chip package structure 1000 may further include an etch-back filling structure 2. The etch-back filling structure 2 is formed by filling an etch-back window (not shown) after the electroplated wires have been etched away with an insulating material. The insulating material may be a semiconductor filler adhesive, which requires curing or semi-curing after filling the etch-back window. Exemplarily, the etch-back filling structure 2 may have a recess on its surface away from the substrate body 10. The chip 3 can be bonded to the solder resist layer 12 via a chip adhesive film 31, covering the etch-back filling structure 2.

[0052] In related technologies, after electroplating, the electroplated wires can be removed and a solder resist layer can be applied. While this can fill the recessed area of ​​the etch-back opening, the secondary solder resist layer increases the substrate thickness and also increases the amount and cost of solder resist material. In contrast, the substrate 1 of the chip packaging structure 1000 according to the embodiment of this application does not have an increased thickness; it can have a thickness approximately the same as that of a conventional electroplated etch-back substrate. The chip packaging structure 1000 according to the embodiment of this application only requires an additional step of filling the etch-back opening before the conventional packaging process, which is not only simple in process but also keeps the material cost essentially the same as that of conventionally designed substrates.

[0053] In an exemplary embodiment, combined with Figure 1 and Figure 2The height difference h between the lowest point of the upper surface 21 of the etch-back filling structure 2 and the upper surface 121 of the solder resist layer 12 is defined as the depth of the recess. The height difference h can be measured in a direction perpendicular to the substrate body 10. By controlling the height difference h (i.e., the recess depth of the etch-back filling structure) within the range of about 1 μm to about 10 μm, it can be ensured that when the chip adhesive film 31 on the back of the chip is heated to fix the chip 3 to the substrate 1, the chip adhesive film 31 can just fill the recess located at the upper surface 21 of the etch-back filling structure 2. For example, the chip adhesive film 31 is a DAF film. It can be understood that when h is greater than about 10 μm, the recess of the filling structure 2 is too large, which will cause voids to remain at the bottom of the chip adhesive film 31 after the chip 3 is attached to the substrate 1. In this case, it is equivalent to insufficient recess filling. If there is a temperature change during the subsequent installation of the package with the motherboard, the thermal expansion and contraction of the incompletely filled recess will cause delamination between the chip 3 and the substrate 1, thereby causing the chip 3 to fail. On the other hand, it is understandable that when h is less than 1µm, the filler material may expand and protrude from the upper surface 121 of the solder resist layer 12 during the curing process, causing the chip 3 to break after bonding due to uneven bonding surface. In particular, when the filler material protrudes from the upper surface 121 of the solder resist layer 12, it may also cause the filler material, solder resist layer 12 and chip adhesive film 31 to form a sandwich composite surface of three materials, resulting in unreliable bonding of chip 3 and possible delamination of the bonding surface in the later stage.

[0054] Figure 3 This is a top view of a chip packaging structure 1000 according to an exemplary embodiment of this application. The cross-section of the etch-back filling structure 2 in the direction parallel to the surface of the substrate 1 is a circular cross-section, and the diameter d of the circular cross-section can be in the range of about 100 μm to about 500 μm. It should be understood that the circular cross-section given herein is merely exemplary, and those skilled in the art can design a suitable cross-sectional shape according to actual needs based on the teachings of the disclosure of this application.

[0055] like Figure 3 As shown, the etch-back filling structure 2 can be located directly below the chip 3. Alternatively, the etch-back filling structure 2 can also be located diagonally below the chip 3, or it can be distributed in an array on the substrate body 10.

[0056] Figure 4This is a mosaic diagram of multiple chip package structures 1000. In an exemplary embodiment, the etch-back windows 1130 of the substrate 1 can be designed in a matrix distribution. The matrix distribution of the etch-back windows 1130 can be based on one chip package structure 1000 as a repeating unit, or on two or more chip package structures 1000 as repeating units. It should be understood that the number and arrangement of the etch-back windows 1130 are not limited to the number and arrangement shown in the figure, but can be designed according to actual needs. This application does not make specific limitations in this regard.

[0057] Figure 5 A matrix filling fixture 300 according to an exemplary embodiment of this application is shown. The matrix filling fixture 300 may include a plurality of filling material channels 301, each corresponding to a back-etching window 1130. A fixing device 400 may also be provided for fixing the plurality of matrix filling fixtures 300. Figure 5 The diagram only schematically shows the shape of the matrix filling fixture 300. The shape of the matrix filling fixture is not limited to this and can be designed according to actual needs. The matrix filling fixture 300 can fill the etch-back windows 1130 on the substrate 1 in an array-like manner. The matrix correspondence between the matrix filling fixture 300 and the etch-back windows 1130 on the substrate 1 not only improves the efficiency of the filling operation but also allows for more precise control of the amount of filling material used in the etch-back windows 1130, resulting in better concavity consistency of the etch-back filling structure 2.

[0058] Back Figure 1 The chip packaging structure 1000 according to an exemplary embodiment of this application may further include bonding wires 6. The bonding wires 6 electrically connect the chip 3 to the bonding contacts 110. Exemplarily, the bonding wires 6 may be one of gold wire, copper wire, silver wire, aluminum wire, gold-plated silver wire, or alloy wire. The surface material of the bonding contacts 110 may be adapted to the material of the bonding wires 6 to ensure the strength and reliability of the bond. Exemplarily, the shape of the bonding contacts 110 may be elongated (see...). Figure 3 ).

[0059] refer to Figure 1The chip packaging structure 1000 according to an exemplary embodiment of this application also includes a molding compound 7. The molding compound 7 can have the following functions: protecting the chip from the influence of the external environment; resisting external moisture, solvents, and impacts; electrically insulating the chip from the external environment; ensuring good mounting performance; resisting thermal shock and mechanical vibration during mounting; and facilitating heat diffusion, etc. Exemplarily, the molding compound 7 can be an epoxy molding compound (EMC), i.e., epoxy resin molding compound or epoxy molding material, which is a powdered molding compound made by mixing epoxy resin as the base resin, high-performance phenolic resin as the curing agent, silica powder and other fillers, and various additives.

[0060] refer to Figure 1 The chip package structure 1000 according to an exemplary embodiment of this application further includes solder balls 8, wherein the pads 112 can be solder ball pads, and the solder balls 8 are mounted on the pads 112 by a ball-mounting process for electrical connection between the chip 3 and the outside world. Exemplarily, a ball grid array (BGA) can be formed on a plurality of pads 112 on the back side of the substrate 1, and the ball grid array can serve as an interface for the chip 3 to connect with the outside world.

[0061] Another aspect of this application also provides a method for chip packaging. Figure 6 This is a schematic flowchart of a chip packaging method 2000 according to an exemplary embodiment of this application, the method 2000 including the following steps:

[0062] Step S201: Form a solder resist layer and an etch-back window on the substrate body of the substrate;

[0063] Step S202: Fill the etch-back windows with insulating material to form an etch-back filling structure; and

[0064] Step S203: Fix the chip on the solder mask layer and make the chip cover the etch-back fill structure.

[0065] It should be understood that the steps shown in Method 2000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. The following is in conjunction with... Figures 7a to 7h , Figures 8 to 12 The specific processes for each step of the above-described packaging method 2000 are explained in detail.

[0066] Step S201

[0067] refer to Figure 7h A solder resist layer 12 and an etch-back window 1130 are formed on the substrate body 10 of the substrate. The etch-back window 1130 is a window structure formed by etching the electroplated wires after the substrate has completed the surface electroplating operation. The following will be combined with Figures 7a to 7hThe formation process of the etch window 1130 is explained in detail. Figures 7a to 7h This is a schematic diagram of the process for fabricating an etch-back substrate. For example... Figures 7a to 7h As shown, the process of fabricating an etch-back substrate mainly includes the following steps:

[0068] Conductive layers 101 are formed on the front and back sides of the substrate body 10. For example, the conductive layer 101 may be made of copper.

[0069] Subsequently, the conductive layer 101 is processed into a predetermined circuit layer 11, wherein the circuit layer 11 may include electroplating wires 113, bonding contacts 110, and pads 112. The bonding contacts 110 may be located on the front side of the substrate body 10, and the pads 112 may be located on the back side of the substrate body 10.

[0070] Subsequently, a solder mask layer 12 is fabricated, which covers the circuit layer 11 and the substrate body 10, while exposing the electroplating wires 113, the bonding contacts 110 to be electroplated, and the pads 112.

[0071] Subsequently, photoresist 13 is printed so that it covers the entire substrate surface.

[0072] Subsequently, after processes such as exposure and development, the bonding contacts 110 and pads 112 that need to be electroplated are opened.

[0073] Subsequently, electroplating is performed on the bonding contacts 110 and the pads 112. Specifically, a first metal layer 4 is electroplated on the surfaces of the bonding contacts 110 and the pads 112, and then a second metal layer 5 is electroplated on the first metal layer 4. For example, the first metal layer 4 may include nickel, and the second metal layer 5 may include gold.

[0074] Subsequently, the remaining photoresist 13 is removed.

[0075] Subsequently, the electroplating wire 113 is etched to form a back-etching window 1130.

[0076] Figure 4 This is a schematic diagram of an arrayed chip package structure. In an exemplary embodiment, the etch-back windows 1130 can be designed in a matrix distribution. The matrix distribution of the etch-back windows 1130 can be based on one chip package structure as a repeating unit, or on two or more chip package structures as repeating units.

[0077] refer to Figure 4 and Figure 7h In an exemplary embodiment, the cross-section of the etch-back window 1130 in the direction parallel to the surface of the substrate body 10 is set as a circular cross-section, and the diameter d of the circular cross-section can be in the range of about 100 μm to about 500 μm. Figure 7hThe diameter of the circular cross-section of the 1130-degree window in the middle erosion is... Figure 3 The diameter of the circular cross-section of the intermediate etch-filling structure. It should be understood that the circular cross-section given herein is merely exemplary, and those skilled in the art can design suitable cross-sectional shapes according to actual needs based on the teachings of this application.

[0078] Step S202

[0079] refer to Figure 8 An insulating material is used to fill the etch-back window 1130 to form the etch-back filled structure 2. For example, the insulating material can be a semiconductor filler adhesive, which needs to be cured or semi-cured after filling before proceeding to the next step.

[0080] In an exemplary implementation, reference Figure 2 The etch-back filling structure 2 has a recess on its surface away from the substrate body 10. The recess depth of the etch-back filling structure 2 can be in the range of about 1 μm to about 10 μm, that is, the height difference h between the lowest point of the recess of the etch-back filling structure 2 and the upper surface 121 of the solder resist layer 12 can be in the range of 1 μm to 10 μm. Controlling the recess of the etch-back filling structure 2 can ensure that when the chip adhesive film 31 on the back of the chip is heated to fix the chip 3 to the substrate 1, the chip adhesive film 31 can just fill the recess located at the upper surface 21 of the etch-back filling structure 2. For example, the chip adhesive film 31 is a DAF film. It can be understood that when h is greater than about 10 μm, the recess of the filling structure 2 is too large, which will cause voids to remain at the bottom of the chip adhesive film 31 after the chip 3 is attached to the substrate 1. In this case, it is equivalent to insufficient recess filling. If there is a temperature change during the subsequent installation of the package with the motherboard, the thermal expansion and contraction of the incompletely filled recess will cause delamination between the chip 3 and the substrate 1, thereby causing the chip 3 to fail. On the other hand, it is understandable that when h is less than 1µm, the filler material may expand and protrude from the upper surface 121 of the solder resist layer 12 during the curing process, causing the chip 3 to break after bonding due to uneven bonding surface. In particular, when the filler material protrudes from the upper surface 121 of the solder resist layer 12, it may also cause the filler material, solder resist layer 12 and chip adhesive film 31 to form a sandwich composite surface of three materials, resulting in unreliable bonding of chip 3 and possible delamination of the bonding surface in the later stage.

[0081] Step S203

[0082] refer to Figure 9 The chip 3 is fixed on the solder resist layer 12, and the chip 3 is covered by the etch-back filling structure 2.

[0083] In an exemplary embodiment, the chip 3 is attached to the solder resist layer 12 via a chip adhesive film 31 on the back side of the chip 3. Exemplarily, the chip adhesive film 31 is a DAF film. This application uses only a DAF film as an example, but it should be understood that the adhesive film on the back side of the chip is not limited to a DAF film.

[0084] In an exemplary implementation, reference Figure 10 Method 2000 also includes a bonding process, namely, electrically connecting the chip 3 to the bonding contact 110 using bonding wire 6. Exemplarily, the bonding wire 6 can be one of gold wire, copper wire, silver wire, aluminum wire, gold-plated silver wire, or alloy wire. Exemplarily, such as... Figure 3 As shown, the shape of the bonding contact 110 can be elongated.

[0085] In an exemplary implementation, reference Figure 11 Method 2000 also includes an injection molding process, in which the chip 3 and the substrate 1 are embedded in an encapsulating material such as epoxy molding compound, cured and molded, and finally become a semiconductor device with a certain structural shape.

[0086] In an exemplary implementation, reference Figure 12 Method 2000 also includes a ball-mounting process, which involves assembling solder balls on multiple pads 112 on the back of substrate 1 to form a solder ball array, which serves as the interface between chip 3 and the outside world.

[0087] In an exemplary embodiment, chip 3 may be, for example, a three-dimensional memory chip, which is not limited in this application.

[0088] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this application.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a substrate, comprising: a substrate body; a solder resist layer located on the substrate body; and an etch-back filling structure located on the substrate body and formed of an insulating material, the etch-back filling structure having a recess on a surface thereof away from the substrate body; a chip sticking film, a portion of which is filled in the recess; and a chip fixed to the substrate, the chip being attached to the solder resist layer via the chip sticking film and covering the etch-back filling structure.

2. The chip package structure of claim 1, wherein, The etch-back filling structure has a circular cross section with a diameter in a range of 100 um to 500 um.

3. The chip package structure of claim 1, wherein, The etch-back filling structure is distributed on the substrate body in a preset array form.

4. The chip package structure of claim 1, wherein, The recess of the etch-back filling structure has a recess depth in a range of 1 um to 10 um.

5. The chip package structure of claim 1, wherein, The substrate comprises an organic substrate.

6. The chip package structure of claim 1, wherein, The chip package structure further comprises a pad and a bonding contact, a surface material of the pad and the bonding contact comprising at least one of nickel and gold.

7. The chip package structure of claim 6, wherein, The chip package structure further comprises: a bonding wire for electrically connecting the chip with the bonding contact.

8. The chip package structure of any one of claims 1-7, wherein, The chip comprises a three-dimensional memory chip.

9. A method of chip packaging, characterized by, The method comprises: forming a solder resist layer and an etch-back window on a substrate body of a substrate; filling the etch-back window with an insulating material to form an etch-back filling structure, and causing the etch-back filling structure to form a recess on a surface thereof away from the substrate body; and fixing a chip on the solder resist layer via a chip sticking film, a portion of the chip sticking film being filled in the recess, and causing the chip to cover the etch-back filling structure.

10. The method of claim 9, wherein, The etch-back filling structure has a circular cross section in a direction parallel to a surface of the substrate body, the circular cross section having a diameter in a range of 100 um to 500 um.

11. The method of claim 9, wherein, The step of forming the etch-back filling structure comprises: forming the etch-back filling structure, and causing the etch-back filling structure to be distributed on the substrate body in a preset array form.

12. The method of claim 9, wherein, The recess of the etch-back filling structure has a recess depth in a range of 1 um to 10 um.

13. The method of claim 9, wherein, The substrate comprises an organic substrate.

14. The method of claim 9, wherein, The method further comprises: electroplating a metal layer on the pad and the bonding contact of the substrate, wherein the metal layer comprises at least one of nickel and gold.

15. The method of claim 14, wherein, The method further comprises: electrically connecting the chip with the bonding contact via a metal wire.

16. The method of claim 9, wherein, The method further comprises: injection molding to encapsulate the substrate and the chip.

17. The method according to any one of claims 9-16, characterized by, The chip is a three-dimensional memory chip.

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