Passive driving lossless soft switching clamping circuit

Abstract

This invention discloses a passive-driven, lossless soft-switching clamping circuit, comprising a first transformer, a first unit, a passive-driven soft-switching clamping unit, and a second unit. The first unit includes a rectifier and filter circuit for rectifying and filtering AC voltage to obtain a DC bus voltage. The passive-driven soft-switching clamping unit includes a first diode, a second diode, a third diode, a second capacitor, a third capacitor, and a second switch. The second unit includes a QR mode controller, a first resistor, a second resistor, a third resistor, a first switch, and a first capacitor. Energy is transferred to the secondary side through the switching of the first switch. The first resistor is a current sampling resistor, sampling the current signal and providing it to the QR mode controller. The second resistor and the third resistor form a resistor divider, providing a demagnetizing signal to the QR mode controller. The passive-driven soft-switching clamping circuit provided by this invention not only realizes the function of a traditional RCD clamping circuit but also provides zero-voltage turn-on and turn-off conditions for the main switch, and it also achieves soft-switching itself without requiring additional drive and power supply circuits.

Description

Technical Field

[0001] This invention belongs to the field of circuit technology, specifically relating to a passive drive lossless soft switching clamping circuit. Background Technology

[0002] QR mode flyback topologies are widely used in switching power supplies below 150W, such as in fast charging or LED lighting. A conventional QR flyback primary side includes a main switch MOSFET and an RCD clamping circuit. The main switch Q1 experiences capacitive discharge through C1 during turn-on and hard switching off during turn-off. This is particularly pronounced at high frequencies (above 100kHz), where losses increase significantly with further frequency increases, limiting further increases in operating frequency and hindering the achievement of high power density per unit volume. Simultaneously, the RCD clamping circuit constantly discharges through resistor R, representing a fixed loss and further limiting overall efficiency.

[0003] With the accelerated commercialization of third-generation semiconductors, novel semiconductor devices such as gallium nitride and silicon carbide can only fully realize their superior performance by operating in the high-frequency range. Therefore, developing driving topologies suitable for third-generation semiconductors has become an urgent issue. This invention addresses this problem by providing an alternative solution. Summary of the Invention

[0004] The problem solved by this invention is to provide a soft-switching topology suitable for high frequency and high power density, applicable to, but not limited to, driving third-generation semiconductor power devices. To this end, based on the existing flyback QR topology, the original RCD clamping section is improved to achieve the effect of soft switching.

[0005] To achieve the above objectives, the present invention provides a technical solution: a passive-driven, lossless soft-switching clamping circuit, comprising a first transformer, a first unit, a passive-driven soft-switching clamping unit, and a second unit. The first unit is equipped with a rectifier and filter circuit, which is used to rectify and filter AC voltage to obtain a DC bus voltage. The passive-driven soft-switching clamping unit includes a first diode, a second diode, a third diode, a second capacitor, a third capacitor, and a second switching transistor. The second unit includes a QR mode controller, a first resistor, a second resistor, a third resistor, a first switch, and a first capacitor. Energy is transmitted to the secondary side through the switching of the first switch. The first resistor is a current sampling resistor, sampling the current signal and providing it to the QR mode controller. The second resistor and the third resistor form a resistor divider, providing a demagnetizing signal to the QR mode controller.

[0006] Assuming that at time t0, the voltage across the first capacitor is approximately zero, the QR mode controller turns on the first switch, and the first transformer begins to store energy until time t1;

[0007] At time t1, the first switch is turned off. Because of the presence of the first capacitor, the first switch is turned off at zero voltage. Let the primary inductance of the first transformer be Lp = Lm + Ll, where Lm is the primary magnetizing inductance and Ll is the leakage inductance. Then Lp resonates with the first capacitor C1 until time t2.

[0008] At time t2, the voltage of the first capacitor C1, which is connected in parallel with the first switch, rises to the bus voltage Vbus. At this time, the second capacitor and the input capacitor Ciss2 of the second switch are connected in series and then in parallel with the third capacitor. Their equivalent parallel capacitance is then connected in parallel with the first capacitor, and they all participate in resonance. At this time, the body diode of the second switch turns on and begins to conduct, which is a zero-voltage turn-on. As the voltage of Ciss2 rises to the conduction threshold of the second switch, the second switch turns on with zero voltage, preparing for the subsequent process, up to time t3. Because the body diode of the second switch turns on earlier, the Miller effect of the second switch is weakened, Ciss2 is relatively fixed, and a large drive current is not required.

[0009] At time t3, the voltage across the DS terminals of the first switch Q1 reaches Vds = Vbus + n*Vo, and the energy stored in the primary inductor begins to be transferred to the secondary. At this time, the inductance Lm of the first transformer is clamped by the secondary, and only the leakage inductance Ll resonates with the equivalent capacitance of the first capacitor / / the third capacitor / / the second capacitor + Ciss2. The voltage Vds across the DS terminals of the first switch Q1 surges rapidly, and then falls back to Vds = Vbus + n*Vo until time t4. After that, this voltage is maintained for the energy transfer process.

[0010] At time t5, since energy transfer is complete and the secondary side is disconnected from the circuit, and because the second switch was previously turned on, the equivalent capacitance of the first capacitor / / the third capacitor / / the second capacitor begins to resonate with the primary inductor Lp, transferring energy from the first capacitor, the second capacitor, and the third capacitor to Lp. During this process, Ciss2 is blocked by the second diode and will maintain its initial voltage until VCiss2 = VC3. The third diode provides a reverse discharge path for the second capacitor. When VCiss2 = VC3, the equivalent capacitance of Ciss2 / / the first capacitor / / the second capacitor / / the third capacitor begins to resonate with Lp until time t6. The first diode provides a discharge path for Ciss2. In actual analysis, because the voltage across Ciss2 is relatively small compared to VC3, the influence of Ciss2 is ignored for simplicity.

[0011] At time t6, when the voltage VCiss2 is less than the threshold voltage Vth of the second switch, the second switch Q2 is turned off. Because Vth is very small, it is turned off at approximately zero voltage. At this time, Ciss2, the second capacitor, and the third capacitor are disconnected from the circuit, and their energy is transferred to Lp. Lp and the first capacitor continue to resonate until time t7.

[0012] At time t7, there are two possibilities: one is that the current in Lp decreases to zero and the voltage Vds is also close to zero, in which case turning on the first switch is zero-voltage turn-on; the other is that the current in Lp is not zero, the first switch anti-parallel diode turns on, in which case turning on the first switch is also zero-voltage turn-on, and so on into the next cycle. By reasonably selecting parameters, the system can be made to work in the first case as much as possible, which can reduce conduction losses and duty cycle loss.

[0013] The technical effects and advantages of this invention: The passive drive soft-switching clamping circuit provided by this invention fully utilizes the Ciss2 of the second switching transistor and the second capacitor connected in series to divide the original clamping voltage, thereby achieving passive drive of the second switching transistor. In the subsequent stage, the energy in the clamping capacitor is fed back to the bus smoothing capacitor through resonance to achieve lossless operation. It not only realizes the function of the traditional RCD clamping circuit, but also creates the conditions for zero-voltage turn-on and turn-off of the main switch, and also realizes soft-switching itself without the need for additional drive and power supply circuits, thus having superior performance and cost advantages. The first and second switching transistors used in this invention can be second-generation semiconductor MOSFETs (including planar and Cool MOSFETs) or third-generation semiconductor GaN transistors. Ciss2 and C1 can be the input and output capacitors of the switching transistor itself, or an additional parallel capacitor plus the sum of the input / output capacitors, depending on the actual application. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the passive drive lossless soft switching clamping circuit of the present invention.

[0015] Figure 2 This is a schematic diagram of the passive drive soft switch clamping unit of the present invention.

[0016] Figure 3 This is a schematic diagram of the second unit and the third unit of the present invention.

[0017] Figure 4 This is a schematic diagram of the waveform of Vds on the first switch in one switching cycle of the present invention. Detailed Implementation

[0018] like Figures 1 to 3As shown, a passive drive lossless soft switching clamping circuit includes a first transformer 10, a first unit 100, a second unit 200, a third unit 300, and a passive drive soft switching clamping unit 400. The first unit 100 has a rectifier and filter circuit 110, which is used to rectify and filter the AC voltage to obtain the DC voltage of the bus. The first transformer 10 couples the primary and secondary sides and transfers energy to the secondary side.

[0019] The second unit 200 includes a QR mode controller 210, a first switch Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth diode D4, a first capacitor C1, and a fifth capacitor C5. Energy is transferred to the secondary side through the switching of the first switch Q1. The first resistor R1 is a current sampling resistor that samples the current signal and sends it to the QR mode controller 210. The second resistor R2 and the third resistor R3 form a resistor divider that provides a demagnetizing signal to the QR mode controller 210. The fourth diode D4 and the fifth capacitor C5 provide auxiliary power to the QR mode controller 210.

[0020] The third unit 300 includes a fifth diode D5, a fourth capacitor C4, and a feedback unit 310. The third unit 300 provides a control signal to the QR mode controller 210 through the secondary sampling feedback unit 310. The QR mode controller 210 of the second unit 200 is used to receive the control signal and drive the first switch Q1. The fifth diode D5 and the fourth capacitor C4 are used for secondary rectification and filtering.

[0021] The passive drive soft switch clamping unit 400 includes a first diode D1, a second diode D2, a third diode D3, a second capacitor C2, a third capacitor C3, a second switch Q2, and a first Zener diode ZD1. The second capacitor C2 is connected in series with the input capacitor Ciss2 of the second switch Q2, and the first Zener diode ZD1 is connected in parallel between the gate and source terminals of the second switch Q2 to provide clamping protection. When the second switch Q2 of the passive drive soft switch clamping unit 400 is turned off, it clamps the first switch Q1 and creates the soft switch turn-on condition. The first switch Q1 is connected in parallel with the first capacitor C1.

[0022] The input capacitor Ciss2 is not limited to the input capacitor of the second switch Q2 itself, but may also include the sum of the additional external capacitor connected in parallel between GS and its own input capacitor.

[0023] In practice, assuming that at time t0, the voltage across the first capacitor C1 is approximately zero, the QR mode controller 210 turns on the first switch Q1, and the first transformer 10 begins to store energy until time t1.

[0024] At time t1, the first switch Q1 is turned off. Because of the presence of the first capacitor C1, the first switch Q1 is turned off with zero voltage. Let the primary inductance of the first transformer 10 be Lp = Lm + Ll, where Lm is the primary magnetizing inductance and Ll is the leakage inductance. Then Lp resonates with the first capacitor C1 until time t2.

[0025] At time t2, the voltage between the drain and source terminals of the first switch Q1 rises to the bus voltage Vbus. At this time, the second capacitor C2 and the input capacitor Ciss2 of the second switch Q2 are connected in series and then in parallel with the third capacitor C3. Their equivalent parallel capacitance is then connected in parallel with the first capacitor C1, and they all participate in resonance. At this time, the body diode of the second switch Q2 turns on and begins to conduct, which is a zero-voltage turn-on. As the voltage of Ciss2 rises to the conduction threshold of the second switch Q2, the second switch Q2 turns on with zero voltage, preparing for the subsequent process, until time t3.

[0026] At time t3, the voltage between the primary and secondary terminals of the first switch Q1 reaches Vds = Vbus + n*Vo (Vo is the output voltage, and n is the primary-secondary turns ratio). Energy stored in the primary inductor begins to transfer to the secondary. At this time, the inductor Lm of the first transformer 10 is clamped by the secondary, leaving only the leakage inductance Ll resonating with the equivalent capacitance of the first capacitor C1 / / the third capacitor C3 / / (the second capacitor C2 + Ciss2). The voltage surges rapidly, then drops back to Vds = Vbus + n*Vo at time t4. This voltage is maintained for energy transfer until time t5.

[0027] At time t5, since energy transfer is complete and the secondary side is disconnected from the circuit, and because the second switch Q2 was previously turned on, the equivalent capacitance of the first capacitor C1 / / the third capacitor C3 / / the second capacitor C2 begins to resonate with the primary inductance Lp (=Lm+Ll), transferring energy from the first capacitor C1, the second capacitor C2, and the third capacitor C3 to Lp. During this process, Ciss2 is blocked by the second diode D2, maintaining its initial voltage until Vciss2 (voltage on the input capacitor of the second switch) = VC3 (voltage on the third capacitor C3), where the third diode D3 provides a reverse recovery path for the second capacitor C2. When Vciss2 = VC3, the equivalent capacitance of Ciss2 / / the first capacitor C1 / / the second capacitor C2 / / the third capacitor C3 begins to resonate with Lp, where the first diode D1 provides a path for Ciss2 (this is only for clarity in describing the resonance process; the effect of Ciss2 is ignored in actual calculations to simplify the process). This process continues until time t6.

[0028] At time T6, when the voltage V(ciss2) is less than the threshold voltage Vth of the second switch Q2, the second switch Q2 is turned off. Because Vth is very small, it is turned off at approximately zero voltage. At this time, Ciss2, the second capacitor C2, and the third capacitor C3 are disconnected from the circuit, and their energy is transferred to Lp. Lp and the first capacitor C1 continue to resonate until time t7.

[0029] At time t7, there are two possibilities: either the current in Lp decreases to zero and the voltage Vds is also approximately zero, in which case turning on the first switch Q1 results in zero-voltage turn-on; or the current in Lp is not zero, and the anti-parallel diode of the first switch Q1 turns on, also resulting in zero-voltage turn-on. This process continues into the next cycle. By appropriately selecting parameters to ensure the system operates primarily in the first scenario, conduction losses and duty cycle loss can be minimized.

[0030] This patent primarily utilizes the second capacitor C2 and Cⅰss2 connected in series to divide the clamping voltage and drive the second switch Q2. This is one of the core protected items of this patent, and any operation involving this principle to drive the second switch Q2 is within the protection scope of this patent. Furthermore, Cⅰss2 is not limited to the input capacitance of the second switch Q2 itself, but can also include the sum of an additional external capacitor connected in parallel between GS and its own input capacitance.

[0031] Figure 4 The waveform diagram of Vds on the first switch Q1 for one switching cycle can be divided into 7 modes. As shown above, let the primary inductance Lp = Lm + Ll, where Lm is the magnetizing inductance coupled to the secondary and Ll is the leakage inductance. The bus voltage Vbus operates in the following modes:

[0032] Mode 1 (t0-t1): Assume that at time t0, the voltage Vds reaches its minimum value Vlow, and the inductor current is 0. At this time, the first switch Q1 is turned on (ZVZC turn-on). At time t1, the first switch Q1 is turned off because the first capacitor C1 is present, and the first switch Q1 is turned off at zero voltage. Let ton = t1 - t0, and the inductor current Ipeak at time t1 be...

[0033] Vbus*ton=Lp*Ipeak------ (1)

[0034] We get ton = t1 - t0 = Lp * Ipeak / Vbus

[0035] Mode 2 (t1-t2): From time t1 to time t2, Lp resonates with the first capacitor C1. At time t2, the voltage Vds of the first switch Q1 is Vbus. Let tr1 = t2 - t1, because the first capacitor C1 is rapidly charged, it can be approximated as being charged to Vbus by a constant current Ipeak.

[0036] C1*Vbus=Ipeak*tr1------- (2)

[0037] We get tr1 = t2 - t1 = C1 * Vbus / Ipeak

[0038] Mode 3 (t2-t3): At time t2, after the voltage Vds of the first switch Q1 reaches Vbus, the equivalent capacitance of the second capacitor C2 connected in series with Ciss2 and the third capacitor C3 are connected in parallel and resonate together with the first capacitor C1. Due to parameter settings, Ciss has a small influence and is ignored for ease of analysis. Moreover, for a given mode, if the start time is set to zero, the initial state of the mode corresponds to the initial state at time 0, which does not affect the analysis. Therefore, let time t2 correspond to time 0 at the start of mode 3. Then, for any time t∈(0, t3-t2), the inductor current is iL(t), the inductor voltage is uL(t), the voltage on the third capacitor C3 is uC3(t), the voltage on the first capacitor C1 is uC1(t), and iL(0)=Ipeak, uL(0)=0, uc3(0)=0, uc1(0)=Vbus. At time t3, uL(t3-t2) = -VRF = -n*Vo, where n is the transformer turns ratio and Vo is the output voltage.

[0039] uL(t)=Lp*d(iL(t)) / d(t) ---(3)

[0040] iL(t)=(C2+C3)*d(uc3(t)) / d(t)+C1*d(uc1(t)) / d(t) ----(4)

[0041] Where, uL(t) = -uc3(t) ---- (5)

[0042] uC1(t)=Vbus-uL(t) ----(6)

[0043] Substituting (5) and (6) into the above equation, we get...

[0044] iL(t)=-(C1+C2+C3)*d(uL(t)) / d(t) ----(7)

[0045] uL(t)=-Lp*(C1+C2+C3)*d(uL(t))” / d(t) ---(8)

[0046] Solving the above differential equation yields

[0047] uL(t)=A1*cos(ω1*t)+A2*sin(ω1*t) ---(9)

[0048] ω1=(Lp*(C1+C2+C3))^(-1 / 2),

[0049] Where A1 and A2 are undetermined coefficients.

[0050] When t=0, uL(0)=0, iL(0)=Ipeak, substituting these values, we get A1=0, A2=-Ipeak / [(C1+C2+C3)*ω1].

[0051] =-Ipeak*[Lp / (C1+C2+C3)]^(1 / 2)

[0052] =-Ipeak*Z0

[0053] Where Z0=[Lp / (C1+C2+C3)]^(1 / 2) is the characteristic impedance of the line.

[0054] Therefore, we obtain

[0055] iL(t)=Ipeak*cos(ω1*t) -----(10)

[0056] uL(t)=-Ipeak*Z0*sin(ω1*t) -----(11)

[0057] Therefore, the voltage and current at time t∈(0, t3-t2) and t=t3-t2 are...

[0058] iL(t3-t2)=Ipeak*cos[ω1*(t3-t2)]

[0059] uL(t3-t2)=-Ipeak*Z0*sin[ω1*(t3-t2)]

[0060] In this mode, because the second capacitor C2 and Ciss2 are connected in series, when the voltage on Ciss2 resonates to the turn-on threshold of the second switch Q2, the second switch Q2 turns on, preparing for the subsequent mode.

[0061] Mode 4 (t3-t4): This mode is the spike clamping stage, determining the maximum stress on the first switch Q1. At time t3, because the voltage on the primary inductor has reached the reflected voltage VRF = n*Vo, Lm is disengaged due to secondary clamping, and only L1 and the parallel equivalent capacitance of the first capacitor C1 / second capacitor C2 / third capacitor C3 resonate. By time t4, the voltage on Lp returns to VRF, and the voltage on the leakage inductance is 0. Similarly, as mentioned above, for t∈(0, t4-t3), we have

[0062] uLl(t)-VRF=-uc3(t) ----(12)

[0063] iLl(t)=(C1+C2+C3)*d(uc3(t)) / dt

[0064] =-(C1+C2+C3)*d(uLl(t)) / dt ---(13)

[0065] uLl(t)=Ll*d(iLl(t)) / dt ----(14)

[0066] Substituting (13) into (14) further yields

[0067] uLl(t)=-Ll*(C1+C2+C3)*d[ul(t)]” / dt

[0068] Where, iLl(0) = iL(t3-t2) = Ipeak*cos(ω1*(t3-t2))

[0069] Solving the above three equations, we get

[0070] uLl(t)=A11*cos(ω2*t)+A22*sin(ω2*t) ----(15)

[0071] Where A11 and A22 are undetermined coefficients. ω2=Ll*(C1+C2+C3))^(-1 / 2)

[0072] Substituting (15) into iLl(t) = -(C1+C2+C3)*d(uLl(t)) / dt, we get

[0073] iLl(t)=-(C1+C2+C3)*[A22*ω2*cos(ω2*t)-A11*ω2*sin(ω2*t)]

[0074] ---(16)

[0075] When t=0, uLl(0))=0, iLl(0)=Ipeak*cos(ω1*(t3-t2)).

[0076] We obtain A11=0, A22=-Ipeak*cos(ω1*(t3-t2)) / [(C1+C2+C3)*ω2]=-Ipeak*cos(ω1*(t3-t2))*Z01, where Z01=[Ll / (C1+C2+C3)]^(1 / 2), which is the characteristic impedance of the circuit at this time.

[0077] Therefore, we obtain

[0078] uLl(t)=-Ipeak*cos(ω1*(t3-t2))*Z01*sin(ω2*t)

[0079] iLl(t)=Ipeak*cos(ω1*(t3-t2))*cos(ω2*t)

[0080] Discussion: When d(uLl(t)) / dt=0, uLl(t) reaches its maximum value, resulting in ω2*ta=π / 2, and thus ta=π / (2*ω2). t4-t3=2*ta=π / ω2.

[0081] uLl(ta)=-Ipeak*cos[ω2*(t3-t2)]*Z01

[0082] Mode 5 (t4-t5): This mode is the flyback energy transfer stage. It can be simply derived from the volt-second balance equation.

[0083] n*Vo*(t5-t4)=Vbus*(t3-t2) -----(17)

[0084] We get t5-t4=Vbus*(t3-t2) / [n*Vo*(t5-t4)]

[0085] In this mode, uC3(t) = -uL(t) = -n*Vo is clamped until time t5.

[0086] Mode 6 (t5-t6): At time t5, energy transfer in the first transformer 10 is complete. Because the second switch Q2 in mode 3 has already been turned on, the first capacitor C1, the second capacitor C2, and the third capacitor C3 resonate with Lp, and energy begins to transfer in the reverse direction to Lp until time t6, when the voltage of the third capacitor C3 becomes 0. At this time, the second switch Q2 is turned off, and the second capacitor C2 and the third capacitor C3 are disconnected from the resonant circuit. For t∈(0, t6-t5), we have

[0087] uC3(t)=-uL(t) ----(18)

[0088] iL(t)=(C1+C2+C3)*d(uC3(t)) / dt ----(19)

[0089] uL(t)=Lp*d(iL(t)) / dt ----(20)

[0090] get

[0091] uL(t)=-Lp*(C1+C2+C3)*d(uL(t))” / dt ----(21)

[0092] Solving equation (21) yields

[0093] uL(t)=B1*cos(ω1*t)+B2*sin(ω1t) ----(22)

[0094] iL(t)=-(C1+C2+C3)*[B2*ω1*cos(ω1*t)-B1*ω1*sin(ω1*t)]----(23)

[0095] Where B1 and B2 are undetermined constants, and ω1=[Lp*(C1+C2+C3)]^(-1 / 2)

[0096] Substituting iL(0) = 0 and uL(0) = -VRF = -n*Vo at t = 0 into (22) and (23) we get

[0097] B1=-n*Vo, B2=0

[0098] Then uL(t)=-n*Vo*cos(ω1*t)-----(24)

[0099] At time t6, uC3(t6-t5)=0, then ω1*(t6-t5)=π / 2, thus obtaining...

[0100] t6-t5=π / (2*ω1)

[0101] iL(π / (2*ω1))=-(C1+C2+C3)*(n*Vo*ω1)

[0102] =-n*Vo / Z0,

[0103] Where Z0=[Lp / (C1+C2+C3)]^(1 / 2) is the characteristic impedance of the line, and a negative value indicates that the current direction is opposite to the set direction.

[0104] Mode 7 (t6-t7): Second resonance stage. As mentioned above, at time t6, the second capacitor C2 and the third capacitor C3 disconnect from the system, leaving only Lp resonating with the first capacitor C1. During this stage, for t∈(0, t7-t6)...

[0105] Vbus=uL(t)+uC1(t) -----(25)

[0106] uL(t)=Lp*d(iL(t)) / dt -----(27)

[0107] iL(t)=C1*d(uC1(t)) / dt ----(28)

[0108] From the above three equations, we can obtain

[0109] uL(t)=-Lp*C1*d(uL(t))” / dt ----(29)

[0110] Therefore, we obtain

[0111] uL(t)=B11*cos(ω3*t)+B22*sin(ω3*t)----(30)

[0112] iL(t)=-C1*[B22*ω3*cos(ω3*t)-B11*ω3*sin(ω3*t)]

[0113] Where B11 and B22 are undetermined constants, and ω3 = (Lp*C1)^(-1 / 2),

[0114] From the initial state, at t=0, corresponding to time t6, we can obtain from the previous mode...

[0115] uL(0) = 0, iL(0) = -n*Vo / Z0, thus obtaining

[0116] B11=0,B22=n*Vo / (Z0*C1*ω3)=n*Vo*Z02 / Z0, where Z02=(Lp / C1)^(1 / 2),

[0117] get

[0118] uL(t)=n*Vo*Z02 / Z0*sin(ω3*t)---(31)

[0119] iL(t)= -(n*Vo / Z0)*cos(ω3*t)

[0120] discuss:

[0121] At time t7, uC1(t7-t6) = 0, from which we obtain

[0122] uL(t7-t6)=n*Vo*Z02 / Z0*sin[ω3*(t7-t6)]=Vbus,

[0123] We get t7-t6=arcsin[(Vbus*Z0) / (n*Vo*Z02)] / ω3

[0124] At time t7, iL(t7-t6)=0, so ω3*(t7-t6)=π / 2.

[0125] (t7-t6)=π / (2*ω3)

[0126] uL(t7-t6) = n*Vo*Z02 / Z0, therefore

[0127] uC1(t)=Vbus-uL(t7-t6)=Vbus- n*Vo*Z02 / Z0.

Claims

1. A passive drive lossless soft-switching clamping circuit, characterized in that: The system includes a first transformer, a first unit, a second unit, a third unit, and a passive drive soft-switching clamping unit. The first unit has a rectifier and filter circuit, which is used to rectify and filter the AC voltage to obtain the DC bus voltage. The first transformer couples the primary and secondary windings and transfers energy to the secondary winding. The second unit includes a QR mode controller, a first switch, a first resistor, a second resistor, a third resistor, a fourth diode, a first capacitor, and a fifth capacitor. The first switch is connected between the primary winding of the first transformer and the first resistor. The QR mode controller transmits energy to the secondary winding by controlling the opening and closing of the first switch. The first resistor is a current sampling resistor connected between ground and the first switch, sampling the current signal and sending it to the QR mode controller. The second and third resistors form a voltage divider connected between the auxiliary winding of the first transformer and ground. The connection point of the second and third resistors provides a demagnetizing signal to the QR mode controller. The fourth diode and the fifth capacitor provide auxiliary power to the QR mode controller. The fifth capacitor is connected in parallel across the auxiliary winding of the first transformer. The anode of the fourth diode is connected to the auxiliary winding of the first transformer, and the cathode of the fourth diode is connected to the VCC terminal of the QR mode controller. The third unit includes a fifth diode, a fourth capacitor, and a secondary sampling feedback unit. The third unit provides a control signal to the QR mode controller via the secondary sampling feedback unit. The QR mode controller in the second unit receives the control signal and drives the first switch. The fifth diode and the fourth capacitor are used for secondary rectification and filtering. The passive drive soft-switching clamping unit includes a first diode, a second diode, a third diode, a second capacitor, a third capacitor, a second switching transistor, and a first Zener diode. The first Zener diode is connected in parallel between the gate and source terminals of the second switching transistor to provide clamping protection. The first Zener diode is connected in parallel with the input capacitor Ciss2 of the second switching transistor. The drain terminal of the second switching transistor is connected to one end of the primary winding of the first transformer, and the source terminal of the second switching transistor is connected to the other end of the primary winding of the first transformer via the third capacitor. The anode of the third diode is connected to one end of the third capacitor, and the cathode of the third diode is connected to one end of the second capacitor. The other end of the third capacitor is connected to the other end of the second capacitor. The anode of the second diode is connected to the cathode of the third diode, and the cathode of the second diode is connected to the cathode of the first Zener diode. The anode of the first diode is connected to the gate terminal of the second switching transistor, and the cathode of the first diode is connected to the other end of the second capacitor. The second switching transistor of the passive drive soft-switching clamping unit clamps the first switch when it is turned off and creates the conditions for soft-switching on. The first switch is connected in parallel with the first capacitor. The input capacitor Ciss2 includes the input capacitance of the second switch transistor itself, or the sum of the input capacitance of the second switch transistor itself and an additional external capacitor connected in parallel between the gate and source terminals of the second switch transistor.

Images