Motor control device, motor unit, and vehicle

Abstract

A motor control device, a motor unit, and a vehicle are provided. A motor control device of one embodiment of the present application includes a motor drive circuit including an upper arm and a lower arm, an arithmetic processing device that controls the motor drive circuit, a substitute circuit that substitutes for the arithmetic processing device, and a mode switching section that switches a control mode between a first control mode in which the motor drive circuit is controlled by the arithmetic processing device and a second control mode in which the motor drive circuit is controlled by the substitute circuit, depending on a state of the arithmetic processing device. When the state of the arithmetic processing device changes from a normal state to an abnormal state, the mode switching section switches the control mode from the first control mode to the second control mode. In the second control mode, the substitute circuit controls switching of switching elements included in the upper arm and the lower arm, depending on states of the upper arm and the lower arm.

Description

TECHNICAL FIELD

[0001] The present application relates to a motor control device, a motor unit, and a vehicle. BACKGROUND

[0002] As a technique for protecting an inverter and a motor when an abnormality occurs in the inverter that drives the motor, there is known an active short-circuit control (ASC control) that controls all switching elements included in an upper arm or a lower arm of the inverter to be in an on state, and a shutdown control (SD control) that controls all switching elements of the inverter to be in an off state. Hereinafter, the ASC control and the SD control will be collectively referred to as a fail-safe control.

[0003] For example, in Patent Literature 1, there is disclosed a technique in which, in order to prevent the ASC control from being canceled due to an output current of the inverter instantaneously exceeding an overcurrent threshold value when the ASC control is executed, the overcurrent threshold value is changed from a normal-time threshold value to a short-circuit control-time threshold value that is larger than the normal-time threshold value when the ASC control is executed.

[0004] Further, for example, in Patent Literature 2, there is disclosed a technique in which, in order to prevent an excessive surge voltage from being applied to a switching element when the SD control is executed, all switching elements included in an upper arm are controlled to be in an off state when the SD control is executed, and all switching elements included in a lower arm are controlled to be in an off state after a prescribed time elapses.

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2017-225236

[0006] Patent Literature 2: Japanese Patent Application Publication No. 2014-217151

[0007] The motor control device has an arithmetic processing device such as an MCU (Micro Controller Unit) or a CPU (Central Processing Unit) that controls switching elements of the inverter. Generally, the fail-safe control including the ASC control and the SD control described above is executed by the arithmetic processing device. Therefore, if an abnormality occurs in the arithmetic processing device, there is a possibility that the fail-safe control is not executed. SUMMARY

[0008] In view of the above, an object of the present application is to provide a motor control device, a motor unit, and a vehicle that can execute a fail-safe control when an abnormality occurs in an arithmetic processing device.

[0009] A motor control device of one embodiment of the present application includes a motor drive circuit including an upper arm and a lower arm, an arithmetic processing device that controls the motor drive circuit, a substitute circuit that substitutes for the arithmetic processing device, and a mode switching section that switches a control mode between a first control mode in which the motor drive circuit is controlled by the arithmetic processing device and a second control mode in which the motor drive circuit is controlled by the substitute circuit, in accordance with a state of the arithmetic processing device. The mode switching section switches the control mode from the first control mode to the second control mode when the state of the arithmetic processing device changes from a normal state to an abnormal state. In the second control mode, the substitute circuit controls switching of switching elements included in the upper arm and the lower arm, in accordance with states of the upper arm and the lower arm.

[0010] A motor control device of one embodiment of the present application includes a motor drive circuit including an upper arm and a lower arm, an arithmetic processing device that controls the motor drive circuit, a substitute circuit that substitutes for the arithmetic processing device, a first overvoltage detection circuit that outputs a first overvoltage detection signal whose state changes in accordance with a magnitude of an input voltage of the motor drive circuit, and a mode switching section that switches a control mode between a first control mode in which the motor drive circuit is controlled by the arithmetic processing device and a second control mode in which the motor drive circuit is controlled by the substitute circuit, in accordance with the state of the first overvoltage detection signal. The arithmetic processing device compares the input voltage of the motor drive circuit with a first threshold value, and performs fail-safe control when the input voltage exceeds the first threshold value. The first overvoltage detection circuit compares the input voltage of the motor drive circuit with a second threshold value higher than the first threshold value, and changes the state of the first overvoltage detection signal from a first state to a second state when the input voltage exceeds the second threshold value. The mode switching section switches the control mode from the first control mode to the second control mode when the state of the first overvoltage detection signal changes from the first state to the second state. In the second control mode, the substitute circuit controls switching of switching elements included in the upper arm and the lower arm, in accordance with states of the upper arm and the lower arm.

[0011] A motor unit of one embodiment of the present application includes a motor and the motor control device described in the above embodiment.

[0012] A vehicle of one embodiment of the present application includes the motor unit described in the above embodiment.

[0013] According to the above embodiment of the present application, a motor control device, a motor unit, and a vehicle that can perform fail-safe control when an arithmetic processing device is abnormal can be provided. Attached Figure Description

[0014] Figure 1 This is a diagram schematically illustrating the structure of the vehicle according to this embodiment.

[0015] Figure 2 This is a schematic diagram showing the structure of the internal circuitry of the motor control device according to this embodiment.

[0016] Figure 3 This is a flowchart illustrating the motor control process executed by the MCU according to the program stored in non-volatile memory under normal circumstances.

[0017] Figure 4 This is a flowchart illustrating vector control performed by the MCU as a normal motor control.

[0018] Label Explanation

[0019] 1: Vehicle; 2: Drive wheel; 3: Vehicle sensor; 4: Acceleration position sensor; 5: Electronic control unit; 6: Motor unit; 7: High-voltage battery; 8: Low-voltage battery; 10: Motor; 20: Reducer; 30: Differential gear; 40: Motor control unit; 100: Motor drive circuit; 210: First separation circuit; 220: Second separation circuit; 300: MCU (Multi-MCU); 400: PMIC (Physical Microcontroller); 500: Alternate circuit; 610: First overvoltage detection circuit; 620: Second overvoltage detection circuit; 700: Logic AND circuit; 800: Multiplexer (mode switching unit). Detailed Implementation

[0020] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This diagram schematically illustrates the structure of vehicle 1 according to this embodiment. For example, vehicle 1 is an electric vehicle that travels using four wheels, including two drive wheels 2 and two steering wheels (not shown). Vehicle 1 according to this embodiment includes a vehicle speed sensor 3, an acceleration position sensor (APS) 4, an electronic control unit (ECU) 5, a motor unit 6, a high-voltage battery 7, and a low-voltage battery 8.

[0022] Vehicle speed sensor 3 detects the speed of vehicle 1 and outputs the detection result as vehicle speed data to electronic control device 5. Acceleration position sensor 4 detects the amount of pressure applied to the accelerator pedal and outputs the detection result as acceleration position data to electronic control device 5.

[0023] The electronic control device 5 controls the driving force transmitted to the drive wheels 2 by the motor unit 6 described later, based on the vehicle speed data input from the vehicle speed sensor 3 and the accelerator position data input from the accelerator position sensor 4. Specifically, the electronic control device 5 determines a torque command value Tm* of the driving force requested by the driver to be transmitted to the drive wheels 2 based on the vehicle speed data and the accelerator position data, and outputs a motor control signal CS indicating the torque command value Tm* to the motor unit 6.

[0024] The motor unit 6 drives the drive wheels 2 based on the motor control signal CS input from the electronic control device 5. Specifically, the motor unit 6 controls the torque of the motor 10 based on the torque command value Tm* indicated by the motor control signal CS, thereby transmitting the driving force requested by the driver to the drive wheels 2. The motor unit 6 has the motor 10, a speed reducer 20, a differential gear 30, and a motor control device 40.

[0025] The motor 10 is a high-output motor serving as a driving source of the vehicle 1. For example, the motor 10 is a three-phase synchronous motor of an inner rotor type. The motor 10 has a rotor shaft 11, a U-phase terminal 12u, a V-phase terminal 12v, a W-phase terminal 12w, a U-phase coil 13u, a V-phase coil 13v, and a W-phase coil 13w.

[0026] In addition, although the illustration is omitted in Figure 1 The motor 10 has a motor case and a rotor and a stator housed in the motor case. The rotor is a rotating body supported to be rotatable by a bearing member inside the motor case. The stator is fixed to the inside of the motor case in a state of surrounding the outer circumferential surface of the rotor, and generates an electromagnetic force required to rotate the rotor.

[0027] The rotor shaft 11 is an axially shaped body engaged with the above-described rotor in a coaxial manner. The U-phase terminal 12u, the V-phase terminal 12v, and the W-phase terminal 12w are metal terminals exposed from the surface of the motor case. The U-phase terminal 12u, the V-phase terminal 12v, and the W-phase terminal 12w are electrically connected to the motor control device 40. The U-phase coil 13u, the V-phase coil 13v, and the W-phase coil 13w are exciting coils provided to the stator. The U-phase coil 13u, the V-phase coil 13v, and the W-phase coil 13w are star-connected inside the motor 10.

[0028] The U-phase coil 13u is electrically connected between the U-phase terminal 12u and the neutral point N. The V-phase coil 13v is electrically connected between the V-phase terminal 12v and the neutral point N. The W-phase coil 13w is electrically connected between the W-phase terminal 12w and the neutral point N. By controlling the three-phase currents flowing in the U-phase coil 13u, the V-phase coil 13v, and the W-phase coil 13w by the motor control device 40, an electromagnetic force required to rotate the rotor is generated. By the rotation of the rotor, the rotor shaft 11 is also rotated in synchronization with the rotor. The rotational force of the rotor shaft 11 is transmitted to the drive wheels 2 via the power transmission mechanism including the speed reducer 20 and the differential gear 30.

[0029] The motor control device 40 controls the motor 10 in accordance with a motor control signal CS input from the electronic control device 5. Specifically, the motor control device 40 controls the three-phase currents flowing in the U-phase coil 13u, the V-phase coil 13v, and the W-phase coil 13w in accordance with a torque command value Tm* indicated by the motor control signal CS, thereby controlling the torque of the motor 10 to a value corresponding to the torque command value Tm*.

[0030] The motor control device 40 has a high-voltage positive terminal 41, a high-voltage negative terminal 42, a low-voltage positive terminal 43, and a low-voltage negative terminal 44 as power supply terminals. The high-voltage positive terminal 41 is electrically connected to the positive terminal of the high-voltage battery 7. The high-voltage negative terminal 42 is electrically connected to the negative terminal of the high-voltage battery 7. The low-voltage positive terminal 43 is electrically connected to the positive terminal of the low-voltage battery 8. The low-voltage negative terminal 44 is electrically connected to the negative terminal of the low-voltage battery 8.

[0031] The high-voltage battery 7 and the low-voltage battery 8 are, for example, secondary batteries such as lithium-ion batteries or nickel-hydrogen batteries. The high-voltage battery 7 outputs, for example, a high direct-current voltage HV of 470 V. The low-voltage battery 8 outputs, for example, a low direct-current voltage LV of 12 V. The internal circuit of the motor control device 40 is divided into a high-voltage system circuit and a low-voltage system circuit, the details of which will be described later. The high direct-current voltage HV output from the high-voltage battery 7 to the motor control device 40 is used as a power supply voltage for causing the high-voltage system circuit to operate, and the low direct-current voltage LV output from the low-voltage battery 8 to the motor control device 40 is used as a power supply voltage for causing the low-voltage system circuit to operate.

[0032] The motor control device 40 has a U-phase output terminal 45u, a V-phase output terminal 45v, and a W-phase output terminal 45w as output terminals. The U-phase output terminal 45u is electrically connected to the U-phase terminal 12u of the motor 10. The V-phase output terminal 45v is electrically connected to the V-phase terminal 12v of the motor 10. The W-phase output terminal 45w is electrically connected to the W-phase terminal 12w of the motor 10. A three-phase current is supplied from the motor control device 40 to the motor 10 via the U-phase output terminal 45u, the V-phase output terminal 45v, and the W-phase output terminal 45w, whereby the motor 10 rotates with a torque determined by the torque command value Tm*.

[0033] Figure 2 is a diagram schematically showing the structure of an internal circuit of the motor control device 40. As shown in Figure 2 , the motor control device 40 has a motor drive circuit 100, a first separation circuit 210, a second separation circuit 220, an MCU 300, a PMIC (Power Management Integrated Circuit) 400, a substitution circuit 500, a first overvoltage detection circuit 610, a second overvoltage detection circuit 620, a logic and circuit 700, and a multiplexer 800.

[0034] The motor drive circuit 100 is a three-phase inverter that converts direct-current electric power supplied from the high-voltage battery 7 into three-phase electric power and outputs the three-phase electric power to the motor 10. The motor drive circuit 100 has an upper arm 110 including three upper-side switching elements and a lower arm 120 including three lower-side switching elements. The upper arm 110 includes a U-phase upper-side switching element Q UH , a V-phase upper-side switching element Q VH , and a W-phase upper-side switching element Q WH . The lower arm 120 includes a U-phase lower-side switching element Q UL , a V-phase lower-side switching element Q VL , and a W-phase lower-side switching element Q WL . In the present embodiment, each switching element is, for example, an N-channel type IGBT. In addition, each switching element has a freewheeling diode in an anti-parallel manner.

[0035] The collector terminal of the U-phase upper-side switching element Q UH , the collector terminal of the V-phase upper-side switching element Q VH , and the collector terminal of the W-phase upper-side switching element Q WH are electrically connected to the high-voltage positive terminal 41. The emitter terminal of the U-phase lower-side switching element Q UL , the emitter terminal of the V-phase lower-side switching element Q VL , and the emitter terminal of the W-phase lower-side switching element Q WLThe transmitting terminals are electrically connected to the high-voltage negative terminal 42. Additionally, as described above, the high-voltage positive terminal 41 is electrically connected to the positive terminal of the high-voltage battery 7, and the high-voltage negative terminal 42 is electrically connected to the negative terminal of the high-voltage battery 7.

[0036] U-phase upper side switching element Q UH The transmitting terminal and the U-phase output terminal 45u and the U-phase lower switching element Q UL The collector terminals are electrically connected respectively. That is, the upper switching element Q of phase U is connected... UH The transmitting terminal is electrically connected to the U-phase terminal 12u of the motor 10 via the U-phase output terminal 45u.

[0037] V-phase upper switching element Q VH The transmitting terminal is connected to the V-phase output terminal 45V and the V-phase lower switching element Q. VL The collector terminals are electrically connected respectively. That is, the upper switching element Q of phase V is connected... VH The transmitting terminal is electrically connected to the V-phase terminal 12V of the motor 10 via the V-phase output terminal 45V.

[0038] W-phase upper switching element Q WH The transmitting terminal is connected to the W-phase output terminal 45w and the W-phase lower switching element Q. WL The collector terminals are electrically connected respectively. That is, the upper switching element Q of phase W is connected... WH The transmitting terminal is electrically connected to the W-phase terminal 12w of the motor 10 via the W-phase output terminal 45w.

[0039] The motor drive circuit 100 has an upper U-phase gate driver 111, an upper V-phase gate driver 112, an upper W-phase gate driver 113, a lower U-phase gate driver 121, a lower V-phase gate driver 122, and a lower W-phase gate driver 123 as gate drivers for driving the aforementioned switching elements.

[0040] U-phase upper gate driver 111 and U-phase upper switching element Q UH The gate terminal, collector terminal, and emitter terminal are electrically connected. The U-phase upper gate driver 111, according to the U-phase upper gate control signal UHG output from the multiplexer 800, enables the U-phase upper switching element Q... UH The gate voltage changes. Gate voltage refers to the voltage between the gate terminal and the emitter terminal. Specifically, for example, when the upper gate control signal UHG of phase U is high, the upper gate driver 111 of phase U causes the gate voltage to change so that the upper switching element Q of phase U changes. UH The value becomes the ON state. On the other hand, when the upper gate control signal UHG of phase U is low, the upper gate driver 111 of phase U causes the gate voltage to change so that the upper switching element Q of phase U becomes ON.UH a value that becomes the off state.

[0041] Further, the U-phase upper gate driver 111 outputs a fault signal FLT1 as an abnormality detection signal to the MCU 300 and the replacement circuit 500. The U-phase upper gate driver 111 is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the U-phase upper switching element Q UH When in the normal state, the U-phase upper gate driver 111 outputs the fault signal FLT1 at a high level. On the other hand, when in the abnormal state, the U-phase upper gate driver 111 outputs the fault signal FLT1 at a low level. For example, when an excessive collector current flows in the U-phase upper switching element Q UH , the collector-emitter voltage exceeds the saturation voltage. In this case, it is determined that the U-phase upper switching element Q UH is in the abnormal state. For example, the U-phase upper gate driver 111 monitors the collector-emitter voltage of the U-phase upper switching element Q UH , and when the collector-emitter voltage exceeds the saturation voltage, outputs the fault signal FLT1 at a low level. UH

[0042] Further, phenomena in which the U-phase upper switching element Q UH is determined to be in the abnormal state are not limited to the phenomenon in which an excessive collector current flows in the U-phase upper switching element Q UH . For example, the phenomenon in which the temperature of the U-phase upper switching element Q UH greatly rises is also a phenomenon in which the U-phase upper switching element Q UH is determined to be in the abnormal state. Therefore, for example, the U-phase upper gate driver 111 can monitor the temperature of the U-phase upper switching element Q UH using a thermistor or the like, and when the temperature exceeds a threshold value, outputs the fault signal FLT1 at a low level. Also, in a case where the U-phase upper gate driver 111 does not operate due to a reason such as the power supply voltage to the U-phase upper gate driver 111 not being input, the fault signal FLT1 at a low level can also be output.

[0043] The V-phase upper gate driver 112 is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the V-phase upper switching element Q VH . Similarly to the U-phase upper gate driver 111, the V-phase upper gate driver 112 changes the gate voltage of the V-phase upper switching element Q VH in accordance with the V-phase upper gate control signal VHG output from the multiplexer 800.

[0044] ​Also, similarly to the U-phase upper gate driver 111, the V-phase upper gate driver 112 outputs a failure signal FLT2 as an abnormality detection signal to the MCU 300 and the replacement circuit 500. That is, in a case where the V-phase upper switching element Q VH is in a normal state, the V-phase upper gate driver 112 outputs the failure signal FLT2 at a high level. On the other hand, in a case where the V-phase upper switching element Q VH is in an abnormal state, the V-phase upper gate driver 112 outputs the failure signal FLT2 at a low level.

[0045] The W-phase upper gate driver 113 is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the W-phase upper switching element Q WH . Similarly to the U-phase upper gate driver 111, the W-phase upper gate driver 113 changes the gate voltage of the W-phase upper switching element Q WH in accordance with the W-phase upper gate control signal WHG output from the multiplexer 800.

[0046] Also, similarly to the U-phase upper gate driver 111, the W-phase upper gate driver 113 outputs a failure signal FLT3 as an abnormality detection signal to the MCU 300 and the replacement circuit 500. That is, in a case where the W-phase upper switching element Q WH is in a normal state, the W-phase upper gate driver 113 outputs the failure signal FLT3 at a high level. On the other hand, in a case where the W-phase upper switching element Q WH is in an abnormal state, the W-phase upper gate driver 113 outputs the failure signal FLT3 at a low level.

[0047] The U-phase lower gate driver 121 is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the U-phase lower switching element Q UL . Similarly to the U-phase upper gate driver 111, the U-phase lower gate driver 121 changes the gate voltage of the U-phase lower switching element Q UL in accordance with the U-phase lower gate control signal ULG output from the multiplexer 800.

[0048] Also, similarly to the U-phase upper gate driver 111, the U-phase lower gate driver 121 outputs a failure signal FLT4 as an abnormality detection signal to the MCU 300 and the replacement circuit 500. That is, in a case where the U-phase lower switching element Q UL is in a normal state, the U-phase lower gate driver 121 outputs the failure signal FLT4 at a high level. On the other hand, in a case where the U-phase lower switching element Q UL is in an abnormal state, the U-phase lower gate driver 121 outputs the failure signal FLT4 at a low level.

[0049] The V-phase lower-side gate driver 122 is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the V-phase lower-side switching element Q VL Like the U-phase upper-side gate driver 111, the V-phase lower-side gate driver 122 changes the gate voltage of the V-phase lower-side switching element Q VL in accordance with the V-phase lower-side gate control signal VLG output from the multiplexer 800.

[0050] In addition, like the U-phase upper-side gate driver 111, the V-phase lower-side gate driver 122 outputs the fault signal FLT5 as an abnormality detection signal to the MCU 300 and the replacement circuit 500. That is, when the V-phase lower-side switching element Q VL is in the normal state, the V-phase lower-side gate driver 122 outputs the fault signal FLT5 at the high level. On the other hand, when the V-phase lower-side switching element Q VL is in the abnormal state, the V-phase lower-side gate driver 122 outputs the fault signal FLT5 at the low level.

[0051] The W-phase lower-side gate driver 123 is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the W-phase lower-side switching element Q WL . Like the U-phase upper-side gate driver 111, the W-phase lower-side gate driver 123 changes the gate voltage of the W-phase lower-side switching element Q WL in accordance with the W-phase lower-side gate control signal WLG output from the multiplexer 800.

[0052] In addition, like the U-phase upper-side gate driver 111, the W-phase lower-side gate driver 123 outputs the fault signal FLT6 as an abnormality detection signal to the MCU 300 and the replacement circuit 500. That is, when the W-phase lower-side switching element Q WL is in the normal state, the W-phase lower-side gate driver 123 outputs the fault signal FLT6 at the high level. On the other hand, when the W-phase lower-side switching element Q WL is in the abnormal state, the W-phase lower-side gate driver 123 outputs the fault signal FLT6 at the low level.

[0053] The 1st separation circuit 210 and the 2nd separation circuit 220 are circuits that separate the internal circuits of the motor control device 40 into a high-voltage system circuit and a low-voltage system circuit. The high-voltage system circuit includes the above-described motor drive circuit 100. The low-voltage system circuit includes the MCU 300, the PMIC 400, the replacement circuit 500, the 1st overvoltage detection circuit 610, the 2nd overvoltage detection circuit 620, the logic and circuit 700, and the multiplexer 800.

[0054] The input terminal of the 1st separation circuit 210 is electrically connected to the high-voltage positive terminal 41. The output terminal of the 1st separation circuit 210 is electrically connected to the input terminal of the 1st overvoltage detection circuit 610 and the overvoltage detection port 310 of the MCU 300. The 1st separation circuit 210 electrically separates the high-voltage system circuit from the low-voltage system circuit, and outputs the high direct-current voltage HV input from the high-voltage battery 7 as a low voltage that can be input to the 1st overvoltage detection circuit 610.

[0055] The input terminal of the 2nd separation circuit 220 is electrically connected to the high-voltage positive terminal 41. The output terminal of the 2nd separation circuit 220 is electrically connected to the input terminal of the 2nd overvoltage detection circuit 620. The 2nd separation circuit 220 electrically separates the high-voltage system circuit from the low-voltage system circuit, and outputs the high direct-current voltage HV input from the high-voltage battery 7 as a low voltage that can be input to the 2nd overvoltage detection circuit 620. The 1st separation circuit 210 and the 2nd separation circuit 220 are configured, for example, by a circuit including an isolator and a resistance dividing circuit, or the like.

[0056] The output voltage of the 1st separation circuit 210 is equal to the output voltage of the 2nd separation circuit 220. The output voltages of the 1st separation circuit 210 and the 2nd separation circuit 220 are in a proportional relationship with the high direct-current voltage HV input from the high-voltage battery 7, that is, the input voltage of the motor drive circuit 100. In other words, the output voltages of the 1st separation circuit 210 and the 2nd separation circuit 220 represent the input voltage of the motor drive circuit 100. Therefore, hereinafter, the output voltages of the 1st separation circuit 210 and the 2nd separation circuit 220 are referred to as the inverter input voltage V INV .

[0057] The MCU 300 is an arithmetic processing device that controls the motor drive circuit 100. The MCU 300 is, for example, a dual-core type MCU in which two processor cores are mounted. The MCU 300 has, in addition to the two processor cores, a nonvolatile memory such as a flash memory that stores programs and the like executed by the processor cores, a volatile memory such as a RAM (Random Access Memory), an input / output port, a communication port, and an internal bus that connects them to each other.

[0058] The MCU 300 has a CAN communication port that performs CAN (Controller Area Network) communication with the electronic control device 5 and an SPI communication port that performs SPI (Serial Peripheral Interface) communication with the PMIC 400 as communication ports. The CAN communication port of the MCU 300 is electrically connected to the electronic control device 5 via a CAN communication cable that is not shown. A motor control signal CS output from the electronic control device 5 is input to the MCU 300 via the CAN communication cable and the CAN communication port. The SPI communication port of the MCU 300 is electrically connected to the PMIC 400 via a 4-wire SPI communication bus 320.

[0059] The MCU 300 performs switching control of each switching element included in the motor drive circuit 100 in accordance with the motor control signal CS input from the electronic control device 5. Specifically, the MCU 300 generates a timing signal that indicates a switching timing of each switching element in accordance with a torque command value Tm* indicated by the motor control signal CS and outputs the timing signal from an output port to the multiplexer 800. The switching timing refers to a timing at which the state of each switching element is switched from an off state to an on state and a timing at which the state of each switching element is switched from the on state to the off state. The timing signal is, for example, a rectangular wave signal after pulse width modulation.

[0060] Specifically, the MCU 300 outputs a U-phase upper timing signal HPU that indicates a switching timing of the U-phase upper switching element Q UH to the multiplexer 800 and outputs a U-phase lower timing signal LPU that indicates a switching timing of the U-phase lower switching element Q UL to the multiplexer 800.

[0061] In addition, the MCU 300 outputs a V-phase upper timing signal HPV that indicates a switching timing of the V-phase upper switching element Q VH to the multiplexer 800 and outputs a V-phase lower timing signal LPV that indicates a switching timing of the V-phase lower switching element Q VL to the multiplexer 800.

[0062] Further, the MCU 300 outputs a W-phase upper timing signal HPW that indicates a switching timing of the W-phase upper switching element Q WH to the multiplexer 800 and outputs a W-phase lower timing signal LPW that indicates a switching timing of the W-phase lower switching element Q WL to the multiplexer 800.

[0063] The MCU 300 has an overvoltage detection port 310 electrically connected to the output terminal of the 1st separation circuit 210 as an input port. The MCU 300 compares the inverter input voltage V INV with the 1st threshold value V TH1 and executes a failsafe control when the inverter input voltage V INV exceeds the 1st threshold value V TH1 . The failsafe control refers to a control (ASC control) in which all the switching elements included in one of the upper arm 110 and the lower arm 120 are set to an on state and all the switching elements included in the other are set to an off state, or a control (SD control) in which all the switching elements included in both the upper arm 110 and the lower arm 120 are set to an off state, the details of which will be described later. In addition, the 1st threshold value V TH1 is digital data that is stored in advance in a nonvolatile memory of the MCU 300. In addition, the inverter input voltage V INV input via the overvoltage detection port 310 is converted into digital data by an AD converter built in the MCU 300.

[0064] The MCU 300 outputs the 1st error signal ER1 and the 2nd error signal ER2 to the PMIC 400 as signals that notify of an abnormality of the two processor cores. Specifically, the MCU 300 sets both the 1st error signal ER1 and the 2nd error signal ER2 to a high level when the two processor cores are in a normal state. On the other hand, the MCU 300 sets at least one of the 1st error signal ER1 and the 2nd error signal ER2 to a low level when at least one of the two processor cores is in an abnormal state.

[0065] The PMIC 400 performs power management of the MCU 300 and functions as a monitoring section that monitors the state of the MCU 300. The PMIC 400 is provided separately from the MCU 300. The PMIC 400 is communicably connected to the MCU 300 via an SPI communication bus 320. The PMIC 400 communicates with the MCU 300 via the SPI communication bus 320 to perform processing necessary for the power management of the MCU 300.

[0066] The PMIC 400 is electrically connected to the low-voltage battery 8 via a low-voltage positive terminal 43 and a low-voltage negative terminal 44. The PMIC 400 generates a power supply voltage necessary for the operation of the low-voltage system circuit based on a low direct-current voltage LV output from the low-voltage battery 8 and supplies it to the MCU 300, the replacement circuit 500, the 1st overvoltage detection circuit 610, the 2nd overvoltage detection circuit 620, the logic and circuit 700, and the multiplexer 800, and the like.

[0067] The PMIC 400 outputs the restart signal RST, the 1st abnormality detection signal FOT, and the 2nd abnormality detection signal IOT as signals that notify the MCU 300 of an abnormality to the logic and circuit 700. Specifically, when the MCU 300 is in a normal state, the PMIC 400 sets all of the restart signal RST, the 1st abnormality detection signal FOT, and the 2nd abnormality detection signal IOT to high levels.

[0068] When the MCU 300 is in an abnormal state, the PMIC 400 sets at least one of the restart signal RST, the 1st abnormality detection signal FOT, and the 2nd abnormality detection signal IOT to a low level. For example, when at least one of the 1st error signal ER1 and the 2nd error signal ER2 input from the MCU 300 is at a low level, the PMIC 400 sets the 1st abnormality detection signal FOT to a low level. Also, when an abnormality occurs that requires the MCU 300 to be restarted, the PMIC 400 sets the restart signal RST to a low level. Also, when another abnormality occurs in the MCU 300, the PMIC 400 sets the 2nd abnormality detection signal IOT to a low level.

[0069] The substitute circuit 500 is a circuit that substitutes for the MCU 300. The substitute circuit 500 has a 1st logic and circuit 510, a 2nd logic and circuit 520, a matrix circuit 530, a 1st switch 540, and a 2nd switch 550.

[0070] The 1st logic and circuit 510 is input with the fault signals FLT1, FLT2, and FLT3 output from the U-phase upper gate driver 111, the V-phase upper gate driver 112, and the W-phase upper gate driver 113. The 1st logic and circuit 510 operates a logical sum of the fault signals FLT1, FLT2, and FLT3, and outputs an upper arm fault signal FLTH that indicates the operation result to the matrix circuit 530.

[0071] The 1st logic and circuit 510 is a logical sum circuit of negative logic. Therefore, when at least one of the fault signals FLT1, FLT2, and FLT3 is at a low level, the upper arm fault signal FLTH at a low level is output from the 1st logic and circuit 510. When all of the fault signals FLT1, FLT2, and FLT3 are at high levels, the upper arm fault signal FLTH at a high level is output from the 1st logic and circuit 510. In other words, when at least one of the U-phase upper switch element Q UH , the V-phase upper switch element Q VH , and the W-phase upper switch element Q WHWhen at least one of them is in an abnormal state, a low-level upper arm fault signal FLTH is output from the first logic AND circuit 510. This occurs when the upper U-phase switching element Q is included in the upper arm 110. UH V-phase upper side switching element Q VH and the upper switch element Q of phase W WH When all conditions are normal, the upper arm fault signal FLTH is output as a high level from the first logic AND circuit 510.

[0072] The upper U-phase switching element Q included in the upper arm 110 will be described below. UH V-phase upper side switching element Q VH and the upper switch element Q of phase W WH The condition where at least one of the components is in an abnormal state is described as "the upper arm 110 is in an abnormal state". Additionally, the upper U-phase switching element Q included in the upper arm 110... UH V-phase upper side switching element Q VH and the upper switch element Q of phase W WH The condition where all operations are in normal condition is described as "upper arm 110 is in normal condition". That is, when the upper arm 110 is in an abnormal condition, a low-level upper arm fault signal FLTH is output from the first logic AND circuit 510. Conversely, when the upper arm 110 is in normal condition, a high-level upper arm fault signal FLTH is output from the first logic AND circuit 510.

[0073] The second logic AND circuit 520 receives fault signals FLT4 from the lower gate driver 121 of phase U, FLT5 from the lower gate driver 122 of phase V, and FLT6 from the lower gate driver 123 of phase W. The second logic AND circuit 520 performs a logical sum of the fault signals FLT4, FLT5, and FLT6, and outputs the lower arm fault signal FLTL, representing the result of the operation, to the matrix circuit 530.

[0074] The second logic AND circuit 520 is a negative logic AND circuit. Therefore, when at least one of the fault signals FLT4, FLT5, and FLT6 is low, a low-level lower arm fault signal FLTL is output from the second logic AND circuit 520. When all of the fault signals FLT4, FLT5, and FLT6 are high, a high-level lower arm fault signal FLTL is output from the second logic AND circuit 520. In other words, the lower U-phase switching element Q included in the lower arm 120... UL V-phase lower side switching element Q VL and the lower switch element Q of phase W WLthe U-phase lower-side switch element Q UL the V-phase lower-side switch element Q VL and the W-phase lower-side switch element Q WL all are in the normal state, the low-level lower-side arm fault signal FLTL is output from the second logic and circuit 520.

[0075] Hereinafter, the case where at least one of the U-phase lower-side switch element Q UL the V-phase lower-side switch element Q VL and the W-phase lower-side switch element Q WL is in the abnormal state is expressed as "the lower-side arm 120 is in the abnormal state". In addition, the case where all of the U-phase lower-side switch element Q UL the V-phase lower-side switch element Q VL and the W-phase lower-side switch element Q WL are in the normal state is expressed as "the lower-side arm 120 is in the normal state". That is, in the case where the lower-side arm 120 is in the abnormal state, the low-level lower-side arm fault signal FLTL is output from the second logic and circuit 520. In addition, in the case where the lower-side arm 120 is in the normal state, the high-level lower-side arm fault signal FLTL is output from the second logic and circuit 520.

[0076] The matrix circuit 530 outputs the first output signal OUT1 to the first switch 540 and outputs the second output signal OUT2 to the second switch 550 in accordance with the upper-side arm fault signal FLTH input from the first logic and circuit 510 and the lower-side arm fault signal FLTL input from the second logic and circuit 520.

[0077] In the case where both the upper-side arm fault signal FLTH and the lower-side arm fault signal FLTL are high-level, the matrix circuit 530 outputs the low-level first output signal OUT1 to the first switch 540 and outputs the high-level second output signal OUT2 to the second switch 550. In other words, in the case where both the upper-side arm 110 and the lower-side arm 120 are in the normal state, the matrix circuit 530 outputs the low-level first output signal OUT1 to the first switch 540 and outputs the high-level second output signal OUT2 to the second switch 550.

[0078] When the upper arm fault signal FLTH is at a low level and the lower arm fault signal FLTL is at a high level, the matrix circuit 530 outputs the first output signal OUT1 at a low level to the first switch 540 and outputs the second output signal OUT2 at a high level to the second switch 550. In other words, when the upper arm 110 among the upper arm 110 and the lower arm 120 is in an abnormal state, the matrix circuit 530 outputs the first output signal OUT1 at a low level to the first switch 540 and outputs the second output signal OUT2 at a high level to the second switch 550.

[0079] When the upper arm fault signal FLTH is at a high level and the lower arm fault signal FLTL is at a low level, the matrix circuit 530 outputs the first output signal OUT1 at a high level to the first switch 540 and outputs the second output signal OUT2 at a low level to the second switch 550. In other words, when the lower arm 120 among the upper arm 110 and the lower arm 120 is in an abnormal state, the matrix circuit 530 outputs the first output signal OUT1 at a high level to the first switch 540 and outputs the second output signal OUT2 at a low level to the second switch 550.

[0080] When both the upper arm fault signal FLTH and the lower arm fault signal FLTL are at a low level, the matrix circuit 530 outputs the first output signal OUT1 at a low level to the first switch 540 and outputs the second output signal OUT2 at a low level to the second switch 550. In other words, when both the upper arm 110 and the lower arm 120 are in an abnormal state, the matrix circuit 530 outputs the first output signal OUT1 at a low level to the first switch 540 and outputs the second output signal OUT2 at a low level to the second switch 550.

[0081] The first switch 540 has three contacts 541, 542, and 543. The contact 541 is electrically connected to a high-level voltage line 561. The high-level voltage VHi is supplied from the PMIC 400 to the high-level voltage line 561. The contact 542 is electrically connected to a low-level voltage line 562. The low-level voltage VLo is supplied from the PMIC 400 to the low-level voltage line 562. In other words, the low-level voltage line 562 is electrically connected to the low-voltage negative terminal 44 that is a ground terminal of the low-voltage system circuit.

[0082] The contact 543 is electrically connected to the multiplexer 800. Hereinafter, a signal outputted from the contact 543 to the multiplexer 800 is referred to as an upper arm control signal HG. When the first output signal OUT1 inputted from the matrix circuit 530 to the first switch 540 is at a low level, the contact 542 is electrically connected to the contact 543, whereby the upper arm control signal HG having a low level voltage VLo is outputted from the contact 543 to the multiplexer 800. Further, when the first output signal OUT1 inputted from the matrix circuit 530 to the first switch 540 is at a high level, the contact 541 is electrically connected to the contact 543, whereby the upper arm control signal HG having a high level voltage VHi is outputted from the contact 543 to the multiplexer 800.

[0083] The second switch 550 has three contacts 551, 552, and 553. The contact 551 is electrically connected to the high level voltage line 561. The contact 552 is electrically connected to the low level voltage line 562. The contact 553 is electrically connected to the multiplexer 800. Hereinafter, a signal outputted from the contact 553 to the multiplexer 800 is referred to as a lower arm control signal LG.

[0084] When the second output signal OUT2 inputted from the matrix circuit 530 to the second switch 550 is at a low level, the contact 552 is electrically connected to the contact 553, whereby the lower arm control signal LG having a low level voltage VLo is outputted from the contact 553 to the multiplexer 800. When the second output signal OUT2 inputted from the matrix circuit 530 to the second switch 550 is at a high level, the contact 551 is electrically connected to the contact 553, whereby the lower arm control signal LG having a high level voltage VHi is outputted from the contact 553 to the multiplexer 800.

[0085] As described above, when both the upper arm 110 and the lower arm 120 are in the normal state, the substitution circuit 500 outputs the upper arm control signal HG having the low level voltage VLo to the multiplexer 800, and outputs the lower arm control signal LG having the high level voltage VHi to the multiplexer 800.

[0086] Further, when the upper arm 110 of the upper arm 110 and the lower arm 120 is in the abnormal state, the substitution circuit 500 outputs the upper arm control signal HG having the low level voltage VLo to the multiplexer 800, and outputs the lower arm control signal LG having the high level voltage VHi to the multiplexer 800.

[0087] Further, when the lower arm 120 of the upper arm 110 and the lower arm 120 is in the abnormal state, the substitution circuit 500 outputs the upper arm control signal HG having the high level voltage VHi to the multiplexer 800, and outputs the lower arm control signal LG having the low level voltage VLo to the multiplexer 800.

[0088] Also, when both the upper side arm 110 and the lower side arm 120 are in the abnormal state, the substitute circuit 500 outputs the upper side arm control signal HG having the low-level voltage VLo to the multiplexer 800 and outputs the lower side arm control signal LG having the low-level voltage VLo to the multiplexer 800.

[0089] The 1st overvoltage detection circuit 610 outputs a 1st overvoltage detection signal DV1 to the logic and circuit 700, the state of which changes depending on the magnitude of the input voltage of the motor drive circuit 100, that is, the inverter input voltage V INV . Specifically, the 1st overvoltage detection circuit 610 compares the inverter input voltage V INV input from the 1st separation circuit 210 with a 2nd threshold value V TH1 higher than the 1st threshold value V TH2 , and changes the state of the 1st overvoltage detection signal DV1 from a 1st state to a 2nd state when the inverter input voltage V INV exceeds the 2nd threshold value V TH2 . In the present embodiment, the 1st state refers to a high level, and the 2nd state refers to a low level.

[0090] The 2nd overvoltage detection circuit 620 outputs a 2nd overvoltage detection signal DV2 to the logic and circuit 700, the state of which changes depending on the magnitude of the input voltage of the motor drive circuit 100, that is, the inverter input voltage V INV . Specifically, the 2nd overvoltage detection circuit 620 compares the inverter input voltage V INV input from the 2nd separation circuit 220 with a 3rd threshold value V TH2 higher than the 2nd threshold value V TH3 , and changes the state of the 2nd overvoltage detection signal DV2 from a 1st state to a 2nd state when the inverter input voltage V INV exceeds the 3rd threshold value V TH3 .

[0091] The 1st overvoltage detection circuit 610 and the 2nd overvoltage detection circuit 620 are each configured by an analog comparison circuit including a comparator. That is, the 2nd threshold value V TH2 and the 3rd threshold value V TH3 are not digital data stored in a nonvolatile memory like the 1st threshold value V TH1 , but are analog voltages generated by a resistance dividing circuit or the like, for example. In the 1st overvoltage detection circuit 610, the inverter input voltage V INV is an analog voltage, and the 2nd threshold value V TH2is input to the comparator, and the output signal of the comparator is output as the first overvoltage detection signal DV1 to the logic sum circuit 700. Similarly, in the second overvoltage detection circuit 620, the inverter input voltage V INV and the third threshold value V TH3 as an analog voltage is input to the comparator, and the output signal of the comparator is output as the second overvoltage detection signal DV2 to the logic sum circuit 700.

[0092] The first threshold value V TH1 , the second threshold value V TH2 , and the third threshold value V TH3 are determined in a range from 470 V as a rated voltage of the high-voltage battery 7 to 700 V as a withstand voltage of the motor drive circuit 100. The first threshold value V TH1 is a voltage value higher than 470 V and lower than the second threshold value V TH2 . The second threshold value V TH2 is a voltage value higher than the first threshold value V TH1 and lower than the third threshold value V TH3 . The third threshold value V TH3 is a voltage value higher than the second threshold value V TH2 and lower than 700 V.

[0093] The logic sum circuit 700 is a logic sum circuit of negative logic. The logic sum circuit 700 is input with the restart signal RST output from the PMIC 400, the first abnormality detection signal FOT and the second abnormality detection signal IOT, the first overvoltage detection signal DV1 output from the first overvoltage detection circuit 610, and the second overvoltage detection signal DV2 output from the second overvoltage detection circuit 620. The logic sum circuit 700 operates a logic sum of the restart signal RST, the first abnormality detection signal FOT, the second abnormality detection signal IOT, the first overvoltage detection signal DV1, and the second overvoltage detection signal DV2, and outputs a signal indicating the operation result as the mode switching signal MS to the multiplexer 800.

[0094] The mode switching signal MS of low level is output from the logic sum circuit 700 when at least one of the restart signal RST, the first abnormality detection signal FOT, the second abnormality detection signal IOT, the first overvoltage detection signal DV1, and the second overvoltage detection signal DV2 is low level. In addition, the mode switching signal MS of high level is output from the logic sum circuit 700 when all of the restart signal RST, the first abnormality detection signal FOT, the second abnormality detection signal IOT, the first overvoltage detection signal DV1, and the second overvoltage detection signal DV2 are high level.

[0095] That is, when all of the following conditions 1 to 3 are satisfied, the mode switching signal MS of high level is output from the logic and circuit 700.

[0096] (Condition 1) It is detected by the PMIC 400 that the MCU 300 is in a normal state.

[0097] (Condition 2) It is detected by the 1st overvoltage detection circuit 610 that the inverter input voltage V INV is the 2nd threshold value V TH2 or more.

[0098] (Condition 3) It is detected by the 2nd overvoltage detection circuit 620 that the inverter input voltage V INV is the 3rd threshold value V TH3 or more.

[0099] In addition, when at least one of the following conditions 4 to 6 is satisfied, the mode switching signal MS of low level is output from the logic and circuit 700.

[0100] (Condition 4) It is detected by the PMIC 400 that the MCU 300 is in an abnormal state.

[0101] (Condition 5) It is detected by the 1st overvoltage detection circuit 610 that the inverter input voltage V INV exceeds the 2nd threshold value V TH2 .

[0102] (Condition 6) It is detected by the 2nd overvoltage detection circuit 620 that the inverter input voltage V INV exceeds the 3rd threshold value V TH3 .

[0103] The mode switching signal MS output from the logic and circuit 700, the respective timing signals output from the MCU 300, and the upper arm control signal HG and the lower arm control signal LG output from the alternative circuit 500 are input to the multiplexer 800. As described above, the timing signals output from the MCU 300 include the U-phase upper timing signal HPU, the U-phase lower timing signal LPU, the V-phase upper timing signal HPV, the V-phase lower timing signal LPV, the W-phase upper timing signal HPW, and the W-phase lower timing signal LPW.

[0104] When the mode switching signal MS is high level, the multiplexer 800 outputs the U-phase upper timing signal HPU as the U-phase upper gate control signal UHG to the U-phase upper gate driver 111, outputs the V-phase upper timing signal HPV as the V-phase upper gate control signal VHG to the V-phase upper gate driver 112, and outputs the W-phase upper timing signal HPW as the W-phase upper gate control signal WHG to the W-phase upper gate driver 113.

[0105] In addition, when the mode switching signal MS is at the high level, the multiplexer 800 outputs the U-phase lower side timing signal LPU as the U-phase lower side gate control signal ULG to the U-phase lower side gate driver 121, outputs the V-phase lower side timing signal LPV as the V-phase lower side gate control signal VLG to the V-phase lower side gate driver 122, and outputs the W-phase lower side timing signal LPW as the W-phase lower side gate control signal WLG to the W-phase lower side gate driver 123.

[0106] When the mode switching signal MS is at the low level, the multiplexer 800 outputs the upper side arm control signal HG as the U-phase upper side gate control signal UHG to the U-phase upper side gate driver 111, outputs the upper side arm control signal HG as the V-phase upper side gate control signal VHG to the V-phase upper side gate driver 112, and outputs the upper side arm control signal HG as the W-phase upper side gate control signal WHG to the W-phase upper side gate driver 113.

[0107] In addition, when the mode switching signal MS is at the low level, the multiplexer 800 outputs the lower side arm control signal LG as the U-phase lower side gate control signal ULG to the U-phase lower side gate driver 121, outputs the lower side arm control signal LG as the V-phase lower side gate control signal VLG to the V-phase lower side gate driver 122, and outputs the lower side arm control signal LG as the W-phase lower side gate control signal WLG to the W-phase lower side gate driver 123.

[0108] As described above, when the mode switching signal MS is at the high level, the motor drive circuit 100 is controlled by the respective timing signals output from the MCU 300. Hereinafter, this state in which the motor drive circuit 100 is controlled by the MCU 300 will be referred to as a first control mode. In addition, when the mode switching signal MS is at the low level, the motor drive circuit 100 is controlled by the upper side arm control signal HG and the lower side arm control signal LG output from the alternative circuit 500. Hereinafter, this state in which the motor drive circuit 100 is controlled by the alternative circuit 500 will be referred to as a second control mode.

[0109] That is, the multiplexer 800 functions as a mode switching section, and switches the control mode between the first control mode in which the motor drive circuit 100 is controlled by the MCU 300 and the second control mode in which the motor drive circuit 100 is controlled by the alternative circuit 500, according to the state of the MCU 300, in other words, according to the state of the mode switching signal MS. When the mode switching signal MS changes from the high level to the low level, the multiplexer 800 switches the control mode from the first control mode to the second control mode. In the second control mode, the alternative circuit 500 controls the switching of the switching elements included in the upper arm 110 and the lower arm 120, according to the state of the upper arm 110 and the lower arm 120, the details of which will be described later. Specifically, the alternative circuit 500 performs one of control (ASC control) in which the switching elements included in one of the upper arm 110 and the lower arm 120 are all set to the on state and the switching elements included in the other are all set to the off state, or control (SD control) in which the switching elements included in both the upper arm 110 and the lower arm 120 are all set to the off state, according to the state of the upper arm 110 and the lower arm 120.

[0110] Next, the operation of the motor control device 40 configured as described above will be described.

[0111] First, the operation of the motor control device 40 at the time of normality will be described. The time of normality refers to when all of the following conditions 1 to 3 are satisfied.

[0112] (Condition 1) The MCU 300 is detected by the PMIC 400 to be in a normal state.

[0113] (Condition 2) The inverter input voltage V INV is the second threshold value V TH2 or more.

[0114] (Condition 3) The inverter input voltage V INV is the third threshold value V TH3 or more.

[0115] When condition 1 is satisfied, the restart signal RST, the 1st abnormality detection signal FOT, and the 2nd abnormality detection signal IOT output from the PMIC 400 to the logic sum circuit 700 are all high. When condition 2 is satisfied, the 1st overvoltage detection signal DV1 output from the 1st overvoltage detection circuit 610 to the logic sum circuit 700 is high. When condition 3 is satisfied, the 2nd overvoltage detection signal DV2 output from the 2nd overvoltage detection circuit 620 to the logic sum circuit 700 is high. Thus, when all of conditions 1 to 3 are satisfied, the mode switching signal MS is output from the logic sum circuit 700 to the multiplexer 800 at high. When the mode switching signal MS is high, the control mode of the motor control device 40 is the 1st control mode in which the motor drive circuit 100 is controlled by the MCU 300.

[0116] Figure 3 is a flowchart showing the motor control processing performed by the MCU 300 according to the program stored in the nonvolatile memory at ordinary times. In addition, the MCU 300 repeatedly performs the motor control processing shown in Figure 3 at a prescribed control cycle.

[0117] As shown in Figure 3 , first, the MCU 300 compares the inverter input voltage V INV input from the 1st isolation circuit 210 via the overvoltage detection port 310 with the 1st threshold value V TH1 , and determines whether the inverter input voltage V INV exceeds the 1st threshold value V TH1 (Step S1). Specifically, in Step S1, the MCU 300 compares the inverter input voltage V INV converted into digital data by the AD converter with the 1st threshold value V TH1 read from the nonvolatile memory, and thereby determines whether the inverter input voltage V INV exceeds the 1st threshold value V TH1 . As described above, the 1st threshold value V TH1 is higher than 470 V which is the rated voltage of the high-voltage battery 7 and lower than the 2nd threshold value V TH2 .

[0118] When the result in Step S1 is "No", that is, when the inverter input voltage V INV is not the 1st threshold value V TH1 , the MCU 300 proceeds to Step S2.The MCU 300 performs normal-time motor control in accordance with the motor control signal CS input from the electronic control device 5 in the following cases (Step S2). In the present embodiment, as the normal-time motor control, the MCU 300 performs vector control of the three-phase current supplied from the motor drive circuit 100 to the motor 10 in accordance with the torque command value Tm* indicated by the motor control signal CS input from the electronic control device 5, thereby rotating the motor 10 with a torque determined by the torque command value Tm*. Since the vector control is well known as a control method of the motor 10 belonging to the three-phase synchronous motor, the vector control will be described in the present embodiment with reference to FIG. 6. Figure 4 The vector control will be briefly described.

[0119] Figure 4 is a flowchart showing the vector control performed by the MCU 300 as the normal-time motor control in Step S2. As shown in Figure 4 , the MCU 300 acquires detection values of the three-phase current including the U-phase current Iu, the V-phase current Iv, and the W-phase current Iw from a current sensor such as a shunt resistor provided in the motor drive circuit 100 (Step S21).

[0120] Next, the MCU 300 calculates the two-phase currents Ia and Ib in the fixed coordinate system by performing Clark transformation on the detection values of the U-phase current Iu, the V-phase current Iv, and the W-phase current Iw (Step S22).

[0121] Next, the MCU 300 converts the two-phase currents Ia and Ib in the fixed coordinate system into the d-axis current Id and the q-axis current Iq in the rotating coordinate system by performing Park transformation based on Equations (1) and (2) (Step S23). In addition, the MCU 300 acquires the detection value of the rotation angle θm of the motor 10 from a position detection device such as a resolver attached to the motor 10 as "θm" in Equations (1) and (2). R R

[0122] Id = Ia cos θm + Ib sin θm … (1) R R Iq = -Ia sin θm + Ib cos θm … (2) R R

[0123] Id = Ia cos θm + Ib sin θm … (1) R R Iq = -Ia sin θm + Ib cos θm … (2) R R

[0124] Next, the MCU 300 determines the target d-axis current Id REF and the target q-axis current Iq REF in accordance with the torque command value Tm* (Step S24). The target d-axis current Id and the target q-axis current Iq corresponding to the torque command value Tm* are stored in advance in the nonvolatile memory of the MCU 300.REF and target q-axis current Iq REF The table data. In step S24, the MCU300 reads the target d-axis current Id corresponding to the torque command value Tm* represented by the motor control signal CS from the table data stored in the non-volatile memory. REF and target q-axis current Iq REF This determines the target d-axis current Id. REF and target q-axis current Iq REF .

[0125] Next, the MCU 300 uses PI calculation to calculate the d-axis current Id relative to the target d-axis current Id. REF The difference between the d-axis voltage Vd and the target q-axis current Iq is zero, and the PI calculation is used to calculate the q-axis current Iq that is equal to the target q-axis current Iq. REF The difference between the q-axis voltages is zero (step S25).

[0126] Next, the MCU 300 performs an inverse Parker transformation based on equations (3) and (4) to convert the d-axis voltage Vd and q-axis voltage Vq in the rotating coordinate system into two-phase voltages Vα and Vβ in the fixed coordinate system (step S26). The rotation angle θ obtained from a position detection device (not shown) such as a rotary transformer is used. R The detected value is used as "θ" in equations (3) and (4). R ".

[0127] Vα=Vd·cosθ R -Vq·sinθ R …(3)

[0128] Vβ=Vd·sinθ R +Vq·cosθ R …(4)

[0129] Next, the MCU 300 performs a space vector transformation to convert the two-phase voltage values ​​Vα and Vβ into three-phase voltages (step S27). The three-phase voltages include the U-phase voltage Vu, the V-phase voltage Vv, and the W-phase voltage Vw. Finally, the MCU 300 generates and outputs the three-phase voltages obtained through the space vector transformation to the motor 10, namely, the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, the W-phase upper timing signal HPW, the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW, and outputs them to the multiplexer 800 (step S28).

[0130] When the mode switching signal MS is high, the multiplexer 800 outputs the upper U-phase timing signal HPU input from the MCU 300 as the upper U-phase gate control signal UHG to the upper U-phase gate driver 111, outputs the upper V-phase timing signal HPV input from the MCU 300 as the upper V-phase gate control signal VHG to the upper V-phase gate driver 112, and outputs the upper W-phase timing signal HPW input from the MCU 300 as the upper W-phase gate control signal WHG to the upper W-phase gate driver 113.

[0131] Additionally, when the mode switching signal MS is high, the multiplexer 800 outputs the U-phase lower-side timing signal LPU input from the MCU 300 as the U-phase lower-side gate control signal ULG to the U-phase lower-side gate driver 121, outputs the V-phase lower-side timing signal LPV input from the MCU 300 as the V-phase lower-side gate control signal VLG to the V-phase lower-side gate driver 122, and outputs the W-phase lower-side timing signal LPW input from the MCU 300 as the W-phase lower-side gate control signal WLG to the W-phase lower-side gate driver 123.

[0132] As mentioned above, at the inverter input voltage V INV The first threshold V TH1 In the following cases, the MCU 300 performs vector control as normal motor control based on the motor control signal CS input from the electronic control unit 5, thereby controlling the switching elements included in the motor drive circuit 100 at appropriate times. As a result, by appropriately controlling the U-phase current Iu, V-phase current Iv, and W-phase current Iw supplied from the motor drive circuit 1100 to the motor 10, the motor 10 rotates with a torque determined by the torque command value Tm*, transmitting the driving force required by the driver from the motor unit 6 to the drive wheel 2.

[0133] Below, return to Figure 3 Let's continue with the explanation. When in Figure 3 If "yes" is selected in step S1, that is, when the inverter input voltage V... INV Exceeding the first threshold V TH1 In this case, there is a high probability that the motor drive circuit 100 has malfunctioned, and if the inverter input voltage V INV If the rise is too high, it will cause failure of switching components, etc. Therefore, the MCU 300 performs fault safety control based on the state of the upper arm 110 and the lower arm 120 (step S3).

[0134] First, in step S3, the MCU 300 determines whether the upper arm 110 and the lower arm 120 are in a normal state or an abnormal state. Specifically, in a case where the fault signal FLT1 input from the U-phase upper gate driver 111, the fault signal FLT2 input from the V-phase upper gate driver 112, and the fault signal FLT3 input from the W-phase upper gate driver 113 are all high, the MCU 300 determines that the upper arm 110 is in a normal state. In addition, in a case where at least one of the fault signals FLT1, FLT2, and FLT3 is low, the MCU 300 determines that the upper arm 110 is in an abnormal state.

[0135] In addition, in a case where the fault signal FLT4 input from the U-phase lower gate driver 121, the fault signal FLT5 input from the V-phase lower gate driver 122, and the fault signal FLT6 input from the W-phase lower gate driver 123 are all high, the MCU 300 determines that the lower arm 120 is in a normal state. In addition, in a case where at least one of the fault signals FLT4, FLT5, and FLT6 is low, the MCU 300 determines that the lower arm 120 is in an abnormal state.

[0136] Then, when it is determined that both the upper arm 110 and the lower arm 120 are in a normal state, the MCU 300 sets the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HPW all to low and outputs them to the multiplexer 800. Thereby, the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer 800 to the motor drive circuit 100 all become low.

[0137] In addition, when it is determined that both the upper arm 110 and the lower arm 120 are in a normal state, the MCU 300 sets the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW all to high and outputs them to the multiplexer 800. Thereby, the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer 800 to the motor drive circuit 100 all become high.

[0138] As a result, in a case where both the upper arm 110 and the lower arm 120 are in the normal state, all the switching elements included in the upper arm 110 are controlled to be in the off state, and all the switching elements included in the lower arm 120 are controlled to be in the on state. In other words, when it is determined that both the upper arm 110 and the lower arm 120 are in the normal state, the MCU 300 performs the ASC control that controls all the switching elements included in the upper arm 110 to be in the off state and controls all the switching elements included in the lower arm 120 to be in the on state. Thereby, the current flowing in all the switching elements included in the upper arm 110 is cut off, and the counter electromotive force generated by the motor 10 continues to flow in the closed circuit composed of the lower arm 120. Thereby, it is possible to prevent the switching elements, the high-voltage battery 7 from being damaged. INV Further, the motor 10 further accelerates, and it is possible to prevent the switching elements, the high-voltage battery 7 from being damaged.

[0139] When it is determined that the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, the MCU 300 sets all the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HPW to the low level and outputs them to the multiplexer 800. Thereby, all the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer 800 to the motor drive circuit 100 become the low level.

[0140] In addition, when it is determined that the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, the MCU 300 sets all the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW to the high level and outputs them to the multiplexer 800. Thereby, all the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer 800 to the motor drive circuit 100 become the high level.

[0141] As a result, in a case where the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, all the switching elements included in the upper arm 110 are controlled to be in the off state, and all the switching elements included in the lower arm 120 are controlled to be in the on state. In other words, when it is determined that the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, the MCU 300 performs the ASC control that controls all the switching elements included in the upper arm 110 to be in the off state and controls all the switching elements included in the lower arm 120 to be in the on state. Thereby, the current flowing in all the switching elements included in the upper arm 110 is cut off, and the counter electromotive force generated by the motor 10 continues to flow in the closed circuit composed of the lower arm 120. Thereby, it is possible to prevent the switching elements, the high-voltage battery 7 from being damaged.INV Further rise, motor 10 further acceleration, can prevent the switch element, high voltage battery 7 damage.

[0142] When it is determined that the lower side arm 120 among the upper side arm 110 and the lower side arm 120 is in an abnormal state, the MCU 300 sets all of the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HPW to high levels and outputs them to the multiplexer 800. Thereby, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer 800 to the motor drive circuit 100 become high levels.

[0143] In addition, when it is determined that the lower side arm 120 among the upper side arm 110 and the lower side arm 120 is in an abnormal state, the MCU 300 sets all of the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW to low levels and outputs them to the multiplexer 800. Thereby, all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer 800 to the motor drive circuit 100 become low levels.

[0144] As a result, in a case where the lower side arm 120 among the upper side arm 110 and the lower side arm 120 is in an abnormal state, all of the switch elements included in the upper side arm 110 are controlled to be in an on state, and all of the switch elements included in the lower side arm 120 are controlled to be in an off state. In other words, when it is determined that the lower side arm 120 among the upper side arm 110 and the lower side arm 120 is in an abnormal state, the MCU 300 performs ASC control that controls all of the switch elements included in the upper side arm 110 to be in an on state and controls all of the switch elements included in the lower side arm 120 to be in an off state. Thereby, the current flowing in all of the switch elements included in the lower side arm 120 is cut off, and the back electromotive force generated by the motor 10 continues to flow in the closed circuit constituted by the upper side arm 110. Thereby, it is possible to prevent the inverter input voltage Vinv from rising further, and it is possible to prevent the switch elements and the high voltage battery 7 from being damaged. INV Further rise, motor 10 further acceleration, thereby it is possible to prevent the switch element, high voltage battery 7 damage.

[0145] When it is determined that both of the upper side arm 110 and the lower side arm 120 are in an abnormal state, the MCU 300 sets all of the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HPW to low levels and outputs them to the multiplexer 800. Thereby, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer 800 to the motor drive circuit 100 become low levels.

[0146] In addition, when it is determined that both the upper arm 110 and the lower arm 120 are in the abnormal state, the MCU 300 sets all of the U-phase lower side timing signal LPU, the V-phase lower side timing signal LPV, and the W-phase lower side timing signal LPW to the low level and outputs them to the multiplexer 800. Thereby, all of the U-phase lower side gate control signal ULG, the V-phase lower side gate control signal VLG, and the W-phase lower side gate control signal WLG, which are output from the multiplexer 800 to the motor drive circuit 100, become the low level.

[0147] As a result, in a case where both the upper arm 110 and the lower arm 120 are in the abnormal state, all of the switching elements included in the upper arm 110 are controlled to the off state, and all of the switching elements included in the lower arm 120 are controlled to the off state. In other words, when it is determined that both the upper arm 110 and the lower arm 120 are in the abnormal state, the MCU 300 performs the SD control of controlling all of the switching elements included in the upper arm 110 to the off state and controlling all of the switching elements included in the lower arm 120 to the off state. Thereby, the counter electromotive voltage generated by the rotation of the motor 10 flows to the high-voltage battery 7 via the freewheeling diodes of the switching elements, and thus the switching elements can be protected.

[0148] The above is a description of the operation of the motor control device 40 at the time of normality. Next, the operation of the motor control device 40 at the time of abnormality will be described. The time of abnormality refers to when at least one of the following conditions 4 to 6 is satisfied.

[0149] (Condition 4) The MCU 300 is detected by the PMIC 400 to be in an abnormal state.

[0150] (Condition 5) The inverter input voltage V INV exceeds the second threshold value V TH2 .

[0151] (Condition 6) The inverter input voltage V INV exceeds the third threshold value V TH3 .

[0152] When the condition 4 is satisfied, at least one of the restart signal RST, the first abnormality detection signal FOT, and the second abnormality detection signal IOT output from the PMIC 400 to the logic sum circuit 700 is at the low level. When the condition 5 is satisfied, the first overvoltage detection signal DV1 output from the first overvoltage detection circuit 610 to the logic sum circuit 700 is at the low level. When the condition 6 is satisfied, the second overvoltage detection signal DV2 output from the second overvoltage detection circuit 620 to the logic sum circuit 700 is at the low level. Thus, when at least one of the conditions 4 to 6 is satisfied, the mode switching signal MS is output at the low level from the logic sum circuit 700 to the multiplexer 800. When the mode switching signal MS is at the low level, the control mode of the motor control device 40 is the second control mode in which the motor drive circuit 100 is controlled by the alternative circuit 500.

[0153] In the second control mode, the alternative circuit 500 performs the fail-safe control in accordance with the states of the upper arm 110 and the lower arm 120. As described above, when both the upper arm 110 and the lower arm 120 are in the normal state, the alternative circuit 500 outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer 800 and outputs the lower arm control signal LG having the high-level voltage VHi to the multiplexer 800.

[0154] When the mode switching signal MS is at the low level, the multiplexer 800 outputs the upper arm control signal HG as the U-phase upper gate control signal UHG to the U-phase upper gate driver 111, outputs the upper arm control signal HG as the V-phase upper gate control signal VHG to the V-phase upper gate driver 112, and outputs the upper arm control signal HG as the W-phase upper gate control signal WHG to the W-phase upper gate driver 113.

[0155] In addition, when the mode switching signal MS is at the low level, the multiplexer 800 outputs the lower arm control signal LG as the U-phase lower gate control signal ULG to the U-phase lower gate driver 121, outputs the lower arm control signal LG as the V-phase lower gate control signal VLG to the V-phase lower gate driver 122, and outputs the lower arm control signal LG as the W-phase lower gate control signal WLG to the W-phase lower gate driver 123.

[0156] Thus, when both the upper arm 110 and the lower arm 120 are in the normal state, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer 800 to the motor drive circuit 100 become at the low level, and all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer 800 to the motor drive circuit 100 become at the high level.

[0157] As a result, in the case where both the upper arm 110 and the lower arm 120 are in the normal state, all the switching elements included in the upper arm 110 are controlled to be in the off state, and all the switching elements included in the lower arm 120 are controlled to be in the on state. In other words, when both the upper arm 110 and the lower arm 120 are in the normal state, the alternative circuit 500 performs the ASC control of controlling all the switching elements included in the upper arm 110 to be in the off state and controlling all the switching elements included in the lower arm 120 to be in the on state. Thereby, the current flowing in all the switching elements included in the upper arm 110 is cut off, and the counter electromotive voltage generated by the motor 10 is freewheeling in the closed circuit composed of the lower arm 120. Thereby, it is possible to prevent the inverter input voltage V INV Further rise, the motor 10 further accelerates, it is possible to prevent the switching element, the high voltage battery 7 damage.

[0158] When the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, the alternative circuit 500 outputs the upper arm control signal HG having the low level voltage VLo to the multiplexer 800, and outputs the lower arm control signal LG having the high level voltage VHi to the multiplexer 800. Thereby, the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG outputted from the multiplexer 800 to the motor drive circuit 100 all become low level, and the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG outputted from the multiplexer 800 to the motor drive circuit 100 all become high level.

[0159] As a result, in the case where the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, all the switching elements included in the upper arm 110 are controlled to be in the off state, and all the switching elements included in the lower arm 120 are controlled to be in the on state. In other words, when the upper arm 110 among the upper arm 110 and the lower arm 120 is in the abnormal state, the alternative circuit 500 performs the ASC control of controlling all the switching elements included in the upper arm 110 to be in the off state and controlling all the switching elements included in the lower arm 120 to be in the on state. Thereby, the current flowing in all the switching elements included in the upper arm 110 is cut off, and the counter electromotive voltage generated by the motor 10 is freewheeling in the closed circuit composed of the lower arm 120. Thereby, it is possible to prevent the inverter input voltage V INV Further rise, the motor 10 further accelerates, it is possible to prevent the switching element, the high voltage battery 7 damage.

[0160] When the upper arm 110 and the lower arm 120 among the lower arm 120 are in the abnormal state, the substitution circuit 500 outputs the upper arm control signal HG having the high-level voltage VHi to the multiplexer 800, and outputs the lower arm control signal LG having the low-level voltage VLo to the multiplexer 800. Thereby, the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG outputted from the multiplexer 800 to the motor drive circuit 100 all become high-level, and the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG outputted from the multiplexer 800 to the motor drive circuit 100 all become low-level.

[0161] As a result, in the case where the upper arm 110 and the lower arm 120 among the lower arm 120 are in the abnormal state, all of the switching elements included in the upper arm 110 are controlled to be in the on state, and all of the switching elements included in the lower arm 120 are controlled to be in the off state. In other words, when the upper arm 110 and the lower arm 120 among the lower arm 120 are in the abnormal state, the substitution circuit 500 performs the ASC control that controls all of the switching elements included in the upper arm 110 to be in the on state and controls all of the switching elements included in the lower arm 120 to be in the off state. Thereby, the current flowing in all of the switching elements included in the lower arm 120 is cut off, and the back electromotive force generated by the motor 10 continues to flow in the closed circuit constituted by the upper arm 110. Thereby, it is possible to prevent the switching elements, the high-voltage battery 7 from being damaged. INV Further, the motor 10 further accelerates, and it is possible to prevent the switching elements, the high-voltage battery 7 from being damaged.

[0162] When both of the upper arm 110 and the lower arm 120 are in the abnormal state, the substitution circuit 500 outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer 800, and outputs the lower arm control signal LG having the low-level voltage VLo to the multiplexer 800. Thereby, the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG outputted from the multiplexer 800 to the motor drive circuit 100 all become low-level, and the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG outputted from the multiplexer 800 to the motor drive circuit 100 all become low-level.

[0163] As a result, in a case where both the upper arm 110 and the lower arm 120 are in the abnormal state, all of the switching elements included in the upper arm 110 are controlled to be in the off state, and all of the switching elements included in the lower arm 120 are controlled to be in the off state. In other words, when both the upper arm 110 and the lower arm 120 are in the abnormal state, the substitution circuit 500 performs the SD control that controls all of the switching elements included in the upper arm 110 to be in the off state and controls all of the switching elements included in the lower arm 120 to be in the off state. Thus, the counter electromotive voltage generated by the rotation of the motor 10 flows to the high-voltage battery 7 via the freewheeling diodes of the switching elements, so it is possible to protect the switching elements.

[0164] As described above, the motor control device 40 of the present embodiment has the motor drive circuit 100 having the upper arm 110 and the lower arm 120, the MCU 300 that controls the motor drive circuit 100, the substitution circuit 500 that substitutes for the MCU 300, and the multiplexer 800 that switches the control mode between the first control mode and the second control mode in accordance with the state of the MCU 300. When the state of the MCU 300 changes from the normal state to the abnormal state, the multiplexer 800 switches the control mode from the first control mode to the second control mode. In the second control mode, the substitution circuit 500 performs the fail-safe control in accordance with the states of the upper arm 110 and the lower arm 120.

[0165] According to such the present embodiment, it is possible to perform the fail-safe control based on the substitution circuit 500 when the MCU 300 has an abnormality. In addition, it is possible to perform appropriate fail-safe control based on the states of the upper arm 110 and the lower arm 120.

[0166] The motor control device 40 of the present embodiment further has a monitoring section (PMIC 400) that monitors the state of the MCU 300. When the monitoring section detects that the state of the MCU 300 changes from the normal state to the abnormal state, the multiplexer 800 switches the control mode from the first control mode to the second control mode.

[0167] In a control device that uses an arithmetic processing device such as the MCU 300, a monitoring circuit that monitors the state of the arithmetic processing device is generally provided, so if the existing monitoring circuit is used as the monitoring section of the present application, it is not necessary to add a new monitoring section component, and the present application can be implemented at low cost.

[0168] In the present embodiment, the monitoring section (PMIC 400) is provided separately from the MCU 300. Thus, even if the MCU 300 as the arithmetic processing device has an abnormality, it is possible to prevent the monitoring section from being affected by the abnormality.

[0169] In this embodiment, the monitoring unit is the PMIC 400 that performs power management of the MCU 300.

[0170] By using the PMIC 400, which is the power management IC of the MCU 300, as the monitoring unit, the present invention can be implemented at low cost without the need to set up new circuits corresponding to the monitoring unit.

[0171] The motor control device 40 of this embodiment also includes a first overvoltage detection circuit 610 that outputs a first overvoltage detection signal DV1. The state of the first overvoltage detection signal DV1 depends on the input voltage of the motor drive circuit 100 (inverter input voltage V). INV The value varies depending on the magnitude of the inverter input voltage V. The MCU 300 will display the inverter input voltage V. INV With the first threshold V TH1 Comparison at inverter input voltage V INV Exceeding the first threshold V TH1 Fault safety control is performed in a timely manner. The first overvoltage detection circuit 610 detects the inverter input voltage V. INV Compared to the first threshold V TH1 The high second threshold V TH2 Comparison at inverter input voltage V INV Exceeding the second threshold V TH2 When the first overvoltage detection signal DV1 changes from high to low, the multiplexer 800 also switches the control mode from the first control mode to the second control mode.

[0172] As is normally the case, when an overvoltage exceeding the first threshold occurs, the MCU 300 performs fault-safe control to suppress the rise in the inverter input voltage. However, in the event of a larger overvoltage exceeding the second threshold, the fault-safe control based on the MCU 300 may not function accurately. In such cases, the system switches to a second control mode, and the alternative circuit 500 performs fault-safe control, thus enabling fault-safe control to continue regardless of the state of the MCU 300. Furthermore, even when using the alternative circuit 500, appropriate fault-safe control based on the states of the upper arm 110 and the lower arm 120 can be performed.

[0173] The motor control device 40 of this embodiment also includes a second overvoltage detection circuit 620 that outputs a second overvoltage detection signal DV2. The state of the second overvoltage detection signal DV2 depends on the input voltage of the motor drive circuit 100 (inverter input voltage V). INV The voltage varies depending on the magnitude of the inverter input voltage V. The second overvoltage detection circuit 620 detects the inverter input voltage V. INV Compared with the second threshold VTH2 High 3rd threshold value V TH3 Comparison is made, at the time when the inverter input voltage V INV Exceeds the 3rd threshold value V TH3 The state of the 2nd overvoltage detection signal DV2 is changed from high level to low level. When at least one of the 1st overvoltage detection signal DV1 and the 2nd overvoltage detection signal DV2 is changed from high level to low level, the multiplexer 800 switches the control mode from the 1st control mode to the 2nd control mode.

[0174] Generally, at the time when the 1st threshold value or the 2nd threshold value is detected, the inverter input voltage is suppressed by the fail-safe control based on the MCU 300 or the 1st overvoltage detection circuit 610, but in the case where a larger overvoltage exceeding the 3rd threshold value is generated, the fail-safe control based on the MCU 300 or the 1st overvoltage detection circuit 610 can not function accurately, and in such a case, the fail-safe control is performed by the alternative circuit 500 in the 2nd control mode, whereby the fail-safe control can be continued regardless of the state of the MCU 300 or the 1st overvoltage detection circuit 610. That is, compared with the case where only the 1st overvoltage detection circuit 610 is provided, in the case where the 2nd overvoltage detection circuit 620 is further provided, the possibility of performing the fail-safe control is high, and the safety is improved. In addition, even in the case of using the alternative circuit 500, appropriate fail-safe control based on the state of the upper arm 110 and the lower arm 120 can be performed.

[0175] In the present embodiment, in the case where both the upper arm 110 and the lower arm 120 are in the normal state, the alternative circuit 500 controls all the switching elements included in the upper arm 110 to the off state, and controls all the switching elements included in the lower arm 120 to the on state.

[0176] Thus, in the case where both the upper arm 110 and the lower arm 120 are in the normal state, appropriate fail-safe control can be performed by the alternative circuit 500.

[0177] In the present embodiment, in the case where the upper arm 110 of the upper arm 110 and the lower arm 120 is in the abnormal state, the alternative circuit 500 controls all the switching elements included in the upper arm 110 to the off state, and controls all the switching elements included in the lower arm 120 to the on state.

[0178] Thus, in the case where the upper arm 110 of the upper arm 110 and the lower arm 120 is in the abnormal state, appropriate fail-safe control can be performed by the alternative circuit 500.

[0179] In the present embodiment, in a case where the lower side arm 120 among the upper side arm 110 and the lower side arm 120 is in an abnormal state, the substitution circuit 500 controls all the switching elements included in the upper side arm 110 to be in an on state, and controls all the switching elements included in the lower side arm 120 to be in an off state.

[0180] Thus, in a case where the lower side arm 120 among the upper side arm 110 and the lower side arm 120 is in an abnormal state, appropriate fail-safe control can be performed by the substitution circuit 500.

[0181] In the present embodiment, in a case where both the upper side arm 110 and the lower side arm 120 are in an abnormal state, the substitution circuit 500 controls all the switching elements included in the upper side arm 110 to be in an off state, and controls all the switching elements included in the lower side arm 120 to be in an off state.

[0182] Thus, in a case where both the upper side arm 110 and the lower side arm 120 are in an abnormal state, appropriate fail-safe control can be performed by the substitution circuit 500.

[0183] In the present embodiment, the substitution circuit 500 judges whether the upper side arm 110 and the lower side arm 120 are in a normal state or in an abnormal state, based on abnormality detection signals (fault signals) output from the gate drivers of the motor drive circuit 100.

[0184] Thus, whether the upper side arm 110 and the lower side arm 120 are in a normal state or in an abnormal state can be judged more accurately than in a case where no fault signal of the gate driver is used.

[0185] (Variants)

[0186] The present application is not limited to the above-described embodiments, and each structure described in the present specification can be appropriately combined within a range not contradicting each other.

[0187] For example, in the above-described embodiments, a case where the PMIC 400 as a monitoring section is provided separately from the MCU 300 as an arithmetic processing device is exemplified, but the present application is not limited thereto, and the monitoring section can be provided to the arithmetic processing device, or both an arithmetic processing device including a monitoring section and a monitoring section provided separately from the arithmetic processing device can be provided.

[0188] In addition, in a case where the monitoring section is arranged inside the arithmetic processing device, a signal output from the arithmetic processing device to notify an abnormality can be used as a trigger to make the mode switching section (multiplexer 800) operate, thereby switching the control mode.

[0189] Also, in the above embodiment, the PMIC 400 is exemplified as the monitoring section provided separately from the operation processing device, but the present application is not limited to this, and any electronic device having a function of monitoring the state of the operation processing device can be used as the monitoring section.

[0190] In the above embodiment, the motor unit 6 that applies driving force to the driving wheel 2 of the vehicle 1 as an electric automobile is exemplified as the motor unit having the motor control device 40, but the present application is not limited to this, and the motor control device of the present application can be provided in other motor units.

[0191] Also, in the above embodiment, the case where the motor unit 6 having the motor control device 40 is mounted on the vehicle 1 as an electric automobile is exemplified, but the motor unit of the present application can be applied to a vehicle other than an electric automobile, or a device that requires the rotational force of a motor, and the like.

[0192] In the above embodiment, the motor unit 6 having the motor drive circuit 100 and one motor 10, and the motor drive circuit 100 having a total of six switching elements of the upper arm and the lower arm are exemplified as the structure, but the present application is not limited to this. The following structure can also be adopted: the motor unit 6 has a motor for a generator in addition to the motor 10, and the motor drive circuit 100 has six switching elements for driving the motor for a generator in addition to the six switching elements for driving the motor 10. Also, a structure in which the switching elements for driving the motor for a generator can also be subjected to the fail-safe control of the present application can also be adopted.

[0193] In the above embodiment, the structure in which the fail-safe control is started when the overvoltage of the inverter input voltage is detected for the operation of the motor control device 40 when the MCU 300 is normal is exemplified, but the present application is not limited to this. The following structure can also be adopted: a rotational speed detection section that detects the rotational speed of the motor 10 is provided, and the fail-safe control is started when the rotational speed detection section detects the rotational speed exceeding an arbitrary threshold value.

[0194] In the above embodiment, the structure in which the mode switching signal MS outputting a low level is output to the multiplexer 800 when the overvoltage of the inverter input voltage or the abnormality of the MCU 300 is detected, whereby the control mode is switched from the first control mode to the second control mode to perform the fail-safe control is exemplified for the operation of the motor control device 40 when the abnormality of the MCU 300 occurs, but the present application is not limited to this. The following structure can also be adopted: a rotational speed detection section that detects the rotational speed of the motor 10 is provided, and the mode switching signal MS outputting a low level is output to the multiplexer 800 when the rotational speed detection section detects the rotational speed exceeding an arbitrary threshold value, whereby the control mode is switched from the first control mode to the second control mode to perform the fail-safe control.

[0195] In the above-described embodiments, a configuration in which the motor unit 6 inputs power to the motor drive circuit 100 without boosting or reducing the voltage of the high-voltage battery 7 is exemplified, but the present application is not limited to this. The motor unit 6 can also have a DC-DC converter that boosts or reduces the voltage of the high-voltage battery 7.

[0196] In the above-described embodiments, a configuration in which the inverter input voltage after the fail-safe control, the rotation speed of the motor 10, and the state of the MCU 300, and the like are detected can also be employed. For example, a configuration in which, after the fail-safe control, in a case where the inverter device changes from a state in which safety is low to a state in which safety is high, for example, in a case where it is detected that the inverter input voltage or the rotation speed of the motor 10 returns to a prescribed threshold value or less or the MCU 300 recovers from an abnormal state to a normal state, even if the rotation of the motor 10 is not stopped, the fail-safe control is ended and the switch control at the time of normality is returned to can be employed.

[0197] In the above-described embodiments, a configuration in which the gate control signal output from the multiplexer 800 is monitored and a short-circuit state of the motor drive circuit 100 is prevented can also be employed. For example, in a case where both the U-phase upper gate control signal UHG and the U-phase lower gate control signal ULG are high, both the U-phase upper side switching element Q UH and the U-phase lower side switching element Q UH become an on state and the motor drive circuit 100 is short-circuited. A configuration in which, in a case where it is detected that the gate control signal is output with a high level to both the upper and lower side arms in the same phase like this, the supply of the gate control signal to the motor drive circuit 100 is stopped or all of the switching elements are set to be off can be employed.

[0198] In the above-described embodiments, the logic AND circuit 700, the first logic AND circuit 510, and the second logic AND circuit 520 are all negative-logic logic AND circuits, but positive-logic logic AND circuits can also be used. Also, the logic of each signal can be reversed, and, for example, the following actions can also be performed. In a case where at least one high-level signal is input to the positive-logic logic AND circuit 700, the high-level mode switching signal MS is output to the multiplexer 800, thereby switching from the first control mode to the second control mode. In a case where an abnormality occurs in the switching element included in the upper arm 110, at least one of the three upper arm gate drivers outputs the high-level FLT signal to the first logic AND circuit 510, which is a positive-logic logic AND circuit. The first logic AND circuit 510 outputs the high-level upper arm fault signal FLTH to the matrix circuit 530. The matrix circuit 530 outputs the high-level first output signal OUT1 to the first switch 540. In the first switch 540, the contact 541 and the contact 543 are electrically connected, thereby outputting the upper arm control signal HG having the high-level voltage VHi from the contact 543 to the multiplexer 800. The multiplexer 800 sets the U-phase upper arm gate control signal UHG, the V-phase upper arm gate control signal VHG, and the W-phase upper arm gate control signal WHG all to high levels and outputs them to the three upper arm gate drivers.

Claims

1. A motor control device having: a motor drive circuit having an upper arm and a lower arm; an arithmetic processing device that controls the motor drive circuit; a substitute circuit that substitutes for the arithmetic processing device; and a mode switching section that switches a control mode between a first control mode in which the motor drive circuit is controlled by the arithmetic processing device and a second control mode in which the motor drive circuit is controlled by the substitute circuit, according to a state of the arithmetic processing device, the mode switching section switching the control mode from the first control mode to the second control mode when the state of the arithmetic processing device changes from a normal state to an abnormal state, the substitute circuit controlling switching of switching elements included in the upper arm and the lower arm according to states of the upper arm and the lower arm in the second control mode.

2. The motor control device according to claim 1, wherein the motor control device further has a monitoring section that monitors the state of the arithmetic processing device, the mode switching section switching the control mode from the first control mode to the second control mode when the monitoring section detects that the state of the arithmetic processing device changes from the normal state to the abnormal state.

3. The motor control device according to claim 2, wherein the monitoring section is provided separately from the arithmetic processing device.

4. The motor control device according to claim 2 or 3, wherein the monitoring section is a power management integrated circuit that performs power management of the arithmetic processing device.

5. The motor control device according to any one of claims 1 to 3, wherein the motor control device further has a first overvoltage detection circuit that outputs a first overvoltage detection signal whose state changes according to a magnitude of an input voltage of the motor drive circuit, the arithmetic processing device compares the input voltage of the motor drive circuit with a first threshold value, and performs fail-safe control when the input voltage exceeds the first threshold value, the first overvoltage detection circuit compares the input voltage of the motor drive circuit with a second threshold value that is higher than the first threshold value, and changes the state of the first overvoltage detection signal from a first state to a second state when the input voltage exceeds the second threshold value, and the mode switching section also switches the control mode from the first control mode to the second control mode when the state of the first overvoltage detection signal changes from the first state to the second state.

6. The motor control device according to claim 5, wherein the motor control device further has a second overvoltage detection circuit that outputs a second overvoltage detection signal whose state changes according to a magnitude of an input voltage of the motor drive circuit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ the second overvoltage detection circuit compares the input voltage of the motor drive circuit with a third threshold value higher than the second threshold value, and changes the state of the second overvoltage detection signal from a first state to a second state when the input voltage exceeds the third threshold value, the mode switching section switches the control mode from the first control mode to the second control mode when the state of at least one of the first overvoltage detection signal and the second overvoltage detection signal changes from the first state to the second state.

7. A motor control device, comprising: a motor drive circuit having an upper arm and a lower arm; an arithmetic processing device that controls the motor drive circuit; a substitute circuit that substitutes for the arithmetic processing device; a first overvoltage detection circuit that outputs a first overvoltage detection signal whose state changes according to the magnitude of the input voltage of the motor drive circuit; and a mode switching section that switches the control mode between a first control mode in which the motor drive circuit is controlled by the arithmetic processing device and a second control mode in which the motor drive circuit is controlled by the substitute circuit according to the state of the first overvoltage detection signal, the arithmetic processing device compares the input voltage of the motor drive circuit with a first threshold value, and executes fail-safe control when the input voltage exceeds the first threshold value, the first overvoltage detection circuit compares the input voltage of the motor drive circuit with a second threshold value higher than the first threshold value, and changes the state of the first overvoltage detection signal from a first state to a second state when the input voltage exceeds the second threshold value, the mode switching section switches the control mode from the first control mode to the second control mode when the state of the first overvoltage detection signal changes from the first state to the second state, in the second control mode, the substitute circuit controls the switching of switching elements included in the upper arm and the lower arm according to the states of the upper arm and the lower arm.

8. The motor control device according to claim 7, wherein the motor control device further comprises a second overvoltage detection circuit that outputs a second overvoltage detection signal whose state changes according to the magnitude of the input voltage of the motor drive circuit, the second overvoltage detection circuit compares the input voltage of the motor drive circuit with a third threshold value higher than the second threshold value, and changes the state of the second overvoltage detection signal from a first state to a second state when the input voltage exceeds the third threshold value, the mode switching section switches the control mode from the first control mode to the second control mode when the state of at least one of the first overvoltage detection signal and the second overvoltage detection signal changes from the first state to the second state.

9. The motor control device according to claim 7 or 8, wherein The mode switching section switches the control mode from the first control mode to the second control mode when the state of the arithmetic processing device changes from the normal state to the abnormal state.

10. The motor control device according to claim 9, wherein The motor control device further has a monitoring section that monitors the state of the arithmetic processing device, The mode switching section switches the control mode from the first control mode to the second control mode when the monitoring section detects that the state of the arithmetic processing device changes from the normal state to the abnormal state.

11. The motor control device according to claim 10, wherein The monitoring section is provided separately from the arithmetic processing device.

12. The motor control device according to claim 10 or 11, wherein The monitoring section is a power management integrated circuit that performs power management of the arithmetic processing device.

13. The motor control device according to claim 1 or 7, wherein The substitution circuit controls all of the switching elements included in the upper side arm to the off state and controls all of the switching elements included in the lower side arm to the on state when both the upper side arm and the lower side arm are in the normal state.

14. The motor control device according to claim 1 or 7, wherein The substitution circuit controls all of the switching elements included in the upper side arm to the off state and controls all of the switching elements included in the lower side arm to the on state when the upper side arm of the upper side arm and the lower side arm is in the abnormal state.

15. The motor control device according to claim 1 or 7, wherein The substitution circuit controls all of the switching elements included in the upper side arm to the on state and controls all of the switching elements included in the lower side arm to the off state when the lower side arm of the upper side arm and the lower side arm is in the abnormal state.

16. The motor control device according to claim 1 or 7, wherein The substitution circuit controls all of the switching elements included in the upper side arm to the off state and controls all of the switching elements included in the lower side arm to the off state when both the upper side arm and the lower side arm are in the abnormal state.

17. The motor control device according to claim 13, wherein The substitution circuit judges whether the upper side arm and the lower side arm are in the normal state or in the abnormal state based on an abnormality detection signal output from a gate driver of the motor drive circuit.

18. A motor unit having: a motor; and the motor control device according to any one of claims 1 to 17 that controls the motor.

19. A vehicle having the motor unit according to claim 18.

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