Method for manufacturing piezoelectric substrate, piezoelectric substrate, and acoustic wave device

Abstract

The present application relates to the technical field of acoustic wave device, and particularly relates to a preparation method of piezoelectric substrate, piezoelectric substrate and acoustic wave device. The method comprises the following steps: obtaining a supporting substrate; making a carrier trapping layer on the supporting substrate; making a dielectric layer on the carrier trapping layer; and making a piezoelectric film layer on the dielectric layer; wherein, the surface of the supporting substrate close to the carrier trapping layer is a first surface, and the surface of the dielectric layer close to the carrier trapping layer is a second surface; before making the piezoelectric film layer on the dielectric layer, the method further comprises making a scattering interface between the first surface and the second surface, and the scattering interface is used for scattering spurious waves. The carrier trapping layer can effectively inhibit the surface parasitic conductance effect, prevent the resistivity of the substrate from decreasing, and thus improve the loss and distortion of the piezoelectric substrate. The scattering interface can effectively inhibit the spurious waves caused by the interface reflection of the multilayer structure in the acoustic wave device, and thus improve the working stability of the device at high frequency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of acoustic wave devices, in particular to a preparation method of a piezoelectric substrate, a piezoelectric substrate and an acoustic wave device. BACKGROUND

[0002] More requirements are put forward for radio frequency filters in the 5G era. In radio frequency filters, surface acoustic wave (SAW) devices have attracted widespread attention. SAW devices are devices that use surface acoustic waves to simulate processing of electrical signals, and the frequency range is about 107-109Hz. SAW devices are the product of the organic combination of surface wave theory in modern acoustics, piezoelectricity research results and microelectronic technology. SAW is an elastic wave that is generated and propagated on the surface of a piezoelectric solid material and whose amplitude decreases rapidly with the depth of the solid material. SAW has two distinct features: one is high energy density, about 90% of which is concentrated in a surface thin layer with a thickness equal to one wavelength; the other is slow propagation speed, about 45% of the longitudinal wave speed and 90% of the transverse wave speed. In most cases, the propagation speed of SAW is 3000-5000m / s. According to these two characteristics, people have developed SAW devices with different functions, and these different types of passive devices are thin and light.

[0003] SAW devices are sensitive to temperature changes. By selecting materials with low thermal expansion coefficients or temperature coefficients, temperature compensation effects can be achieved. High-resistance silicon is usually selected as a support substrate to reduce device loss. However, at high frequencies, a conductive layer can be formed between high-resistance silicon and the insulating layer, resulting in a serious parasitic surface conductance effect. In addition, the flat interface layer between the piezoelectric layer and the substrate layer can reflect the leaked acoustic waves, resulting in the presence of undesirable interference noise in the substrate, which affects the working stability of the device at high frequencies. SUMMARY

[0004] The present application provides a piezoelectric substrate, a preparation method and an acoustic wave device to solve the problems existing in the structure of the piezoelectric substrate in the prior art.

[0005] To solve the above technical problems, in a first aspect, the present application discloses a preparation method of a piezoelectric substrate, comprising:

[0006] obtaining a support substrate;

[0007] making a carrier trapping layer on the support substrate;

[0008] making a dielectric layer on the carrier trapping layer;

[0009] making a piezoelectric thin film layer on the dielectric layer;

[0010] The surface of the support substrate close to the carrier trapping layer is a first surface, and the surface of the dielectric layer close to the carrier trapping layer is a second surface; the method further comprises manufacturing a scattering interface between the first surface and the second surface before manufacturing the piezoelectric film layer on the dielectric layer, and the scattering interface is used for scattering noise.

[0011] Further, the method of manufacturing the scattering interface between the first surface and the second surface comprises:

[0012] heating the support substrate to a preset temperature;

[0013] bombarding the first surface with inert gas ions of a preset energy at a preset oblique angle to manufacture the scattering interface on the first surface.

[0014] Further, the preset energy is 100 ev-2Kev, and the preset oblique angle is greater than or equal to 50°.

[0015] Further, the surface of the carrier trapping layer close to the dielectric layer is a third surface; and the method of manufacturing the scattering interface between the first surface and the second surface further comprises:

[0016] manufacturing the scattering interface on the third surface by a selective etching method.

[0017] Further, the method of manufacturing the piezoelectric substrate further comprises:

[0018] manufacturing an interface layer on the carrier trapping layer;

[0019] manufacturing the scattering interface on the interface layer by a selective etching method.

[0020] In a second aspect, the embodiments of the present application disclose a piezoelectric substrate, which is prepared by the method for preparing a piezoelectric substrate.

[0021] In a third aspect, the embodiments of the present application disclose an acoustic wave device, which comprises the piezoelectric substrate.

[0022] By using the above technical solutions, the piezoelectric substrate, the preparation method and the acoustic wave device have the following beneficial effects:

[0023] By setting a carrier trapping layer in the piezoelectric substrate structure to trap free carriers, the surface parasitic conductance effect can be effectively suppressed, the resistivity of the substrate is prevented from decreasing, and thus the loss and distortion of the piezoelectric substrate are improved. In addition, by setting a scattering interface between the support substrate and the dielectric layer, the spurious waves caused by the interface reflection of the multi-layer structure in the acoustic wave device can be effectively suppressed, and thus the working stability of the device at high frequency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 A flow chart of a piezoelectric substrate preparation method provided by the embodiments of the present application is shown in the figure.

[0026] Figure 2 A structural flowchart of a piezoelectric substrate preparation method provided by the embodiments of the present application is shown in the figure.

[0027] Figure 3 A structural flowchart of another piezoelectric substrate preparation method provided by the embodiments of the present application is shown in the figure.

[0028] Figure 4 A structural diagram of a piezoelectric substrate provided by the embodiments of the present application is shown in the figure.

[0029] Figure 5 A structural diagram of another piezoelectric substrate provided by the embodiments of the present application is shown in the figure.

[0030] Figure 6 A structural diagram of a single crystal silicon ion bombardment surface amorphization transition provided by the embodiments of the present application is shown in the figure.

[0031] The following is a supplementary description of the drawings:

[0032] 101 - support substrate; 102 - carrier trapping layer; 103 - interface layer; 104 - dielectric layer; 105 - piezoelectric film layer; 110 - scattering interface; 111 - first scattering interface; 112 - second scattering interface. DETAILED DESCRIPTION

[0033] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0034] The term "one embodiment" or "an embodiment" as used herein means a specific implementation, feature or structure or characteristic that can be included in at least one implementation of the present application. In the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", etc. indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features referred to. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more of the features. Moreover, the terms "first", "second" and the like are used to distinguish similar objects, and do not necessarily describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0035] The SAW device mainly includes a support substrate and a piezoelectric material with piezoelectric properties, and interdigitated interdigital transducers (IDT) composed of metal thin films made on the polished surface of the piezoelectric material. If a high-frequency electrical signal is added to both ends of the IDT electrode, mechanical vibration will occur on the surface of the piezoelectric material, and at the same time, surface acoustic waves with the same frequency as the applied electrical signal will be excited, and the surface acoustic waves will propagate along the surface of the substrate material. In the existing piezoelectric substrate structure, the flat interface layer between the piezoelectric material layer and the support substrate layer will reflect the leaked acoustic waves, resulting in undesirable interference noise in the substrate structure, affecting the stability of the device at high frequencies.

[0036] Therefore, the present application also provides a preparation method of a piezoelectric substrate, Figure 1 A flow chart of a preparation method of a piezoelectric substrate provided by the present application is shown in Figure 1 The method comprises the following steps:

[0037] S101: obtaining a support substrate 101.

[0038] In the present application,Figure 2 and Figure 3 respectively provide a structural flowchart of a preparation method of a piezoelectric substrate, as shown in Figure 2 and Figure 3 indicate that a single crystal silicon wafer is selected as a support substrate 101, and further, the material of the support substrate 101 is high resistance silicon, and the resistance value is not less than 1000 Ω·cm.

[0039] In an optional embodiment, as shown in Figure 2 and Figure 3 indicate that after the support substrate 101 is selected, any surface of the support substrate 101 is processed to make a scattering interface 110, and the scattering interface 110 is used to scatter noise. Specifically, the surface of the support substrate 101 is bombarded by low-energy inert gas ions. Optionally, the ion energy for ion bombardment is 100 ev-2Kev. When the support substrate 101 is ion bombarded, the ion beam has a certain inclination angle with the surface of the support substrate 101, and the angle is 0-40°. Before the support substrate 101 is ion bombarded, the support substrate 101 needs to be heated to a preset temperature, and the temperature is kept not lower than the preset temperature during the ion bombardment process. Optionally, the preset temperature is greater than or equal to 500°C. By ion bombarding the support substrate 101, a surface with corrugated nanostructure can be prepared on the surface of the support substrate 101. The nanostructure is a grating type structure, and the preparation period is 30nm-300nm. The roughness of the nanostructure is 10nm-100nm.

[0040] S103: making a carrier trapping layer 102 on the support substrate 101.

[0041] In the embodiments of the present application, as shown in Figure 2 and Figure 3 indicate that the carrier trapping layer 102 is made on the surface of the support substrate 101. If the scattering interface 110 is made on one of the surfaces of the support substrate 101, the carrier trapping layer 102 is made on the scattering interface 110, and the carrier trapping layer 102 fills the grooves on the scattering interface 110. Optionally, the material of the carrier trapping layer 102 is polysilicon. The polysilicon layer is deposited on the surface of the support substrate 101 at a preset temperature, and the polysilicon layer has many internal defects, which can provide enough grain boundaries to trap free carriers. Optionally, the deposition method of the polysilicon is low pressure chemical vapor deposition (LPCVD). Optionally, the preset temperature of the deposited polysilicon layer is 580°C-660°C. Optionally, the thickness of the grown polysilicon layer is not less than 1000nm.

[0042] In an optional embodiment, asFigure 2 As shown, after the carrier capture layer 102 is fabricated, the surface of the carrier capture layer 102 is processed to fabricate the scattering interface 110. The roughness of the scattering interface 110 is 10 nm-100 nm. Optionally, the scattering interface 110 can be a surface with irregular microstructure, or a surface with regular microstructure. Optionally, the scattering interface 110 is fabricated by a method of selective etching on the surface of the carrier capture layer 102. Specifically, the processing is performed by wet etching or dry etching. First, a mask is prepared on the surface of the carrier capture layer 102 to protect the surface, and then the carrier capture layer 102 is etched by wet etching or dry etching. For the regions not covered by the mask pattern, the regions will be etched, and finally a nano-microstructure with periodic structure is formed, which is a rough interface in macroscopic, i.e. the scattering interface 110. It should be noted that in the embodiments of the present application, the dry etching method is preferably used to etch the carrier capture layer 102. The dry etching has higher etching precision. Optionally, the dry etching can be performed by using reactive ion etching (RIE) or plasma etching, such as inductively coupled plasma etching (ICP). The etching gas can be selected from fluorine-containing CHF3, CBrF3, CF4, SF6, NF3, etc. In some embodiments, the surface of the carrier capture layer 102 can also be bombarded by low-energy ions to prepare the scattering interface 110 on the surface of the carrier capture layer 102.

[0043] In another optional embodiment, as shown in FIG. 1C, the carrier capture layer 102 is fabricated on the surface of the substrate 100. The carrier capture layer 102 is a rough interface in macroscopic, i.e. the scattering interface 110. The roughness of the scattering interface 110 is 10 nm-100 nm. Optionally, the scattering interface 110 can be a surface with irregular microstructure, or a surface with regular microstructure. Optionally, the scattering interface 110 is fabricated by a method of selective etching on the surface of the carrier capture layer 102. Specifically, the processing is performed by wet etching or dry etching. First, a mask is prepared on the surface of the carrier capture layer 102 to protect the surface, and then the carrier capture layer 102 is etched by wet etching or dry etching. For the regions not covered by the mask pattern, the regions will be etched, and finally a nano-microstructure with periodic structure is formed, which is a rough interface in macroscopic, i.e. the scattering interface 110. It should be noted that in the embodiments of the present application, the dry etching method is preferably used to etch the carrier capture layer 102. The dry etching has higher etching precision. Optionally, the dry etching can be performed by using reactive ion etching (RIE) or plasma etching, such as inductively coupled plasma etching (ICP). The etching gas can be selected from fluorine-containing CHF3, CBrF3, CF4, SF6, NF3, etc. In some embodiments, the surface of the carrier capture layer 102 can also be bombarded by low-energy ions to prepare the scattering interface 110 on the surface of the carrier capture layer 102. Figure 3As shown, after the carrier capture layer 102 is made, the interface layer 103 is prepared on the surface of the carrier capture layer 102 to make the scattering interface 110. Optionally, the material of the interface layer 103 is polysilicon or polycrystalline silicon carbide. Optionally, the interface layer 103 can be made by the method of chemical vapor deposition (CVD). After the interface layer 103 is made, the surface of the interface layer 103 is processed to make the scattering interface 110. The roughness of the scattering interface 110 is 10 nm-100 nm. Optionally, the scattering interface 110 can be a surface with irregular microstructure or a surface with regular microstructure. Optionally, the scattering interface 110 is prepared by the method of selective etching on the surface of the interface layer 103. Specifically, the wet etching or dry etching method is used for processing. First, a mask that plays a protective role is prepared on the surface of the interface layer 103, and then the wet etching or dry etching is performed on the interface layer 103. For the area not covered by the mask pattern, it will be etched, and finally the nano microstructure with periodic structure is formed, which is a rough interface in macroscopic, i.e., the scattering interface 110. It should be noted that in the embodiments of the present application, the dry etching method is preferably used to etch the interface layer 103. The dry etching has higher etching precision. Optionally, the dry etching can use the method of reactive ion etching or plasma etching, such as inductively coupled plasma etching technology. The etching gas can be selected from fluorine-containing CHF3, CBrF3, CF4, SF6 or NF3 gas. In some embodiments, low-energy ions can also be used to bombard the surface of the interface layer 103 to prepare the scattering interface 110 on the surface of the interface layer 103.

[0044] S105: A dielectric layer 104 is made on the carrier capture layer 102.

[0045] As shown in the embodiments of the present application, Figure 5 and Figure 6 The dielectric layer 104 has a small thermal expansion coefficient or temperature coefficient, and the selected material includes but is not limited to silicon oxide, silicon nitride, aluminum nitride, etc. The dielectric layer 104 is prepared on the carrier capture layer 102 or the interface layer 103 by the method of surface deposition. When the dielectric layer 104 is made on the interface layer 103, and the interface layer 103 is made of polycrystalline silicon carbide, the dielectric layer 104 can be prepared by depositing amorphous silicon on the surface of the polycrystalline silicon carbide layer and then heat oxidizing. The material of the interface layer 103 is selected to be polycrystalline silicon carbide, which can prevent the amorphous silicon layer as the dielectric layer 104 from being over-oxidized.

[0046] S107: A piezoelectric thin film layer 105 is made on the dielectric layer 104.

[0047] As shown in the embodiments of the present application, Figure 5and Figure 6 As shown in FIG. 1, after the medium layer 104 is made, the piezoelectric thin film layer 105 is made on the medium layer 104 as an active layer. Optionally, the material for making the piezoelectric thin film layer 105 includes lithium niobate or lithium tantalate. Optionally, the transfer method of the piezoelectric thin film layer 105 can be one of ion implantation and bond peeling, grinding and thinning, and epitaxy. As an optional embodiment, the piezoelectric thin film layer 105 made on the medium layer 104 can be specifically as follows: a bulk wafer of piezoelectric material, such as a lithium tantalate wafer, a lithium niobate wafer, etc., is obtained, and then the bulk wafer of piezoelectric material is subjected to ion implantation to introduce defects in the bulk wafer of piezoelectric material. Optionally, the implanted ions can be hydrogen ions, helium ions, or hydrogen-helium co-implantation, etc. After the bulk wafer of piezoelectric material is subjected to ion implantation, the bulk wafer of piezoelectric material is bonded with the medium layer 104 to form a bonded body. Annealing causes the bulk wafer of piezoelectric material to peel off along the defects to form a hetero-piezoelectric thin film layer 105 on the medium layer 104. In some embodiments, the medium layer 104 needs to be subjected to planarization treatment before the piezoelectric thin film layer 105 is transferred on the medium layer 104, so as to ensure the thin film quality and reduce the loss of the acoustic wave device. In other embodiments, after the piezoelectric thin film layer 105 is made on the medium layer 104, the piezoelectric thin film layer 105 can also be subjected to surface treatment to remove the surface damage layer and improve the thin film quality. Specifically, the piezoelectric thin film layer 105 is thinned to a specified thickness by chemical mechanical polishing, and the surface damage layer is removed.

[0048] The piezoelectric substrate provided in the embodiments of the present application is prepared by the piezoelectric substrate preparation method as described above.

[0049] In the embodiments of the present application, Figure 4 A structure schematic diagram of the piezoelectric substrate provided in the embodiments of the present application is shown in FIG. 1, which includes: Figure 4

[0050] The support substrate 101, the carrier trapping layer 102, the medium layer 104, and the piezoelectric thin film layer 105. The carrier trapping layer 102 is arranged on the support substrate 101. The medium layer 104 is arranged on the carrier trapping layer 102. The piezoelectric thin film layer 105 is arranged on the medium layer 104. The surface of the support substrate 101 close to the carrier trapping layer 102 is a first surface, the surface of the medium layer 104 close to the carrier trapping layer 102 is a second surface, and a scattering interface 110 is arranged between the first surface and the second surface, and the scattering interface 110 is used for scattering spurs.

[0051] ​In the embodiment of the present application, the support substrate 101 is used to support the piezoelectric thin film layer 105. The material of the support substrate 101 is monocrystalline silicon. Alternatively, the support substrate 101 is selected as a high-resistance silicon substrate to reduce the loss of the device. Alternatively, the resistance of the high-resistance silicon substrate is greater than or equal to 1000 Ω·cm. The support substrate 101 is provided with a carrier trapping layer 102 for trapping free carriers. Alternatively, the material of the carrier trapping layer 102 is selected as polysilicon material. The carrier trapping layer 102 made of polysilicon material has a large number of internal defects, which can provide sufficient grain boundaries, and a large number of grain boundaries can trap free carriers, thereby improving the loss and distortion of the substrate. The carrier trapping layer 102 is provided with a dielectric layer 104, and the dielectric layer 104 is mainly used to separate the support substrate 101 and the piezoelectric thin film as an electrical isolation layer. Moreover, the dielectric layer 104 can also be used for temperature compensation of the radio frequency device, thereby improving the working stability at high frequency. The dielectric layer 104 is also used as a bonding layer to improve the bonding strength of the piezoelectric thin film. Alternatively, the dielectric layer 104 is selected to be prepared by an electrically insulating material with a small thermal expansion coefficient or temperature coefficient to provide a better temperature compensation effect. At the same time, a smooth interface for bonding with the piezoelectric thin film layer 105 is also provided. The piezoelectric thin film layer 105 is arranged on the dielectric layer 104, and the piezoelectric thin film layer 105 is made of piezoelectric material. The piezoelectric thin film layer 105 is used as an active layer for the preparation of an acoustic wave device. Alternatively, the material of the piezoelectric thin film layer 105 includes lithium niobate or lithium tantalate.

[0052] In the embodiment of the present application, in order to solve the problem of interference noise existing in the piezoelectric substrate, a scattering interface 110 with high roughness is introduced between the support substrate 101 and the dielectric layer 104 to scatter the interference noise, so as to avoid the influence of the interference noise on the working stability of the SAW device at high frequency. Alternatively, a scattering interface 110 can be arranged in the piezoelectric substrate to suppress the noise caused by the interface reflection of the multi-layer structure in the acoustic wave device. Alternatively, two or more scattering interfaces 110 can be arranged to suppress the noise caused by the interface reflection of the multi-layer structure in the acoustic wave device. Alternatively, the roughness of the scattering interface 110 is 10 nm-100 nm, that is, the size of the protrusions or depressions in the scattering interface 110 is 10 nm-100 nm.

[0053] As an alternative implementation, as shown in FIG. 6, the support substrate 101 is provided with a carrier trapping layer 102, and the carrier trapping layer 102 is provided with a dielectric layer 104. The dielectric layer 104 is provided with a piezoelectric thin film layer 105. The piezoelectric thin film layer 105 is provided with a scattering interface 110. The scattering interface 110 is arranged between the piezoelectric thin film layer 105 and the dielectric layer 104. Figure 4As shown, a scattering interface 110 is disposed in the piezoelectric substrate. This scattering interface 110 can be the interface between the supporting substrate 101 and the carrier trapping layer 102. Alternatively, it can be the interface between the carrier trapping layer 102 and the supporting substrate 101. It can also be the interface between the carrier trapping layer 102 and the dielectric layer 104. Finally, it can be the interface between the dielectric layer 104 and the carrier trapping layer 102. The scattering interface 110 can also be formed by disposing an interface layer 103 between the carrier trapping layer 102 and the dielectric layer 104, and then processing the surface of the interface layer 103. Optionally, the interface layer 103 is made of polycrystalline silicon or polycrystalline silicon carbide.

[0054] As an alternative implementation, the piezoelectric substrate has two scattering interfaces 110. Specifically, the scattering interface 110 includes a first scattering interface 111 and a second scattering interface 112. Optionally, the first scattering interface 111 is a first surface, i.e., the interface between the supporting substrate 101 and the carrier trapping layer 102. The first scattering interface 111 can be a surface with irregular microstructures or a surface with regular microstructures. Optionally, the first scattering interface 111 is a surface with regular microstructures, which can be a grating structure. Optionally, the period of the grating structure is 30nm-300nm. The second scattering interface 112 can be the interface between the carrier trapping layer 102 and the dielectric layer 104. The second scattering interface 112 can also be the interface between the dielectric layer 104 and the carrier trapping layer 102. Figure 2 This is a schematic diagram of another piezoelectric substrate provided in an embodiment of this application, as shown below. Figure 5 As shown, the second scattering interface 112 can also be formed by disposing an interface layer 103 between the carrier trapping layer 102 and the dielectric layer 104, and then processing the surface of the interface layer 103. Optionally, the interface layer 103 is made of polycrystalline silicon or polycrystalline silicon carbide. The first scattering interface 111 and the second scattering interface 112 together constitute a double-layer scattering interface 110, which can effectively suppress clutter caused by interface reflections of multi-layer structures in acoustic wave devices.

[0055] In an optional embodiment, the first scattering interface 111 is a surface with a corrugated nanostructure prepared on the surface of the supporting substrate 101 by low-energy ion bombardment. This corrugated nanostructure surface can, on the one hand, increase the contact area with the deposited carrier trapping layer 102, and on the other hand, provide a surface with a defined roughness as the first scattering interface 111. It should be noted that, due to the conditions at room temperature, Figure 6 A schematic diagram of the amorphization transformation structure of a single-crystal silicon surface after ion bombardment is provided in an embodiment of this application, as shown below. Figure 6As shown, bombardment of the single crystal substrate surface by energetic ions can introduce a large number of defects in the nanostructure and even cause the surface to be amorphized. Therefore, when the surface of the support substrate 101 is bombarded by low-energy ions, the support substrate 101 needs to be heated to a temperature higher than the recrystallization temperature of the material of the support substrate 101, so that the support substrate 101 will remain single-crystal characteristics.

[0056] The piezoelectric substrate described in the embodiments of the present application can effectively suppress the surface parasitic conductance effect by setting the carrier trapping layer 102 in the piezoelectric substrate structure to trap free carriers, prevent the resistivity of the substrate from decreasing, and thus improve the loss and distortion of the piezoelectric substrate. In addition, by setting the scattering interface 110 between the support substrate 101 and the dielectric layer 104, the spurious waves caused by the interface reflection of the multilayer structure in the acoustic wave device can be effectively suppressed, and thus the working stability of the device at high frequencies can be improved.

[0057] The embodiments of the present application also provide an acoustic wave device, which comprises the piezoelectric substrate as described above.

[0058] In the embodiments of the present application, the acoustic wave device can be a resonator, a filter, or the like, and the acoustic wave device comprises the piezoelectric substrate as described above. For the specific structure of the piezoelectric substrate, please refer to the above description of all the ways of the piezoelectric substrate.

[0059] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of producing a piezoelectric substrate, characterized by, The preparation method comprises the following steps: obtaining a support substrate (101); making a carrier trapping layer (102) on the support substrate (101); making a dielectric layer (104) on the carrier trapping layer (102); making a piezoelectric film layer (105) on the dielectric layer (104); wherein the surface of the support substrate (101) close to the carrier trapping layer (102) is a first surface, and the surface of the dielectric layer (104) close to the carrier trapping layer (102) is a second surface; the step of making the piezoelectric film layer (105) on the dielectric layer (104) further comprises the step of making a scattering interface (110) between the first surface and the second surface, the scattering interface (110) is used for scattering noise, and the roughness of the scattering interface (110) is 10 nm-100 nm; the step of making the scattering interface (110) between the first surface and the second surface comprises the steps of: heating the support substrate (101) to a preset temperature; bombarding the first surface with inert gas ions with a preset energy and at a preset oblique angle to make the scattering interface (110) on the first surface.

2. The production method according to claim 1, characterized by, The scattering interface (111) is a grating type structure, and the period of the grating type structure is 30 nm-300 nm.

3. The method of claim 1, wherein, The preset energy is 100 ev-2Kev; and the preset oblique angle is greater than or equal to 50°.

4. The production method according to any one of claims 1 to 3, characterized by, The surface of the carrier trapping layer (102) close to the dielectric layer (104) is a third surface; the step of making the scattering interface (110) between the first surface and the second surface further comprises the step of: making the scattering interface (110) on the third surface by a selective etching method.

5. The method of any one of claims 1-3, wherein, Before the step of making the dielectric layer (104) on the carrier trapping layer (102), the method further comprises the steps of: making an interface layer (103) on the carrier trapping layer (102); making the scattering interface (110) on the interface layer (103) by a selective etching method.

6. The production method according to claim 1 or 3, characterized by, The method for making the piezoelectric film layer (105) on the dielectric layer (104) comprises any one of ion implantation and bond peeling, grinding and thinning, or epitaxy.

7. A piezoelectric substrate, characterized by, The piezoelectric substrate is prepared by the preparation method of the piezoelectric substrate according to any one of claims 1-6.

8. An acoustic wave device, characterized by, The acoustic wave device comprises the piezoelectric substrate according to claim 7.

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