A three-state gate circuit based on a three-terminal resistive switching device

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, and discloses a three-state gate circuit based on a three-terminal resistive switching device. The present invention uses a single three-terminal resistive switching device with two resistance states to construct a three-state gate circuit. The three-terminal resistive switching device has one more side control voltage input port than a two-terminal resistive switching device. Compared with a traditional CMOS three-state output gate, the number of devices in a three-state gate circuit based on a three-terminal resistive switching device is reduced from multiple to a single device, thereby improving the integration density, having non-volatility, and reducing power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and integrated circuits, and in particular relates to a three-state gate circuit based on a three-terminal resistive switching device. Background Art

[0002] With the development of integrated circuit technology, the characteristic size of electronic devices is constantly decreasing, and traditional electronic devices are increasingly facing the challenge of physical limits. In recent years, in order to improve the integration density and performance of semiconductor memory chips, the research of various new non-volatile memories has made continuous progress, and resistive switching materials and resistive switching devices have received increasing attention. Resistive switching materials will change their resistance state under the action of an external electric field, and their resistance value can still be maintained after the electric field is removed. Resistive switching devices are electronic devices that can process signals and are made using the resistance variability of resistive switching materials.

[0003] At present, the main application of resistive switching devices is resistive switching memory, which is a new technology that uses the change of the internal resistance value of resistive switching materials to store data. The change of the resistance state of the resistive switching device indicates that the stored value is 0 or 1. Resistive switching memory has the advantages of low power consumption, low operating voltage, fast read and write speed, and high storage density. It has become one of the preferred solutions to replace traditional Flash non-volatile memory, and is even expected to become the next generation of general-purpose memory to replace various existing memories. However, in addition to being used in the memory field, resistive switching devices can also be used in logic gate circuits to realize logical operations.

[0004] Traditional multifunctional logic circuits use selectors or switches to select circuits with different functions. With the increase of circuit functions and the improvement of modern complexity, the consumption of circuit resources will increase exponentially. The concepts of polymorphic electronics and polymorphic circuits were proposed by Stoica et al. As a non-traditional multifunctional circuit, polymorphic circuits can adaptively change the function of the circuit by sensing changes in the external environment (such as temperature, light, voltage, etc.) without changing the circuit structure, thus saving circuit resources.

[0005] The design of polymorphic gates is the basis of polymorphic electronics and polymorphic circuits. However, design and experiments have also shown that the most complex transistor-level polymorphic circuit evolution can only realize a single gate function. There has been little research on the actual performance of polymorphic gates. Three-state gates are widely used in the field of digital circuits, especially in digital integrated circuits, mainly bus structures and bidirectional transmission gates. In some complex digital systems, in order to reduce the number of connections between each unit, a bus structure based on a three-state gate is often used to achieve time-sharing transmission of output signals of multiple gate circuits using the same wire. The use of two gate circuits with three-state output structures can also realize bidirectional transmission of data. However, these traditional three-state gates are all based on CMOS, and the present invention aims to apply three-terminal resistive switching devices to three-state output gate circuits. Summary of the invention

[0006] In view of the shortcomings of the existing CMOS-based three-state output gate, the purpose of the present invention is to provide a three-state gate circuit based on a three-terminal resistive variable device. By changing the resistance state of the three-terminal resistive variable device, the three-terminal resistive variable device can be used in the three-state gate circuit, thereby improving the integration and reducing the power consumption.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] A three-state gate circuit based on a three-terminal resistive switching device, wherein the output of the three-state gate circuit includes a high level, a low level and a high impedance state, and the three-terminal resistive switching device has a top end, a bottom end and a side end;

[0009] The three-terminal resistive switching device includes a first metal layer, a bottom end is led out through the first metal layer, a metal tantalum oxide layer is formed on the upper surface of the first metal layer, a metal tantalum layer is formed on the upper surface of the metal tantalum oxide layer, the upper surface and side of the metal tantalum layer, and the side of the metal tantalum oxide layer surround an isolation layer, a second metal layer is formed on the top of the isolation layer, a top end is led out through the second metal layer, a third metal layer is formed on the side of the isolation layer, and a side end is led out through the third metal layer;

[0010] An assignment operation is performed on the three-terminal resistive variable device to control the resistance state of the three-terminal resistive variable device. After the assignment, the three-terminal resistive variable device can realize a three-state output gate.

[0011] Furthermore, the first metal layer is Cu or Ni; the second metal layer is Ti, TiN or Pt; the third metal layer is W, Cu, Ti or TiN; and the isolation layer is generally an active metal oxide layer, such as a hafnium oxide layer or a nickel oxide layer.

[0012] Furthermore, the assigning operation to the three-terminal resistive switching device to control the resistance state of the resistive switching device is performed by applying voltage to three terminals of the three-terminal resistive switching device to assign values, including:

[0013] When the top of the three-terminal resistive variable device is connected to the negative voltage -Vp1, the bottom of the three-terminal resistive variable device is connected to the ground GND, and the side of the three-terminal resistive variable device is connected to the positive voltage Vdd1, the three-terminal resistive variable device is set to a high-impedance state, and the output of the three-state gate circuit is a high-impedance state;

[0014] When the top of the three-terminal resistive variable device is connected to the positive voltage Vp2, the bottom of the three-terminal resistive variable device is connected to the ground GND, and the side of the three-terminal resistive variable device is connected to the positive voltage Vdd2, the three-terminal resistive variable device is set to a low resistance state, and the output of the three-state gate circuit is a high level or a low level;

[0015] Among them, Vp1≥|Vreset|, Vp2≥|Vset|, Vdd1≥|Vdd|, Vdd2≥|Vdd|, Vreset is the threshold voltage required for the three-terminal resistive variable device to be set to a high-resistance state, Vset is the threshold voltage required for the three-terminal resistive variable device to be set to a low-resistance state, and Vdd is the side threshold voltage that enables the three-terminal resistive variable device to be resistive.

[0016] Furthermore, after the assignment, the side terminal of the three-terminal resistive variable device is grounded GND, and a three-state output gate can be realized at this time, including:

[0017] If the three-terminal resistive variable device is in a low-resistance state and a high level is input to the top end of the three-terminal resistive variable device, the bottom end of the three-terminal resistive variable device outputs a high level;

[0018] If the three-terminal resistive variable device is in a low-resistance state and a low level is input to the top end of the three-terminal resistive variable device, the bottom end of the three-terminal resistive variable device outputs a low level;

[0019] If the three-terminal resistive variable device is in a high-impedance state, the bottom end of the three-terminal resistive variable device outputs a high-impedance state.

[0020] Furthermore, the assignment operation of the three-terminal resistive switching device requires one clock cycle.

[0021] The beneficial technical effect of the present invention is as follows: the present invention designs the structure of a three-terminal resistive switching device, and uses the designed three-terminal resistive switching device to construct a three-state output gate circuit, which can reduce the number of devices required for a traditional three-state output gate circuit based on CMOS, and directly implement the three-state output gate circuit on a single device, thereby reducing the circuit implementation area and delay, and reducing the circuit cost; at the same time, the application field of the resistive switching device is expanded. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic structural diagram of a three-terminal resistive switching device provided by an embodiment of the present invention;

[0023] Figure 2 It is a schematic diagram of simulation results of a three-terminal resistive switching device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with the accompanying drawings and specific implementation methods.

[0025] In the description of the present invention, it is necessary to understand that words indicating positions such as “top end”, “bottom end” and “side end” are based on the drawings and are only used to facilitate the description of the present invention. They do not refer to a specific device structure and therefore cannot be understood as a limitation on the present invention.

[0026] The specific implementation of the present invention is to provide a novel three-state gate circuit based on a three-terminal resistive variable device, which is used to realize a three-state output gate circuit, and the output includes a high level, a low level and a high impedance state to realize logic operations.

[0027] The three-terminal resistive switching device of the present invention is a three-port element, and its basic structure is as follows: Figure 1 As shown, it includes a first metal layer 3, the bottom end is led out through the first metal layer 3, a metal tantalum oxide layer 2 is formed on the upper surface of the first metal layer 3, a metal tantalum layer 1 is formed on the upper surface of the metal tantalum oxide layer 2, the upper surface and side of the metal tantalum layer 1, and the side of the metal tantalum oxide layer 2 surround the isolation layer 4, a second metal layer 6 is formed on the top of the isolation layer 4, the top end is led out through the second metal layer 6, a third metal layer 5 is formed on the side of the isolation layer 4, and the side end is led out through the third metal layer 5. By applying different combinations of voltages to the top, bottom, and side of the three-terminal resistive variable device, the three-terminal resistive variable device is assigned to control the resistance state of the three-terminal resistive variable device, and after the assignment, the three-terminal resistive variable device can realize a three-state output gate.

[0028] The metal tantalum oxide layer 2 between the metal tantalum layer 1 and the first metal layer 3 is a resistive material interlayer, similar to the electrode-dielectric-electrode (MIM, metal-insulator-metal) structure of a capacitor. There are many types of resistive materials, mainly perovskite oxides and transition metal oxides. The choice of electrode material depends on the type of resistive material, including active metal electrodes (such as Ti, Cu or Ni, etc.) and inert electrodes (such as Pt, W, etc.). The resistive material of the present invention is tantalum oxide. On the one hand, the isolation layer 4 plays the role of electrical isolation, and on the other hand, it plays the role of absorbing conductive oxygen vacancies in the resistive material interlayer or transporting oxygen vacancies to the resistive material interlayer. It mainly includes metal oxides such as hafnium oxide and nickel oxide, and does not directly participate in the resistive process. The third metal layer 5 serves as a side electrode, which is a metal or other conductive material, and controls whether the resistive device can resistively change by applying voltage.

[0029] The resistance state conversion of a traditional two-terminal resistive variable device can be divided into two processes, set and reset. Set is to change the device from a high resistance state to a low resistance state by applying a bias voltage at the top and bottom of the two-terminal resistive variable device, while reset is the opposite, and the device is returned from a low resistance state to a high resistance state by applying a reverse bias voltage at the top and bottom of the two-terminal resistive variable device. The three-terminal resistive variable device of the present invention has a side terminal in addition to a top and a bottom terminal. Resistance state conversion can also be divided into two processes, set and reset, except that the bias voltage added is different. Set is to change the device from a high resistance state to a low resistance state by applying a bias voltage at the top and bottom of the three-terminal resistive variable device, and at the same time, a high level is added to the side terminal. Reset is to change the device from a high resistance state to a low resistance state by applying a reverse bias voltage at the top and bottom of the three-terminal resistive variable device, and at the same time, a high level is added to the side terminal. If a low level is added to the side terminal of the three-terminal resistive variable device, no matter what kind of bias is applied to the top and bottom of the three-terminal resistive variable device, the resistance state of the three-terminal resistive variable device cannot be changed.

[0030] Voltage can be applied to the three terminals of the three-terminal resistive variable device to perform a value assignment operation on the three-terminal resistive variable device, so that the resistance value of the resistive variable device is switched between a high resistance state and a low resistance state, as shown in Table 1.

[0031] Table 1

[0032]

[0033] include:

[0034] When the top end of the three-terminal resistive variable device is connected to a negative voltage -Vp, the bottom end is connected to GND, and the side end is connected to a positive voltage Vdd, the three-terminal resistive variable device will be set to a high-resistance state regardless of its previous state; when the top end of the three-terminal resistive variable device is connected to a positive voltage Vp, the bottom end is connected to GND, and the side end is connected to a positive voltage Vdd, the three-terminal resistive variable device will be set to a low-resistance state regardless of its previous state; for other voltage connections of the three electrodes, the resistance state inside the three-terminal resistive variable device will not change.

[0035] After the assignment, the output voltage at the bottom will be determined according to the input signal at the top and the resistance state inside the three-state resistive device, as shown in Table 2.

[0036] Table 2

[0037]

[0038] include:

[0039] When the resistance value of the three-terminal resistor variable device is in a low resistance state, a high level Vdd is added to the top and a low level GND is added to the side, then the three-state output gate will output a high level Vdd at the bottom. The low level is usually directly grounded.

[0040] When the resistance state of the three-terminal resistive variable device is low resistance state, a low level GND is added to the top end and a low level GND is added to the side end, then the three-state output gate will output a low level GND at the bottom end.

[0041] When the resistance state of the three-terminal resistive variable device is high impedance, a high level Vdd is added to the top and a low level GND is added to the side, then the three-state output gate will output a high impedance state at the bottom.

[0042] When the resistance state of the three-terminal resistive variable device is high impedance, a low level GND is added to the top and a low level GND is added to the side, then the three-state output gate will also output a high impedance state at the bottom.

[0043] It can be seen that for Figure 1 The multi-state output gate shown in the figure can realize three outputs, namely high level, low level and high impedance state, by changing the resistance state inside the three-terminal resistive variable device. Figure 1 The circuit shown in the figure is simulated, and the simulation results are shown in Figure 2 shown.

[0044] During 0ms-50ms, the top end, namely the first row Vin, is at a low level, the side end, namely the second row Vm, is also at a low level, and the bottom end, namely the third row Vout, outputs a low level.

[0045] At 50ms-100ms, the top end is low level, the side end is high level, and the bottom end output is low level.

[0046] At 100ms-150ms, the top end is high level, the side end is low level, and the bottom end output is low level.

[0047] At 150ms-200ms, the top end is at a high level and the side end is at a high level. At this time, the resistance state of the three-terminal resistive variable device is set to a low resistance state, and the output becomes a high level.

[0048] At 200ms-250ms, the top end becomes a low level, the side end is a low level, the resistance state of the three-terminal resistive variable device is a low resistance state, and the bottom end output is a low level.

[0049] At 250ms-300ms, the top end is at a low level, the side end is at a high level, the resistance state of the three-terminal resistive variable device is a low resistance state, and the bottom end output is a low level.

[0050] At 300ms-350ms, the top end is a negative level, the side end is a low level, the resistance state of the three-terminal resistive variable device is a low resistance state, and the bottom end output is a negative level.

[0051] At 350ms-400ms, the top end is at a negative level and the side end is at a high level. At this time, the resistance state of the three-terminal resistive variable device is set to a high-impedance state, and the bottom end output becomes a high-impedance state.

[0052] During 400ms-500ms, the bottom output remains in high impedance state.

[0053] It can be seen from the results in Table 2 that the polymorphic gate proposed in the present invention can be realized without additional circuit elements. The polymorphic gate proposed in the present invention is realized by a single resistive switching device, and the three-state output can be realized by adjusting the voltage applied to the three-terminal resistive switching device. Since this three-state gate circuit adopts a resistive switching device, it can not only realize the three-state output, but also improve the integration and speed, reduce the cost and power consumption, and is conducive to overcoming the separation of information processing and storage in the current von Neumann architecture, and provides a new idea for realizing storage and computing integration.

[0054] The above description is merely a preferred embodiment of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present specification shall be included in the scope of protection of one or more embodiments of the present specification.

Claims

1. A three-state gate circuit based on a three-terminal resistive variable device, wherein the output of the three-state gate circuit includes a high level, a low level and a high impedance state, characterized in that: The three-terminal resistive switching device has a top end, a bottom end and a side end; The three-terminal resistive switching device includes a first metal layer, a bottom end is led out through the first metal layer, a metal tantalum oxide layer is formed on the upper surface of the first metal layer, a metal tantalum layer is formed on the upper surface of the metal tantalum oxide layer, the upper surface and side of the metal tantalum layer, and the side of the metal tantalum oxide layer all surround an isolation layer, a second metal layer is formed on the top of the isolation layer, a top end is led out through the second metal layer, a third metal layer is formed on the side of the isolation layer, and a side end is led out through the third metal layer; The three-terminal resistive switching device is assigned a value to control the resistance state of the three-terminal resistive switching device, and the value is assigned by applying voltage to three terminals of the three-terminal resistive switching device, including: When the top of the three-terminal resistive variable device is connected to the negative voltage -Vp1, the bottom of the three-terminal resistive variable device is connected to the ground GND, and the side of the three-terminal resistive variable device is connected to the positive voltage Vdd1, the three-terminal resistive variable device is set to a high-impedance state, and the output of the three-state gate circuit is a high-impedance state; When the top of the three-terminal resistive variable device is connected to the positive voltage Vp2, the bottom of the three-terminal resistive variable device is connected to the ground GND, and the side of the three-terminal resistive variable device is connected to the positive voltage Vdd2, the three-terminal resistive variable device is set to a low resistance state, and the output of the three-state gate circuit is a high level or a low level; Wherein, Vp1≥|Vreset|, Vp2≥|Vset|, Vdd1≥|Vdd|, Vdd2≥|Vdd|, Vreset is the threshold voltage required for the three-terminal resistive variable device to be set to a high-resistance state, Vset is the threshold voltage required for the three-terminal resistive variable device to be set to a low-resistance state, and Vdd is the side threshold voltage that enables the three-terminal resistive variable device to resist change; After the assignment, the side end of the three-terminal resistive variable device is grounded GND, and a three-state output gate can be realized, including: If the three-terminal resistive variable device is in a low-resistance state and a high level is input to the top end of the three-terminal resistive variable device, the bottom end of the three-terminal resistive variable device outputs a high level; If the three-terminal resistive variable device is in a low-resistance state and a low level is input to the top end of the three-terminal resistive variable device, the bottom end of the three-terminal resistive variable device outputs a low level; If the three-terminal resistive variable device is in a high-impedance state, the bottom end of the three-terminal resistive variable device outputs a high-impedance state.

2. The three-state gate circuit based on a three-terminal resistive switching device according to claim 1, characterized in that: The first metal layer is Cu or Ni; the second metal layer is Ti, TiN or Pt; the third metal layer is W, Cu, Ti or TiN; and the isolation layer is a hafnium oxide layer or a nickel oxide layer.

3. The three-state gate circuit based on a three-terminal resistive switching device according to claim 1, characterized in that: The assignment operation of the three-terminal resistive switching device requires one clock cycle.

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