Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate on which a channel layer structure is formed; oxidizing the channel layer structure to form an interface layer on the surface of the channel layer structure; forming a gate dielectric layer covering the interface layer; forming an oxygen adsorption layer covering the gate dielectric layer, adapted to adsorb oxygen ions in the interface layer; performing a first annealing treatment on the oxygen adsorption layer, the gate dielectric layer, and the interface layer, adapted to allow oxygen ions in the interface layer to diffuse into the oxygen adsorption layer, and during the first annealing treatment, the oxygen adsorption layer adsorbs oxygen ions; and removing the oxygen adsorption layer after the first annealing treatment. In the first annealing treatment, oxygen ions in the interface layer diffuse into the oxygen adsorption layer and are adsorbed by the oxygen adsorption layer, reducing the oxygen ion content in the interface layer and thus reducing the thickness of the interface layer. This helps to reduce impurities and defects in the interface layer, correspondingly reducing the interface state density between the channel layer structure and the gate dielectric layer, thereby improving the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. BACKGROUND

[0002] The main semiconductor device of integrated circuits, especially very large scale integrated circuits, is metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology node of semiconductor devices is continuously reduced, and the geometric size of semiconductor devices is continuously reduced according to Moore's law. When the size of the semiconductor device is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor device appear in succession, and the proportional reduction of the feature size of the semiconductor device becomes more and more difficult. Among them, in the field of semiconductor manufacturing, the most challenging is how to solve the problem of large leakage current of semiconductor devices. The large leakage current of the semiconductor device is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer.

[0003] The current solution is to replace the traditional silicon dioxide gate dielectric material with high-k gate dielectric material, and use metal as the gate electrode to avoid the Fermi level pinning effect and boron penetration effect of high-k material and traditional gate electrode material. The introduction of high-k metal gate reduces the leakage current of the semiconductor device. SUMMARY

[0004] The problem solved by the embodiments of the present application is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above problems, the embodiments of the present application provide a method for forming a semiconductor structure, comprising: providing a substrate, a channel layer structure is formed on the substrate; performing an oxidation treatment on the surface of the channel layer structure to form an interface layer located on the surface of the channel layer structure; forming a gate dielectric layer covering the interface layer; forming an oxygen adsorption layer covering the gate dielectric layer, the oxygen adsorption layer is suitable for adsorbing oxygen ions in the interface layer; performing a first annealing treatment on the oxygen adsorption layer, the gate dielectric layer and the interface layer, the first annealing treatment is suitable for diffusing the oxygen ions in the interface layer to the oxygen adsorption layer, and during the first annealing treatment, the oxygen adsorption layer adsorbs the oxygen ions; after the first annealing treatment, the oxygen adsorption layer is removed.

[0006] Optionally, the oxygen adsorption layer is formed by a deposition process, and the oxygen partial pressure of the deposition process is less than the oxygen partial pressure of the oxidation process.

[0007] Optionally, the oxygen adsorption layer is formed by a physical vapor deposition process.

[0008] Optionally, during the first annealing process, oxygen ions in the interface layer diffuse towards the surface of the gate dielectric layer of the oxygen adsorption layer, forming a barrier layer between the gate dielectric layer and the oxygen adsorption layer on the sidewall of the channel layer structure and between the gate dielectric layer and the oxygen adsorption layer on the top of the channel layer structure; the barrier layer is retained after the oxygen adsorption layer is removed.

[0009] Optionally, the material of the oxygen adsorption layer comprises one or more of Ta, Ti, TiN, TaN, TiAl, TaAl, AlN and W.

[0010] Optionally, the oxidation process comprises an in-situ steam generation process, a chemical oxidation process or a thermal oxidation process.

[0011] Optionally, the first annealing process comprises a low-temperature furnace tube annealing process, a spike annealing process, a laser annealing process or a flash annealing process.

[0012] Optionally, the oxygen adsorption layer is removed by a wet etching process.

[0013] Optionally, the etching solution used in the wet etching process comprises an APM solution.

[0014] Optionally, the gate dielectric layer comprises a high-k gate dielectric layer.

[0015] Optionally, after the gate dielectric layer covering the interface layer is formed, before the oxygen adsorption layer covering the gate dielectric layer is formed, the forming method further comprises: performing a second annealing process on the gate dielectric layer.

[0016] Optionally, the thickness of the oxygen adsorption layer is 0.5-5 nm.

[0017] Optionally, the material of the channel layer structure comprises SiGe, Ge or Si.

[0018] Optionally, after the oxygen adsorption layer is removed, the forming method further comprises: forming a work function layer covering the gate dielectric layer and a gate electrode layer covering the work function layer.

[0019] Optionally, the channel layer structure is a fin protruding from the substrate; or the channel layer structure is spaced apart from the substrate, and the channel layer structure comprises one or more channel layers spaced apart in the normal direction of the surface of the substrate; in the step of forming the gate dielectric layer covering the interface layer, the gate dielectric layer surrounds the channel layer.

[0020] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0021] ​The forming method provided by the embodiment of the present application comprises the following steps: performing oxidation treatment on the surface of the channel layer structure to form an interface layer on the surface of the channel layer structure; forming an oxygen adsorption layer covering the gate dielectric layer; and performing first annealing treatment on the oxygen adsorption layer, the gate dielectric layer and the interface layer, so as to diffuse oxygen ions in the interface layer into the oxygen adsorption layer, and adsorb the oxygen ions in the oxygen adsorption layer during the first annealing treatment, and then remove the oxygen adsorption layer; wherein the interface layer is formed by performing oxidation treatment on the surface of the channel layer structure, and the material of the interface layer at least contains one of the elements of the material of the channel layer structure; during the first annealing treatment, redox reaction occurs between the interface layer and the oxygen adsorption layer, the oxygen ions in the interface layer diffuse into the oxygen adsorption layer, fill into the corresponding oxygen vacancies in the oxygen adsorption layer, and are adsorbed by the oxygen adsorption layer, so that the content of the oxygen ions in the interface layer is reduced, which makes the part of atoms in the interface layer that are the same as the material elements of the channel layer structure unable to form chemical bonds with oxygen, and the un-bonded atoms in the part of atoms in the interface layer that are the same as the material elements of the channel layer structure diffuse to the surface of the channel layer structure, so that the interface layer is reduced during the first annealing treatment, and the material layer formed after the reduction of the interface layer at the interface between the interface layer and the channel layer structure becomes part of the channel layer structure, so that the thickness of the interface layer is reduced, which is conducive to reducing the impurity defects in the interface layer, thereby reducing the density of interface trap (Dit) at the interface between the channel layer structure and the gate dielectric layer, and further improving the performance of the semiconductor structure; and the oxygen adsorption layer covers the gate dielectric layer, and the first annealing treatment is performed on the oxygen adsorption layer, the gate dielectric layer and the interface layer, compared with the scheme of forming an oxygen adsorption layer covering the interface layer, performing annealing treatment on the interface layer and the oxygen adsorption layer, and then forming a gate dielectric layer, the embodiment of the present application can avoid the problem of introducing oxygen ions into the interface layer again by post deposition annealing (PDA) treatment after the deposition of the gate dielectric layer, so that the effect of reducing the density of interface trap at the interface between the channel layer structure and the gate dielectric layer is remarkable. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figures 1 to 9 is the structure schematic diagram corresponding to each step in the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0023] As known from the background, the introduction of the high-k metal gate is conducive to reducing the leakage current of the semiconductor device. However, the performance of the semiconductor structure still needs to be improved.

[0024] It is found that an interfacial layer (IL) is usually formed between the high-k gate dielectric layer and the channel layer structure, which helps to maintain the interface state characteristics of the channel layer structure and form an interface with good electrical properties. Since the IL usually covers the surface of the channel layer structure and has a small distance from the transistor channel, the quality of the IL will affect the performance of the device.

[0025] Specifically, a method for forming a semiconductor structure includes: providing a substrate, the substrate having a channel layer structure formed thereon; performing an oxidation treatment on the surface of the channel layer structure to form an interfacial layer on the surface of the channel layer structure; forming a high-k gate dielectric layer covering the interfacial layer; forming a work function layer covering the high-k gate dielectric layer, and a gate electrode layer covering the work function layer.

[0026] The interfacial layer is formed by performing an oxidation treatment on the channel layer structure, so the material of the interfacial layer at least contains one of the elements of the material of the channel layer structure, and the material of the interfacial layer contains oxygen elements. For example, when the material of the channel layer structure is silicon germanium (SiGe), the material of the interfacial layer is oxygen-containing silicon germanium (SiGeO2). X Ge 1-X O2).

[0027] After the interfacial layer is formed on the surface of the channel layer structure and before the high-k gate dielectric layer is formed, the method usually further includes: performing a first annealing treatment on the interfacial layer in an atmosphere of ammonia (NH3); and performing a second annealing treatment on the interfacial layer in an atmosphere of hydrogen (H2) after the first annealing treatment. The hydrogen provided by the first annealing treatment and the second annealing treatment combines with the oxygen in the interfacial layer to reduce the content of oxygen ions in the interfacial layer. Accordingly, the same part atoms as the material elements of the channel layer structure in the interfacial layer cannot form a chemical bond with oxygen, and the unbound atoms among the same part atoms as the material elements of the channel layer structure diffuse to the surface of the channel layer structure. Therefore, the interfacial layer is reduced during the first annealing treatment and the second annealing treatment, and the material layer formed after the reduction of the interfacial layer at the interface between the interfacial layer and the channel layer structure becomes part of the channel layer structure, thereby achieving the effect of thinning the interfacial layer. The reduction of the thickness of the interfacial layer is conducive to reducing the impurity defects in the interfacial layer, thereby reducing the interface state density at the interface between the channel layer structure and the gate dielectric layer.

[0028] Taking the material of the channel layer structure as SiGe for example, the material of the formed interfacial layer is oxygen-containing silicon germanium (SiGeO2). X Ge 1-XO2), wherein, compared with the chemical bond energy between Ge and O, the chemical bond energy between Si and O is stronger, thus, during the annealing process, the chemical bond between Ge and O is easier to break, resulting in that the O atom originally bonded with Ge combines with H atom, and Ge atom diffuses to the surface of the channel layer structure, thereby forming a Ge layer on the surface of the SiGe layer, so that the thickness of the interface layer is reduced, and the material of the interface layer is converted from oxygen-containing silicon germanium to nitrogen-containing silicon monoxide.

[0029] However, after forming the high-k gate dielectric layer, a post deposition annealing (PDA) process is usually performed, that is, an annealing process performed after forming the high-k gate dielectric layer, under the influence of the annealing process, oxygen in the annealing environment is easy to diffuse into the interface layer and at the interface between the interface layer and the channel layer structure at high temperature, and oxidize the channel layer structure and the interface layer again, thereby reducing the material of the interface layer to the initial material, and causing the thickness of the interface layer to increase.

[0030] In summary, the post deposition annealing (PDA) process performed after forming the high-k gate dielectric layer is easy to cause the effect of the annealing process on the interface layer to be poor, or even fail.

[0031] To solve the technical problem, an embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, wherein the substrate is formed with a channel layer structure; performing an oxidation process on the surface of the channel layer structure to form an interface layer on the surface of the channel layer structure; forming a gate dielectric layer covering the interface layer; forming an oxygen adsorption layer covering the gate dielectric layer, wherein the oxygen adsorption layer is adapted to adsorb oxygen ions in the interface layer; performing a first annealing process on the oxygen adsorption layer, the gate dielectric layer and the interface layer, wherein the first annealing process is adapted to make the oxygen ions in the interface layer diffuse into the oxygen adsorption layer, and the oxygen adsorption layer adsorbs the oxygen ions during the first annealing process; and removing the oxygen adsorption layer after the first annealing process.

[0032] In the forming method, the interface layer is formed by oxidizing the surface of the channel layer structure, and the material of the interface layer at least contains one of the elements of the material of the channel layer structure. In the first annealing process, the interface layer and the oxygen adsorption layer have a redox reaction, the oxygen ions in the interface layer diffuse into the oxygen adsorption layer, fill into the corresponding oxygen vacancies in the oxygen adsorption layer, and are adsorbed by the oxygen adsorption layer, and the content of the oxygen ions in the interface layer is reduced, which makes the part of the atoms in the interface layer that are the same as the material elements of the channel layer structure unable to form a chemical bond with oxygen, and the unbound atoms among the part of the atoms in the interface layer that are the same as the material elements of the channel layer structure diffuse to the surface of the channel layer structure. Therefore, the interface layer is reduced in the first annealing process, and at the interface between the interface layer and the channel layer structure, the material layer formed after the reduction of the interface layer becomes part of the channel layer structure, so that the thickness of the interface layer is reduced, which is conducive to reducing the impurity defects in the interface layer, thereby reducing the interface state density (Dit) at the interface between the channel layer structure and the gate dielectric layer, and further improving the performance of the semiconductor structure. Moreover, the oxygen adsorption layer covers the gate dielectric layer, and the first annealing process is performed on the oxygen adsorption layer, the gate dielectric layer and the interface layer. Compared with the scheme of forming the oxygen adsorption layer covering the interface layer, annealing the interface layer and the oxygen adsorption layer, and then forming the gate dielectric layer, the embodiment of the present application can avoid the problem of introducing oxygen ions into the interface layer again in the post deposition annealing (PDA) process after the deposition of the gate dielectric layer, so that the effect of reducing the content of oxygen ions in the interface layer is remarkable.

[0033] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0034] Figures 1 to 9 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.

[0035] Reference Figure 1 , a substrate 100 is provided, and the substrate 100 has a channel layer structure 110 formed thereon.

[0036] The substrate 100 is used to provide a process platform for subsequent processes.

[0037] In this embodiment, the substrate 100 is a bulk substrate.

[0038] Specifically, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials. In other embodiments, the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0039] The substrate 100 is used to form a transistor, which includes one or both of a PMOS transistor and an NMOS transistor.

[0040] As the feature size of a device is continuously reduced, the transistor is transitioned from a planar transistor to a three-dimensional transistor, thereby improving the control ability of the gate structure of the device on the channel and improving the short channel effect.

[0041] Therefore, the substrate 100 is formed with a channel layer structure 110. In operation of the device, the channel layer structure 110 is used to provide a conductive channel of the transistor.

[0042] In this embodiment, the number of the channel layer structures 110 is multiple, and the multiple channel layer structures 110 are arranged in parallel and spaced apart.

[0043] As an example, the formed transistor is a fin field effect transistor (FinFET), and accordingly, the channel layer structure 110 is a fin protruding from the substrate 100.

[0044] In this embodiment, the material of the fin is the same as the material of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other semiconductor materials suitable for forming a fin, and the material of the fin can also be different from the material of the substrate.

[0045] In other embodiments, when the formed transistor is a gate-all-around (GAA) transistor or a fork sheet transistor, the channel layer structure is spaced apart from the substrate, and the channel layer structure includes one or more channel layers spaced apart in the normal direction of the surface of the substrate.

[0046] In this embodiment, taking the formed transistor as a PMOS transistor as an example, the material of the channel layer structure 110 is SiGe.

[0047] By using the SiGe material, the negative bias temperature instability (NBTI) problem of the PMOS transistor is improved, thereby improving the performance of the PMOS transistor.

[0048] In some embodiments, the material of the channel layer structure is Ge. Ge has higher bulk hole mobility than silicon and other III-V semiconductors.

[0049] In other embodiments, the material of the channel layer structure can also be Si.

[0050] Specifically, taking the fin as an example, the step of forming the channel layer structure 110 includes: using an epitaxial process to form a channel material layer on the surface of the base 100 (not shown in the figure); and patterning the channel material layer to form discrete channel layer structures 110 on the base 100.

[0051] The channel material layer is epitaxially grown based on the surface of the base 100, which is conducive to improving the formation quality and thickness uniformity of the channel material layer.

[0052] In this embodiment, the forming method further includes: forming an isolation layer 101 on the exposed base 100 of the channel layer structure 110.

[0053] The isolation layer 101 is used to achieve isolation between adjacent devices.

[0054] In this embodiment, the isolation layer 101 is a shallow trench isolation (STI).

[0055] The material of the isolation layer 101 is an insulating material, which includes silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon oxide.

[0056] It should be noted that in this embodiment, the device gate structure of the transistor formed is a metal gate structure, and the metal gate structure is formed using a high-k last metal gate last process; therefore, an interlayer dielectric layer (not shown in the figure) is also formed on the isolation layer 101, a gate opening (not shown in the figure) exposing the channel layer structure 110 is formed in the interlayer dielectric layer, and source / drain doping layers (not shown in the figure) are formed in the channel layer structure 110 on both sides of the gate opening.

[0057] The gate opening is formed by removing a dummy gate structure.

[0058] The specific description of the interlayer dielectric layer, the source / drain doping layer, and the dummy gate structure is not repeated here.

[0059] Continuing to refer to Figure 1The surface of the channel layer structure 110 is subjected to an oxidation treatment to form an interface layer 120 on the surface of the channel layer structure 110.

[0060] Subsequently, a gate dielectric layer is formed on the interface layer 120, and the interface layer 120 provides a good interface basis for the formation of the gate dielectric layer, thereby improving the quality of the formed gate dielectric layer and reducing the interface state density between the gate dielectric layer and the channel layer structure 110.

[0061] In addition, the interface layer 120 and the gate dielectric layer are used to constitute a gate dielectric layer stack in a device gate structure.

[0062] In the embodiment, the interface layer 120 is formed by subjecting the surface of the channel layer structure 110 to an oxidation treatment, which is advantageous in improving the formation quality of the interface layer 120 compared with a scheme of forming the interface layer by deposition, so that the interface performance between the interface layer 120 and the channel layer structure 110 is excellent.

[0063] Correspondingly, the material of the interface layer 120 at least contains one of the elements of the material of the channel layer structure 110.

[0064] The oxidation treatment process includes an in-situ steam generation (ISSG) process, a chemical oxidation process, or a thermal oxidation process.

[0065] In the embodiment, the oxidation treatment process is a chemical oxidation process.

[0066] By adopting the chemical oxidation process to form the interface layer 120, the interface layer 120 and the channel layer structure 110 are in close contact, so that the interface performance between the interface layer 120 and the channel layer structure 110 is excellent.

[0067] Specifically, the chemical oxidation process can be a chemical dip process. By adopting the chemical dip to form the interface layer 120, it is advantageous to improve the interface state between the interface layer 120 and the subsequently formed gate dielectric layer, and to improve the properties of the gate dielectric layer.

[0068] As an example, a mixed solution of deionized water and ozone is used to dip the channel layer structure 110.

[0069] In the embodiment, the material of the channel layer structure 110 is SiGe, and correspondingly, the material of the interface layer 120 is oxygen-containing silicon germanium (SiGeO2). X Ge 1-X O2).

[0070] In some embodiments, the material of the channel layer structure is Ge, and the material of the interface layer is germanium oxide (GeO2).

[0071] In other embodiments, the material of the channel layer structure is Si, and the material of the interface layer is silicon oxide (SiO2).

[0072] It should be noted that, in the process of oxidizing the surface of the channel layer structure 110, the oxidation process only acts on the semiconductor material, and therefore, the interface layer 120 is only formed on the surface of the channel layer structure 110 exposed by the isolation layer 101.

[0073] It should also be noted that, after the interface layer 120 is formed, the method further includes: performing a third annealing process on the interface layer 120 in an atmosphere of ammonia (NH3); and performing a fourth annealing process on the interface layer 120 in an atmosphere of hydrogen (H2) after the third annealing process.

[0074] The hydrogen provided by the third annealing process and the fourth annealing process combines with the oxygen in the interface layer 120 and forms chemical bonds. Accordingly, the part of the atoms in the interface layer 120 that are the same as the material elements of the channel layer structure 110 cannot form chemical bonds with oxygen. Among the part of the atoms in the interface layer 120 that are the same as the material elements of the channel layer structure 110, the unbound atoms diffuse to the surface of the channel layer structure 110. Therefore, the interface layer 120 is reduced during the third annealing process and the fourth annealing process, and at the interface between the interface layer 120 and the channel layer structure 110, the material layer formed after the reduction of the interface layer 120 becomes part of the channel layer structure 110. Thus, the interface layer 120 is thinned, and the reduction of the thickness of the interface layer 120 is conducive to reducing the impurity defects in the interface layer 120, thereby reducing the interface state density between the channel layer structure 110 and the subsequent gate dielectric layer.

[0075] In some embodiments, the third annealing process is performed on the interface layer 120 in an atmosphere of ammonia, so as to dope nitrogen into the interface layer 120, thereby increasing the dielectric constant (k) value of the interface layer 120, and improving the leakage current problem while reducing the physical thickness of the interface layer 120.

[0076] Referring to Figure 2 , a gate dielectric layer 130 is formed covering the interface layer 120.

[0077] The gate dielectric layer 130 and the interface layer 120 constitute a gate dielectric stack, which is used to achieve electrical isolation between the gate electrode layer and the channel.

[0078] In this embodiment, the device gate structure of the transistor is a metal gate structure, and therefore the gate dielectric layer 130 includes at least a high-k gate dielectric layer.

[0079] As an example, the gate dielectric layer 130 is a high-k gate dielectric layer.

[0080] The high-k gate dielectric layer is made of a high-k gate dielectric material (dielectric constant greater than 3.9). Specifically, the high-k gate dielectric material includes one or more of HfO2, ZrO2, HfSiO, HfSiN, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, and La2O3.

[0081] In this embodiment, the high-k gate dielectric layer is a single-layer structure, and the material of the high-k gate dielectric layer is HfO2.

[0082] In other embodiments, the high-k gate dielectric layer can also be a stacked-layer structure. For example, the high-k gate dielectric layer includes an Al2O3 layer and a HfO2 layer covering the Al2O3 layer.

[0083] In other embodiments, according to the performance requirements of the device, the gate dielectric layer can also include a dielectric layer with a dielectric constant less than 3.9. For example, before forming the high-k gate dielectric layer, a gate oxide layer (e.g., a silicon oxide layer) covering the interface layer can also be formed by deposition, and then a high-k gate dielectric layer covering the gate oxide layer is formed, and the high-k gate dielectric layer and the gate oxide layer constitute a stacked-layer gate dielectric layer.

[0084] According to the process requirements and the material of the gate dielectric layer 130, the formation process of the gate dielectric layer 130 includes an atomic layer deposition (ALD) process, a metal organic chemical vapor deposition (MOCVD) process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process.

[0085] In this embodiment, an atomic layer deposition process is used to form the gate dielectric layer 130.

[0086] The atomic layer deposition process has a low process temperature, which is beneficial to reduce the impact on the performance of the device. Moreover, the atomic layer deposition process has good step coverage, which is beneficial to improve the thickness uniformity and conformal coverage of the gate dielectric layer 130, and the surface of the gate dielectric layer 130 is tightly combined with the interface layer 120.

[0087] In this embodiment, the gate dielectric layer 130 conformally covers the bottom and sidewall of the gate opening (not shown in figure) and also covers the top of the ILD layer.

[0088] Specifically, the gate dielectric layer 130 conformally covers the surface of the interface layer 120 exposed by the gate opening and the top of the isolation layer 101.

[0089] In this embodiment, after forming the gate dielectric layer 130, the forming method further comprises: performing a second annealing process on the gate dielectric layer 130.

[0090] Specifically, the second annealing process is a post deposition annealing (PDA) process.

[0091] The second annealing process is used to repair the gate dielectric layer 130, thereby reducing oxygen vacancies and charge traps in the gate dielectric layer 130, and further improving the quality and density of the gate dielectric layer 130, and accordingly improving the electrical performance and reliability performance of the formed semiconductor structure, for example, the positive bias temperature instability (PBTI) of NMOS transistor.

[0092] As an example, the gas used in the second annealing process is ammonia.

[0093] In this embodiment, the second annealing process is performed by using a low-temperature furnace tube annealing process. The annealing temperature of the low-temperature furnace tube annealing process is relatively low, which is beneficial to reduce the influence on the substrate 100 or the distribution of the easily doped ions in the channel layer structure 110, and is also beneficial to improve the uniformity of the annealing effect.

[0094] In other embodiments, the process of the second annealing process can also be a spike anneal process, a laser anneal process or a flash anneal process.

[0095] In combination with reference to Figure 3 and Figure 4 , Figure 4 is Figure 3 an enlarged view in the dashed box in FIG. 13B, an oxygen adsorption layer 140 covering the gate dielectric layer 130 is formed, and the oxygen adsorption layer 140 is adapted to adsorb oxygen ions in the interface layer 120.

[0096] Subsequently, the oxygen adsorption layer 140, the gate dielectric layer 130 and the interface layer 120 are subjected to a first annealing treatment, which is suitable for diffusing the oxygen ions in the interface layer 120 into the oxygen adsorption layer 140, and in the first annealing treatment, the oxygen adsorption layer 140 adsorbs the oxygen ions, so that a redox reaction occurs between the interface layer 120 and the oxygen adsorption layer 140, thereby reducing the thickness of the interface layer 120, which is correspondingly conducive to reducing the density of interface traps (Dit) at the interface between the channel layer structure 110 and the gate dielectric layer 130.

[0097] In the embodiment, the material of the oxygen adsorption layer 140 is selected as follows: in the process of the redox reaction between the interface layer 120 and the oxygen adsorption layer 140, the change in Gibbs free energy of the material of the oxygen adsorption layer 140 is positive; in addition, in the subsequent first annealing treatment, the probability of the redox reaction between the oxygen adsorption layer 140 and the gate dielectric layer 130 is low.

[0098] In view of the above factors, in the embodiment, the material of the oxygen adsorption layer 140 includes one or more of Ta, Ti, TiN, TaN, TiAl, TaAl, AlN and W.

[0099] Moreover, by selecting the above-mentioned material, the reaction layer formed after the oxidation of the oxygen adsorption layer 140 can be retained and used as a barrier layer covering the gate dielectric layer 130, and in addition, the barrier layer formed by the material has high density and good barrier effect.

[0100] As an example, the material of the oxygen adsorption layer 140 is TiN.

[0101] In the embodiment, the deposition process is used to form the oxygen adsorption layer 140, and the oxygen partial pressure in the deposition process is less than that in the oxidation process used to form the interface layer 120, so that the oxygen adsorption layer 140 has strong adsorption capacity for oxygen ions.

[0102] Here, the partial pressure refers to the pressure component of a single gas in a mixed gas in a process chamber. The partial pressure corresponds to the pressure exerted by a single gas occupying the entire volume space on the total pressure. Correspondingly, the environmental oxygen partial pressure refers to the pressure component of oxygen in a mixed gas in a process chamber.

[0103] Therefore, when forming the oxygen adsorption layer 140, the lower the ambient oxygen partial pressure, the more oxygen vacancies in the oxygen adsorption layer 140, and the stronger the adsorption capacity of the oxygen adsorption layer 140 to oxygen ions.

[0104] In this embodiment, the oxygen adsorption layer 140 is formed by a physical vapor deposition process.

[0105] The physical vapor deposition process is usually carried out in a vacuum environment, so the ambient oxygen partial pressure of the physical vapor deposition process is low, which makes the oxygen adsorption layer 140 have more oxygen vacancies, thereby improving the adsorption capacity of the oxygen adsorption layer 140 to oxygen ions.

[0106] It should be noted that the thickness of the oxygen adsorption layer 140 should not be too small or too large. If the thickness of the oxygen adsorption layer 140 is too small, the thickness of the interface layer 120 that can be reduced during the subsequent first annealing process is too small, so that the thickness reduction of the interface layer 120 by the subsequent first annealing process is limited, or it is easy to cause that the gate dielectric layer 130 at some positions is not formed with an oxygen adsorption layer 140 of sufficient thickness, thereby causing the uniformity of the effect of the subsequent first annealing process to be poor; if the thickness of the oxygen adsorption layer 140 is too large, after the subsequent first annealing process, it is easy to cause the thickness of the unreacted oxygen adsorption layer 140 to be too large, thereby increasing the process difficulty and the required process time for removing the unreacted oxygen adsorption layer 140. Therefore, in this embodiment, the thickness of the oxygen adsorption layer 140 is 1 to 30. For example, the thickness of the oxygen adsorption layer 140 is 1 to 20, 1 to 10, 1 to 5, 1 to 3, 1 to 2, 2 to 5, 5 to 10, 10 to 20, or 20 to 30. or

[0107] It should also be noted that the oxygen adsorption layer 140 will also be removed after the first annealing process, so the conformal coverage capability of the oxygen adsorption layer 140 is not required in this embodiment.

[0108] Reference is made to Figure 5 , Figure 5 is based on Figure 4 schematic diagram, the oxygen adsorption layer 140, the gate dielectric layer 130 and the interface layer 120 are subjected to a first annealing process, the first annealing process is suitable for diffusing the oxygen ions in the interface layer 120 into the oxygen adsorption layer 140, and during the first annealing process, the oxygen adsorption layer 140 adsorbs the oxygen ions.

[0109] In the process of the first annealing treatment, a redox reaction occurs between the interface layer 120 and the oxygen adsorption layer 140, oxygen ions in the interface layer 120 diffuse into the oxygen adsorption layer 140, fill into corresponding oxygen vacancies in the oxygen adsorption layer 140, and are adsorbed by the oxygen adsorption layer 140, and the content of oxygen ions in the interface layer 120 decreases, which makes part of atoms in the interface layer 120 that are the same as the material elements of the channel layer structure 110 unable to form chemical bonds with oxygen. Correspondingly, among the part of atoms in the interface layer 120 that are the same as the material elements of the channel layer structure 110, unbound atoms diffuse to the surface of the channel layer structure 110, and therefore, the interface layer 120 is reduced in the process of the first annealing treatment, and at the interface between the interface layer 120 and the channel layer structure 110, the material layer formed after the reduction of the interface layer 120 becomes part of the channel layer structure 110, which reduces the thickness of the interface layer 120, and accordingly, is beneficial to reducing impurity defects in the interface layer 120, thereby being beneficial to reducing the interface state density (Dit) between the channel layer structure 110 and the gate dielectric layer 130, and further improving the performance of the semiconductor structure.

[0110] wherein an annealing process is employed to provide sufficient thermodynamic driving force.

[0111] Furthermore, compared with the scheme of forming an oxygen adsorption layer covering the interface layer, and performing annealing treatment on the interface layer and the oxygen adsorption layer, and then forming the gate dielectric layer, the embodiment forms the oxygen adsorption layer 140 after forming the gate dielectric layer 130, and then performs the first annealing treatment, thereby avoiding the problem of introducing oxygen ions into the interface layer 120 again in the gate dielectric layer deposition and annealing (PDA) treatment, and making the effect of reducing the interface state density between the channel layer structure 110 and the gate dielectric layer 130 remarkable.

[0112] In the embodiment, taking SiGe as an example for the material of the channel layer structure 110, the material of the interface layer 120 is oxygen-containing silicon germanium (SiGe X Ge 1-X O2), wherein the chemical bond energy between Si and O is stronger than that between Ge and O, and therefore, in the process of the second annealing treatment, the chemical bond between Ge and O is more easily broken, which causes the O atoms originally bonded with Ge to be driven to diffuse into the oxygen adsorption layer 140 and be adsorbed by the oxygen adsorption layer 140, and to have an oxidation reaction with the oxygen adsorption layer 140, and unbound Ge diffuses to the surface of the channel layer structure 110, thereby reducing part of the interface layer 120 into a Ge layer (not shown in the figure), which is formed on the surface of the channel layer structure 110 and is part of the channel layer structure 110.

[0113] It should be noted that when the material of the channel layer structure 110 is SiGe or Ge, after the interface layer 120 is formed by oxidizing the SiGe or Ge, the interface layer 120 contains Ge-O bonds, and because the band gap of GeO is narrow, the interface state density between the channel layer structure 110 and the gate dielectric layer 130 is large. Therefore, by breaking the chemical bond between Ge and O to reduce the Ge-O bond, the interface state density between the channel layer structure 110 and the gate dielectric layer 130 can be significantly reduced.

[0114] In this embodiment, during the first annealing process, the oxygen ions in the interface layer 120 diffuse into the surface of the oxygen adsorption layer 140 facing the gate dielectric layer 130 to form a barrier layer 150, which is located between the gate dielectric layer 130 and the oxygen adsorption layer 140 on the sidewall of the channel layer structure 110 and between the gate dielectric layer 130 and the oxygen adsorption layer 140 on the top of the channel layer structure 110.

[0115] In this embodiment, the material of the oxygen adsorption layer 140 includes one or more of Ta, Ti, TiN, TaN, TiAl, TaAl, AlN, and W, so that the barrier layer 150 can be retained subsequently.

[0116] The oxygen ions in the interface layer 120 diffuse into the surface of the oxygen adsorption layer 140 facing the gate dielectric layer 130 to form a barrier layer 150 between the gate dielectric layer 130 and the remaining oxygen adsorption layer 140, so that the barrier layer 150 can conformally cover the sidewall and the top of the channel layer structure 110, and the conformal covering ability and thickness uniformity of the barrier layer 150 are better.

[0117] As an example, the material of the oxygen adsorption layer 140 is TiN, and correspondingly, the material of the barrier layer 150 is TiON.

[0118] In this embodiment, the gas used in the first annealing process can be nitrogen or an inert gas, and the inert gas includes helium, argon, neon, etc.

[0119] The first annealing process includes a low-temperature furnace tube annealing process, a spike anneal process, a laser anneal process, or a flash anneal process.

[0120] In this embodiment, the first annealing process is a low-temperature furnace tube annealing process. The low-temperature furnace tube annealing process has a low annealing temperature, which is beneficial to improve the uniformity of the redox reaction, and is beneficial to reduce the influence on the distribution of the doped ions in the substrate 100 or the channel layer structure 110, and is beneficial to improve the uniformity of the annealing effect.

[0121] With reference to Figure 6 and Figure 7 , Figure 7 is Figure 6 an enlarged view in the dashed box in FIG. 1C, after the first annealing process, the oxygen adsorption layer 140 is removed (as shown in FIG. 1D). Figure 5

[0122] By removing the oxygen adsorption layer 140, the subsequent formation of other film layers in the device gate structure is prepared.

[0123] In this embodiment, a wet etching process is used to remove the oxygen adsorption layer 140.

[0124] The wet etching process has the characteristic of isotropic etching, so as to remove the oxygen adsorption layer 140 completely. In particular, the oxygen adsorption layer 140 is formed in the gate opening, and the oxygen adsorption layer 140 is located at the bottom and sidewall of the gate opening, and also at the top and sidewall of the channel layer structure 110.

[0125] In this embodiment, the etching solution used in the wet etching process includes an APM (mixture of ammonium and hydrogen peroxide) solution. The APM solution refers to a mixed solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O2).

[0126] The APM solution has high etching selectivity for metal and non-metal materials. The etching rate of the APM solution for metal is high, and the etching rate of the APM solution for dielectric material is low, so as to reduce the damage to the gate dielectric layer 130.

[0127] In particular, the material of the barrier layer 150 is metal oxide, so the etching rate of the APM solution for the barrier layer 150 is also low.

[0128] In this embodiment, after the oxygen adsorption layer 140 is removed, the barrier layer 150 is retained.

[0129] ​The barrier layer 150 not only protects the gate dielectric layer 130 and reduces damage to the gate dielectric layer 130 caused by subsequent processes, but also a work function layer covering the barrier layer 150 and a gate electrode layer covering the work function layer are formed subsequently. The barrier layer 150 is formed by oxidizing the oxygen adsorption layer 140, and the barrier layer 150 has a high density. Therefore, by retaining the barrier layer 150, the barrier layer 150 can block easily diffusing ions in the work function layer or the gate electrode layer, thereby reducing the probability of diffusion of the easily diffusing ions into the gate dielectric layer 130, and further improving the performance of the semiconductor structure.

[0130] With reference to Figure 8 and Figure 9 , Figure 9 is Figure 8 an enlarged view in the dashed box in FIG. 1C. After removing the oxygen adsorption layer 140 (as shown in FIG. 1D), the forming method further includes forming a work function layer 160 covering the gate dielectric layer 130 and a gate electrode layer 170 covering the work function layer 160. Figure 5

[0131] The work function layer 160 is used to adjust the threshold voltage of the formed transistor.

[0132] When forming a PMOS transistor, the work function layer 160 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. When forming an NMOS transistor, the work function layer 160 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0133] In this embodiment, the work function layer 160 is formed by an atomic layer deposition process.

[0134] The process temperature of the atomic layer deposition process is low, which is beneficial to reduce the impact on the performance of the device. Moreover, as the feature size of the device is continuously reduced, the transistor is transitioning from a planar transistor to a three-dimensional transistor, and the atomic layer deposition process has good step coverage, which is beneficial to improve the thickness uniformity and conformal coverage of the work function layer 160.

[0135] In this embodiment, the work function layer 160 conformally covers the bottom and sidewall of the gate opening (not shown in the figure) and also covers the top of the interlayer dielectric layer.

[0136] Specifically, the work function layer 160 conformally covers the barrier layer 150 and the gate dielectric layer 130 exposed by the gate opening.

[0137] ​The gate electrode layer 170 is used to lead out the electrical property of the device gate structure of the transistor. In this embodiment, the material of the gate electrode layer 170 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0138] In this embodiment, the gate electrode layer 170 fills in the gate opening and covers the work function layer 160, therefore, the forming method further comprises: planarizing the gate electrode layer 170, the work function layer 160 and the gate dielectric layer 130 with the top surface of the interlayer dielectric layer as the stop position, the gate electrode layer 170, the work function layer 160, the barrier layer 150, the gate dielectric layer 130 and the interface layer 120 in the gate opening are used to form the device gate structure.

[0139] In this embodiment, the channel layer structure 110 is a fin protruding from the substrate 100, therefore, the gate electrode layer 170 spans the fin and covers part of the top and part of the sidewall of the fin.

[0140] In other embodiments, when the channel layer structure is spaced apart from the substrate and the channel layer structure comprises one or more channel layers spaced apart in the direction of the surface normal of the substrate, the gate structure correspondingly covers part of the top of the channel layer structure and surrounds the channel layer.

[0141] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore, the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, a channel layer structure being formed on the substrate; performing an oxidation treatment on a surface of the channel layer structure to form an interface layer on the surface of the channel layer structure; forming a gate dielectric layer covering the interface layer; forming an oxygen adsorption layer covering the gate dielectric layer, the oxygen adsorption layer being adapted to adsorb oxygen ions in the interface layer; performing a first annealing treatment on the oxygen adsorption layer, the gate dielectric layer and the interface layer, the first annealing treatment being adapted to diffuse the oxygen ions in the interface layer into the oxygen adsorption layer, and during the first annealing treatment, the oxygen adsorption layer adsorbs the oxygen ions; wherein during the first annealing treatment, the oxygen ions in the interface layer diffuse into the surface of the oxygen adsorption layer towards the gate dielectric layer to form a barrier layer between the gate dielectric layer and the oxygen adsorption layer on the sidewall of the channel layer structure and between the gate dielectric layer and the oxygen adsorption layer on the top of the channel layer structure; after the first annealing treatment, removing the oxygen adsorption layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The oxygen adsorption layer is formed by a deposition process, and an ambient oxygen partial pressure of the deposition process is less than an ambient oxygen partial pressure of the oxidation treatment.

3. The method for forming a semiconductor structure according to claim 1 or 2, wherein The oxygen adsorption layer is formed by a physical vapor deposition process.

4. The method of claim 1, wherein, after the oxygen adsorption layer is removed, the barrier layer is retained.

5. The method of forming a semiconductor structure of claim 1, wherein, The material of the oxygen adsorption layer comprises one or more of Ta, Ti, TiN, TaN, TiAl, TaAl, AlN and W.

6. The method of forming a semiconductor structure of claim 1, wherein, The oxidation treatment comprises an in-situ steam generation process, a chemical oxidation process or a thermal oxidation process.

7. The method of forming a semiconductor structure of claim 1, wherein, The first annealing treatment comprises a low-temperature furnace tube annealing process, a spike annealing process, a laser annealing process or a flash annealing process.

8. The method of forming a semiconductor structure of claim 1, wherein, The oxygen adsorption layer is removed by a wet etching process.

9. The method of forming a semiconductor structure of claim 8, wherein, The etching solution used in the wet etching process comprises an APM solution.

10. The method of forming a semiconductor structure of claim 1, wherein, The gate dielectric layer comprises a high-k gate dielectric layer.

11. The method of forming a semiconductor structure of claim 1 or 10, wherein, After the gate dielectric layer covering the interface layer is formed, and before the oxygen adsorption layer covering the gate dielectric layer is formed, the method further comprises: performing a second annealing treatment on the gate dielectric layer.

12. The method of forming a semiconductor structure of claim 1, wherein, The thickness of the oxygen adsorption layer is to 13. The method of forming a semiconductor structure of claim 1, wherein, The material of the channel layer structure comprises SiGe, Ge or Si.

14. The method of forming a semiconductor structure of claim 1, wherein, After the oxygen adsorption layer is removed, the method further comprises: forming a work function layer covering the gate dielectric layer, and a gate electrode layer covering the work function layer.

15. The method of forming a semiconductor structure of claim 1, wherein, The channel layer structure is a fin protruding from the substrate. Alternatively, The channel layer structure is spaced apart from the substrate, and the channel layer structure comprises one or more channel layers spaced apart in a normal direction of a surface of the substrate. In the step of forming the gate dielectric layer covering the interface layer, the gate dielectric layer surrounds the channel layer.

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