Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, comprising: a substrate; a plurality of parallel gate structures disposed on the substrate; source / drain doped regions disposed within the substrate on either side of each gate structure; sidewall structures disposed on the sidewalls of the gate structures, the top surface of the sidewall structures being lower than the top surface of the gate structures; a conductive layer disposed on the source / drain doped regions, the conductive layer being isolated from the gate structures by the sidewall structures; and a barrier layer disposed on the conductive layer and the sidewall structures. The barrier layer and the sidewall structures in the semiconductor structure can collectively protect the top and sidewall surfaces of the conductive layer, thereby reducing damage to the conductive layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component or line that can be produced using a manufacturing process) has decreased. As technology nodes shrink, metal gates are used to replace the typical polysilicon gates to improve device performance. One process for forming metal gates is known as a replacement gate or "gate-last" process.

[0003] However, after forming the metal gate, there are still some challenges in how to effectively isolate the metal gate. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a plurality of parallel gate structures located on the substrate; source-drain doped regions located in the substrate on both sides of each gate structure; a sidewall structure located on the sidewall of the gate structure, the top surface of the sidewall structure being lower than the top surface of the gate structure; a conductive layer located on the source-drain doped regions, the conductive layer and the gate structure being isolated by the sidewall structure; and a barrier layer located on the conductive layer and the sidewall structure.

[0006] Optionally, the material of the barrier layer is different from that of the gate structure.

[0007] Optionally, the material of the barrier layer includes silicon carbide or silicon carbonitride.

[0008] Optionally, the etching rate of the material of the conductive layer is different from that of the gate structure material.

[0009] Optionally, the material of the conductive layer includes metal, and the metal includes cobalt.

[0010] Optionally, a top surface of the spacer structure is 10 nanometers to 40 nanometers lower than a top surface of the gate structure.

[0011] Optionally, it further includes: an isolation structure located within a portion of the gate structure, wherein the isolation structure is located on a portion of the sidewall of the spacer structure and the sidewall of the barrier layer.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of gate structures and source-drain doped regions, wherein the sidewalls of the gate structure have an initial sidewall structure, and the plurality of gate structures are arranged in parallel in a direction parallel to the substrate surface, and the source-drain doped regions are located in the substrate on both sides of the gate structure; forming a conductive layer on the source-drain doped region, wherein the top surface of the conductive layer is lower than the top surface of the gate structure; removing part of the initial sidewall structure to form a sidewall structure, wherein the top surface of the sidewall structure is lower than the top surface of the gate structure, and the sidewall structure isolates the conductive layer and the gate structure; and forming a blocking layer on the conductive layer and the sidewall structure.

[0013] Optionally, before forming the conductive layer and the sidewall structure on the source and drain doped regions, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer is located on the sidewall of the gate structure.

[0014] Optionally, after forming the sidewall structure, the conductive layer is formed.

[0015] Optionally, the method for forming the sidewall structure includes: removing the dielectric layer on the source and drain doped regions, forming a first opening in the dielectric layer, wherein the first opening exposes the surface of the source and drain doped regions; forming a sacrificial layer in the first opening, wherein the top surface of the sacrificial layer is lower than the top surface of the initial sidewall structure; and removing the initial sidewall structure exposed by the sacrificial layer to form a sidewall structure.

[0016] Optionally, the method for forming the conductive layer includes: removing the sacrificial layer after forming the sidewall structure; forming an initial conductive layer in the first opening and on the sidewall structure; and etching back the initial conductive layer until the top surface of the sidewall structure is exposed to form the conductive layer.

[0017] Optionally, the method for forming the sacrificial layer includes: forming an initial sacrificial layer in the first opening; and etching back the initial sacrificial layer until a portion of the sidewall surface of the initial sidewall structure is exposed to form the sacrificial layer.

[0018] Optionally, the material of the sacrificial layer includes an amorphous material.

[0019] Optionally, after forming the conductive layer, the sidewall structure is formed.

[0020] Optionally, the method for forming the conductive layer and the sidewall structure includes: removing the dielectric layer on the source and drain doped regions, forming a first opening in the dielectric layer, wherein the first opening exposes the surface of the source and drain doped regions; forming an initial conductive layer in the first opening; etching back the initial conductive layer until a portion of the sidewall surface of the initial sidewall structure is exposed to form a conductive layer; and removing the initial sidewall structure exposed by the conductive layer to form the sidewall structure.

[0021] Optionally, the material of the barrier layer is different from that of the gate structure.

[0022] Optionally, the material of the barrier layer includes silicon carbide or silicon carbonitride.

[0023] Optionally, the material of the conductive layer and the material of the gate structure have different etching rates.

[0024] Optionally, the material of the conductive layer includes metal, and the metal includes cobalt.

[0025] Optionally, after forming the barrier layer, the method further includes: removing part of the gate structure, forming a third opening in the dielectric layer, wherein the third opening exposes part of the sidewall of the spacer structure and the sidewall of the barrier layer; and forming an isolation structure in the third opening.

[0026] Optionally, the method for removing part of the gate structure includes: forming a patterned layer on the barrier layer and the gate structure, wherein the patterned layer exposes part of the gate structure surface and part of the barrier layer surface; and etching the gate structure using the patterned layer as a mask until the substrate surface is exposed.

[0027] Optionally, a top surface of the spacer structure is 10 nanometers to 40 nanometers lower than a top surface of the gate structure.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] In the semiconductor structure in the technical solution of the present invention, the top surface of the sidewall structure is lower than the top surface of the gate structure, and the barrier layer is located on the conductive layer and the sidewall structure. Therefore, when part of the gate structure is subsequently removed, the barrier layer and the sidewall structure can jointly protect the top surface and sidewall surface of the conductive layer, reduce damage to the conductive layer, and thereby improve the performance of the semiconductor structure.

[0030] The method for forming a semiconductor structure in the technical solution of the present invention first removes part of the initial sidewall structure so that the top surface of the formed sidewall structure is lower than the top surface of the gate structure, then forms a conductive layer in part of the first opening, and then forms a barrier layer on the conductive layer and the sidewall structure, so that when part of the gate structure is subsequently removed, the barrier layer and the sidewall structure can jointly protect the conductive layer, thereby reducing the damage to the conductive layer caused by the process of removing part of the gate structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 and Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0032] Figures 3 to 10is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0033] Figure 11 and Figure 12 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the current metal gate manufacturing process still faces many challenges, which will now be analyzed and explained in conjunction with specific embodiments.

[0035] Figure 1 and Figure 2 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0036] Please refer to Figure 1 , providing a substrate 100; forming a plurality of parallel gate structures 101 on the substrate 100, wherein the sidewalls of the gate structures 101 have sidewalls (not labeled), and the top of the gate structures 101 has a barrier layer (not labeled); forming source and drain doped regions 102 in the substrate on both sides of the gate structures 101; forming a dielectric layer 103 on the substrate 100, wherein the dielectric layer 103 is located on the sidewalls of the gate structures 101; removing the dielectric layer 103 on the source and drain doped regions 102, and forming an opening (not shown) in the dielectric layer 103; forming a conductive layer 104 in the opening, wherein the conductive layer 104 is electrically connected to the source and drain doped regions 102.

[0037] Please refer to Figure 2 , forming a patterned layer 105 on the conductive layer 104 and the gate structure 101, wherein the patterned layer 105 exposes a portion of the surface of the gate structure 101; removing the gate structure 101 using the patterned layer 105 as a mask, and forming an opening 106 in the dielectric layer 103.

[0038] During the formation of the semiconductor structure, the patterned layer 105 is affected by the exposure accuracy and the overlay accuracy. The patterned layer 105 also exposes part of the sidewall structure and part of the conductive layer 104. In the process of removing the gate structure 101 using the patterned layer 105 as a mask, since the sidewall structure is only located on the side wall of the conductive layer 104, the removal process is likely to cause damage to the top surface of the exposed conductive layer 104, thereby affecting the subsequent conductive effect of the conductive layer 104, and further affecting the performance of the semiconductor structure.

[0039] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by first removing part of the initial sidewall structure so that the top surface of the formed sidewall structure is lower than the top surface of the gate structure, and then forming a conductive layer in part of the first opening, and forming a blocking layer in the second opening, so that the blocking layer is located on the conductive layer and the sidewall structure, so that when part of the gate structure is subsequently removed, the blocking layer and the sidewall structure can jointly protect the conductive layer, reduce damage to the conductive layer, and thereby improve the performance of the semiconductor structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 10 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0042] Please refer to Figure 3 , providing a substrate 200.

[0043] In this embodiment, the substrate 200 is made of silicon.

[0044] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0045] In this embodiment, the substrate 200 is a planar substrate. In other embodiments, the substrate includes a base and a plurality of fin structures located on the base.

[0046] Please refer to Figure 4 , forming several gate structures 201 and source-drain doped regions 203, the sidewalls of the gate structures 201 having initial sidewall structures 202, and the several gate structures 201 being arranged in parallel along a direction parallel to the surface of the substrate 200, and the source-drain doped regions 203 being located in the substrate 200 on both sides of the gate structures 201.

[0047] In this embodiment, the method further includes forming a dielectric layer 204 on the substrate 200 . The dielectric layer 204 is located on the sidewall of the gate structure 201 and on the source / drain doped regions 203 .

[0048] In this embodiment, the gate structure 201 is a metal gate.

[0049] The gate structure 201 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer. In this embodiment, the gate structure further includes a work function layer (not shown) located between the gate dielectric layer and the gate layer.

[0050] The material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0051] In other embodiments, the gate structure may also be a polysilicon gate.

[0052] The method for forming the gate structure 201, the initial sidewall structure 202 and the source-drain doped region 203 includes: forming a dummy gate structure (not shown) on a substrate 200; forming an initial sidewall structure 202 on the sidewall of the dummy gate structure; after forming the initial sidewall structure 202, forming a source-drain doped region 203 in the substrate on both sides of the dummy gate structure; after forming the source-drain doped region 203, forming a dielectric layer 204 on the substrate 200, wherein the dielectric layer 204 is located on the sidewall of the initial sidewall structure 202; removing the dummy gate structure, forming a gate opening (not shown) in the dielectric layer 204; and forming a gate structure 201 in the gate opening.

[0053] The material of the initial spacer 202 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the initial spacer 202 includes silicon nitride.

[0054] The source / drain doping region 203 has doping ions therein, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0055] The dielectric layer 204 is made of a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, and silicon carbon nitride oxide. In this embodiment, the dielectric layer 204 is made of silicon oxide.

[0056] Next, a conductive layer 209 is formed on the source-drain doped region 203, and the top surface of the conductive layer 209 is lower than the top surface of the gate structure 201; a portion of the initial sidewall structure 202 is removed to form a sidewall structure 207, and the top surface of the sidewall structure 207 is lower than the top surface of the gate structure 201. The sidewall structure 207 isolates the conductive layer 209 and the gate structure 201.

[0057] In this embodiment, after forming the spacer structure 207, the conductive layer 209 is formed. The formation process of the spacer structure 207 and the conductive layer 209 can be referred to Figures 5 to 8 .

[0058] Please refer to Figure 5 , the dielectric layer 204 on the source / drain doped region 203 is removed, and a first opening 205 is formed in the dielectric layer 204 , wherein the first opening 205 exposes the surface of the source / drain doped region 203 .

[0059] The method for forming the first opening 205 includes: forming a mask layer (not shown) on the dielectric layer 204 and the gate structure 201, wherein the mask layer exposes the surface of the dielectric layer 204 on the source / drain doped region 203; and etching the dielectric layer 204 using the mask layer as a mask until the surface of the source / drain doped region 203 is exposed.

[0060] The process of etching the dielectric layer 204 includes a dry etching process or a wet etching process.

[0061] Please refer to Figure 6 A sacrificial layer 206 is formed in the first opening 205 , and a top surface of the sacrificial layer 206 is lower than a top surface of the initial spacer structure 202 .

[0062] The sacrificial layer 206 serves as a mask for subsequently removing a portion of the initial spacer structure 202 .

[0063] The method for forming the sacrificial layer 206 includes: forming an initial sacrificial layer (not shown) in the first opening 205 ; and etching back the initial sacrificial layer until a portion of the sidewall surface of the initial spacer structure 202 is exposed to form the sacrificial layer 206 .

[0064] The material of the sacrificial layer 206 includes an amorphous material. In this embodiment, the material of the sacrificial layer 206 includes amorphous carbon.

[0065] Please continue to refer to Figure 6 , the initial spacer structure 202 exposed by the sacrificial layer 206 is removed to form a spacer structure 207 , wherein the top surface of the spacer structure 207 is lower than the top surface of the gate structure 201 .

[0066] The spacer structure 207 is used to electrically isolate the subsequently formed conductive layer 209 from the gate structure 201 .

[0067] The process of removing the initial spacer structure 202 exposed by the sacrificial layer 206 includes a dry etching process or a wet etching process.

[0068] In this embodiment, the top surface of the spacer structure 207 is 10 nm to 40 nm lower than the top surface of the gate structure 201 , thereby ensuring that the height of the subsequently formed conductive layer is within a preset range and that the conductive layer has good conductive effect.

[0069] Please refer to Figure 7 After forming the sidewall structure 207 , the sacrificial layer 206 is removed.

[0070] The process of removing the sacrificial layer 206 includes a dry etching process.

[0071] Please continue to refer to Figure 7 After removing the sacrificial layer 206 , an initial conductive layer 208 is formed in the first opening 205 and on the spacer structure 207 .

[0072] The method for forming the initial conductive layer 208 includes: forming a conductive material layer (not shown) in the first opening 205 , on the sidewall structure 207 and on the dielectric layer 204 ; and planarizing the conductive material layer until the surface of the dielectric layer 204 is exposed to form the initial conductive layer 208 .

[0073] The material of the initial conductive layer 208 includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and titanium nitride.

[0074] In this embodiment, the material of the initial conductive layer 208 includes cobalt. Metal cobalt has a relatively low resistivity, so when the resistance of the initial conductive layer 208 increases due to size reduction, the selection of metal cobalt as the material can reduce the resistance of the subsequently formed conductive layer.

[0075] The process of forming the conductive material layer includes a physical vapor deposition process, an electroplating process or a chemical plating process.

[0076] Please refer to Figure 8 , the initial conductive layer 208 is etched back until the top surface of the sidewall structure 207 is exposed, thereby forming the conductive layer 209 .

[0077] The material of the conductive layer 209 and the material of the gate structure 201 have different etching rates. Therefore, during the process of etching back the initial conductive layer 208 , the gate structure 201 is less damaged.

[0078] In this embodiment, before etching back the initial conductive layer 208 , the initial conductive layer 208 is further pre-processed.

[0079] The process of etching back the initial conductive layer 208 includes a dry etching process or a wet etching process.

[0080] In this embodiment, the process of etching back the initial conductive layer 208 includes a wet etching process. The wet etching process can better control the etching height and obtain a conductive layer 209 with a better surface morphology, which is beneficial to the good contact between other subsequent conductive structures and the conductive layer 209. At the same time, the wet etching process can have a larger etching selectivity ratio for the gate structure 201, so that the gate structure 201 is less damaged.

[0081] In this embodiment, the pretreatment is an oxidation treatment, and the parameters of the oxidation treatment include: a mixed solution of ammonia water, hydrogen peroxide and water in a volume ratio ranging from 1:1:5 to 1:1:20.

[0082] The parameters of the wet etching process include: the etching solution is a citric acid solution with a pH value of 2 to 8, and the chemical formula of the citric acid is C6H8O7.

[0083] In other embodiments, the process of etching back the initial conductive layer includes a dry etching process.

[0084] In other embodiments, the process parameters of the pretreatment include: the gas is a mixture of one or more of hydrogen, methane and nitrogen trifluoride gas and boron trichloride gas; and the pretreatment time is 3 seconds to 10 seconds.

[0085] The parameters of the dry etching process include: the gas is a mixture of argon and carbon fluoride gas, the carbon fluoride gas is one or both of methane and trifluoromethane; the bias voltage is 20 volts to 200 volts; the ion source power is 100 watts to 1500 watts; the pressure is 2 millitorr to 100 millitorr; and the time is 30 seconds to 60 seconds.

[0086] Please refer to Figure 9 , a barrier layer 210 is formed on the conductive layer 209 and the spacer structure 207 .

[0087] The method for forming the barrier layer 210 includes: forming a barrier material layer (not shown) on the conductive layer 209 , the sidewall structure 207 and the dielectric layer 204 ; and planarizing the barrier material layer until the surface of the dielectric layer 204 is exposed to form the barrier layer 210 .

[0088] The material of the barrier layer 210 is different from that of the gate structure 201 , so that when a portion of the gate structure 201 is subsequently removed, the barrier layer 210 can protect the conductive layer 207 from being damaged by the process of removing the gate structure 201 .

[0089] In this embodiment, the barrier layer 210 is made of silicon carbide or silicon carbonitride. Silicon carbide and silicon carbonitride have a dense structure and are relatively hard, so that the barrier layer 210 and the sidewall structure 207 can protect the conductive layer 209 together.

[0090] Please refer to Figure 10 After forming the barrier layer 210, the method further includes: removing part of the gate structure 201, forming a third opening (not shown) in the dielectric layer 204, wherein the third opening exposes part of the sidewall of the spacer structure 207 and the sidewall of the barrier layer 210; and forming an isolation structure 211 in the third opening.

[0091] The method for removing part of the gate structure 201 includes: forming a patterned layer (not shown) on the barrier layer and the gate structure, wherein the patterned layer exposes part of the surface of the gate structure 201 and part of the surface of the barrier layer 210; etching the gate structure 201 using the patterned layer as a mask until the surface of the substrate 200 is exposed.

[0092] The process of etching the gate structure 201 includes a dry etching process and a wet etching process or a combination of one or more of the above.

[0093] The material of the isolation structure 211 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the isolation structure 211 includes silicon nitride.

[0094] During the formation of the semiconductor structure, part of the initial sidewall structure 202 is first removed so that the top surface of the formed sidewall structure 207 is lower than the top surface of the gate structure 201, and then a conductive layer 209 is formed in part of the first opening 205, and then a barrier layer 210 is formed on the conductive layer 209 and the sidewall structure 207. When part of the gate structure 201 is subsequently removed, the barrier layer 210 and the sidewall structure 207 can jointly protect the conductive layer 209, thereby reducing the damage to the conductive layer 209 caused by the process of removing part of the gate structure 201, thereby improving the performance of the semiconductor structure.

[0095] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 10 ,include:

[0096] substrate 200;

[0097] A plurality of gate structures 201 arranged in parallel on a substrate 200;

[0098] Source and drain doped regions 203 located in the substrate 200 on both sides of each gate structure 201;

[0099] a spacer structure 207 located on a portion of a sidewall of the gate structure 201 , wherein a top surface of the spacer structure 207 is lower than a top surface of the gate structure 201 ;

[0100] A conductive layer 209 located on the source / drain doped region 203 , wherein the conductive layer 209 is isolated from the gate structure 201 by a spacer structure 207 ;

[0101] A barrier layer 210 is located on the conductive layer 209 and the spacer structure 207 .

[0102] In this embodiment, the material of the barrier layer 210 is different from that of the gate structure 201 .

[0103] In this embodiment, the material of the barrier layer 210 includes silicon carbide or silicon carbonitride.

[0104] In this embodiment, the material of the conductive layer 210 and the material of the gate structure 201 have different etching rates.

[0105] In this embodiment, the conductive layer 210 is made of metal, and the metal includes cobalt.

[0106] In this embodiment, the top surface of the spacer structure 207 is 10 nanometers to 40 nanometers lower than the top surface of the gate structure 201 .

[0107] In this embodiment, the present invention further includes: an isolation structure 211 located within a portion of the gate structure 201 , wherein the isolation structure 211 is located on a portion of the sidewalls of the spacer structure 207 and the sidewalls of the barrier layer 210 .

[0108] In the semiconductor structure, the top surface of the sidewall structure 207 is lower than the top surface of the gate structure 201, and the barrier layer 210 is located on the conductive layer 209 and the sidewall structure 207. Therefore, when part of the gate structure 201 is subsequently removed, the barrier layer 210 and the sidewall structure 207 can jointly protect the top surface and sidewall surface of the conductive layer 209, reduce the damage to the conductive layer 209, and thereby improve the performance of the semiconductor structure.

[0109] Figure 11 and Figure 12 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0110] In another embodiment, after forming the conductive layer, the sidewall structure is formed. For the formation method of the conductive layer and the sidewall structure, please refer to Figure 11 and Figure 12 .

[0111] Please refer to Figure 11 , Figure 11 For Figure 5 Based on the schematic diagram, an initial conductive layer (not shown) is formed in the first opening 205 ; the initial conductive layer is etched back until a portion of the sidewall surface of the initial spacer structure 202 is exposed to form a conductive layer 301 .

[0112] The method for forming the initial conductive layer includes: forming a conductive material layer (not shown) in the first opening 205 , on the initial sidewall structure 202 and on the dielectric layer 204 ; and planarizing the conductive material layer until the surface of the dielectric layer 204 is exposed to form the initial conductive layer.

[0113] The material of the initial conductive layer includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and titanium nitride.

[0114] In this embodiment, the material of the initial conductive layer includes cobalt. Metal cobalt has a relatively low resistivity, so when the resistance of the initial conductive layer increases due to size reduction, selecting the material of cobalt can reduce the resistance of the subsequently formed conductive layer.

[0115] The process of forming the conductive material layer includes a physical vapor deposition process, an electroplating process or a chemical plating process.

[0116] The material of the conductive layer 301 and the material of the gate structure 201 have different etching rates, so the gate structure 201 is less damaged during the process of etching back the initial conductive layer.

[0117] Please refer to the process of etching back the initial conductive layer Figure 8 , I will not go into details here.

[0118] Please refer to Figure 12 , removing the initial spacer structure 202 exposed by the conductive layer 301 to form the spacer structure 302 , wherein the top surface of the spacer structure 302 is lower than the top surface of the gate structure 201 .

[0119] The process of removing the initial spacer structure 202 exposed by the conductive layer 301 includes a dry etching process or a wet etching process.

[0120] In this embodiment, the top surface of the spacer structure 302 is 10 nanometers to 40 nanometers lower than the top surface of the gate structure 201 .

[0121] Next, a barrier layer is formed on the conductive layer 301 and the spacer structure 302. After the barrier layer is formed, a portion of the gate structure 201 is removed, and a third opening (not shown) is formed in the dielectric layer 204. The third opening exposes a portion of the sidewalls of the spacer structure 302 and the barrier layer. An isolation structure is formed in the third opening. For methods, processes, and materials for forming the barrier layer and isolation structure, please refer to Figure 9 and Figure 10 , I will not go into details here.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; A plurality of parallel gate structures are arranged on the substrate; source and drain doping regions located in the substrate on both sides of each gate structure; a spacer structure located on a sidewall of a portion of the gate structure, wherein a top surface of the spacer structure is lower than a top surface of the gate structure; a conductive layer located on the source / drain doped regions, wherein a top surface of the conductive layer is lower than a top surface of the gate structure, and the conductive layer and the gate structure are isolated by a sidewall structure; a barrier layer located on the conductive layer and the spacer structure, wherein a top surface of the barrier layer is lower than or flush with a top surface of the gate structure; An isolation structure is located within a portion of the gate structure, and the isolation structure is located on a portion of the sidewall of the spacer structure and the sidewall of the barrier layer.

2. The semiconductor structure according to claim 1, wherein The material of the barrier layer is different from that of the gate structure.

3. The semiconductor structure according to claim 2, wherein: The material of the barrier layer includes silicon carbide or silicon carbonitride.

4. The semiconductor structure according to claim 1, wherein: The material of the conductive layer and the material of the gate structure have different etching rates.

5. The semiconductor structure according to claim 4, wherein: The conductive layer is made of metal, and the metal includes cobalt.

6. The semiconductor structure according to claim 1, wherein The top surface of the spacer structure is 10 nanometers to 40 nanometers lower than the top surface of the gate structure.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of gate structures and source-drain doped regions, wherein the sidewalls of the gate structures have an initial sidewall structure, the plurality of gate structures are arranged in parallel along a direction parallel to the substrate surface, and the source-drain doped regions are located in the substrate on both sides of the gate structures; forming a conductive layer on the source-drain doped region, wherein a top surface of the conductive layer is lower than a top surface of the gate structure; removing a portion of the initial spacer structure to form a spacer structure, wherein a top surface of the spacer structure is lower than a top surface of the gate structure, and the spacer structure isolates the conductive layer and the gate structure; forming a barrier layer on the conductive layer and the spacer structure, wherein a top surface of the barrier layer is lower than or flush with a top surface of the gate structure; Removing a portion of the gate structure to form a third opening in the dielectric layer, wherein the third opening exposes a portion of the sidewall of the spacer structure and the sidewall of the barrier layer; An isolation structure is formed in the third opening.

8. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the conductive layer and the sidewall structure on the source and drain doped regions, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer is located on the sidewall of the gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming the sidewall structure, the conductive layer is formed.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the sidewall structure includes: removing the dielectric layer on the source and drain doped regions, forming a first opening in the dielectric layer, wherein the first opening exposes the surface of the source and drain doped regions; forming a sacrificial layer in the first opening, wherein the top surface of the sacrificial layer is lower than the top surface of the initial sidewall structure; and removing the initial sidewall structure exposed by the sacrificial layer to form the sidewall structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the conductive layer includes: removing the sacrificial layer after forming the sidewall structure; forming an initial conductive layer in the first opening and on the sidewall structure; and etching back the initial conductive layer until the top surface of the sidewall structure is exposed to form the conductive layer.

12. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the sacrificial layer includes: forming an initial sacrificial layer in a first opening; etching back the initial sacrificial layer until a portion of the sidewall surface of the initial sidewall structure is exposed to form the sacrificial layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the sacrificial layer includes an amorphous material.

14. The method for forming a semiconductor structure according to claim 8, wherein: After forming the conductive layer, the sidewall structure is formed.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the conductive layer and the sidewall structure includes: removing the dielectric layer on the source and drain doped regions, forming a first opening in the dielectric layer, and exposing the surface of the source and drain doped regions; forming an initial conductive layer in the first opening; etching back the initial conductive layer until a portion of the sidewall surface of the initial sidewall structure is exposed to form a conductive layer; and removing the initial sidewall structure exposed by the conductive layer to form the sidewall structure.

16. The method for forming a semiconductor structure according to claim 7, wherein: The material of the barrier layer is different from that of the gate structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: The material of the barrier layer includes silicon carbide or silicon carbonitride.

18. The method for forming a semiconductor structure according to claim 7, wherein: The material of the conductive layer and the material of the gate structure have different etching rates.

19. The method for forming a semiconductor structure according to claim 18, wherein: The conductive layer is made of metal, and the metal includes cobalt.

20. The method for forming a semiconductor structure according to claim 7, wherein: The method for removing part of the gate structure includes: forming a patterned layer on the barrier layer and the gate structure, the patterned layer exposing part of the gate structure surface and part of the barrier layer surface; etching the gate structure using the patterned layer as a mask until the substrate surface is exposed.

21. The method for forming a semiconductor structure according to claim 7, wherein: The top surface of the spacer structure is 10 nanometers to 40 nanometers lower than the top surface of the gate structure.

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