Semiconductor memory device

Abstract

Embodiments provide a high-quality semiconductor memory device. The semiconductor memory device according to the embodiments includes: a substrate; a plurality of first conductive layers and a plurality of first insulating layers alternately stacked in a first direction intersecting the surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers and the plurality of first insulating layers; a second semiconductor layer connected to one end portion of the first semiconductor layer in the first direction and extending in a second direction intersecting the first direction; a second insulating layer covering the outer peripheral surface of the other end portion of the first semiconductor layer; and a third insulating layer having a different position in the second direction from the plurality of first conductive layers, the plurality of first insulating layers, and the second insulating layer, extending in the first direction, and being in contact with the second semiconductor layer at one end in the first direction, and the other end in the first direction being farther from the second semiconductor layer than the second insulating layer. A metal oxide film is provided on the surface of the second insulating layer on the third insulating layer side in the second direction, and no metal oxide film is provided on the surface of the plurality of first insulating layers on the third insulating layer side in the second direction.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-156255 (filing date: September 17, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0002] This embodiment relates to a semiconductor memory device. Background Art

[0003] There is known a semiconductor memory device including a semiconductor substrate, a plurality of conductive layers laminated in a direction intersecting the surface of the semiconductor substrate, a semiconductor pillar extending in a direction intersecting the surface of the semiconductor substrate and facing the plurality of conductive layers, and a gate insulating film provided between the conductive layer and the semiconductor pillar. Summary of the Invention

[0004] An embodiment provides a high-quality semiconductor memory device.

[0005] A semiconductor memory device according to one embodiment includes: a substrate; a plurality of first conductive layers and a plurality of first insulating layers alternately laminated in a first direction intersecting the surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers and the plurality of first insulating layers; a second semiconductor layer connected to one end portion of the first semiconductor layer in the first direction and extending in a second direction intersecting the first direction; a second insulating layer covering the outer peripheral surface of the other end portion of the first semiconductor layer; and a third insulating layer having a position different from that of the plurality of first conductive layers, the plurality of first insulating layers, and the second insulating layer in the second direction, extending in the first direction, being in contact with the second semiconductor layer at one end in the first direction, and having the other end in the first direction farther from the second semiconductor layer than the second insulating layer. A metal oxide film is provided on the surface of the second insulating layer on the third insulating layer side in the second direction, and no metal oxide film is provided on the surface of the plurality of first insulating layers on the third insulating layer side in the second direction. Brief Description of the Drawings

[0006] Figure 1 、 Figure 2 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment.

[0007] Figure 3 is Figure 2 a schematic enlarged cross-sectional view of a portion indicated by A of

[0008] Figure 4 is Figure 2 a schematic enlarged cross-sectional view of a portion indicated by B of

[0009] Figures 5 to 16It is a schematic Y-Z cross-sectional view showing a first manufacturing method of a semiconductor memory device according to the first embodiment.

[0010] Figures 17 to 28 It is a schematic Y-Z cross-sectional view showing a second manufacturing method of a semiconductor memory device according to the first embodiment.

[0011] Figure 29 、 Figure 30 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first comparative example.

[0012] Figure 31 、 Figure 32 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the second comparative example.

[0013] Figure 33 It is a schematic cross-sectional view showing the structure of a semiconductor memory device according to the second embodiment.

[0014] Figures 34 to 38 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the second embodiment.

[0015] Figure 39 It is a schematic cross-sectional view showing the structure of a semiconductor memory device according to the third comparative example.

[0016] Figure 40 、 Figure 41 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the third comparative example.

[0017] Reference Numeral Explanation

[0018] 100... semiconductor substrate, 110... conductive layer, 120... semiconductor pillar, 130... gate insulating film, 150... inter-block structure Detailed Embodiment

[0019] Next, a semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. In addition, the following embodiments are merely examples and are not intended to limit the present invention.

[0020] In addition, in this specification, a predetermined direction parallel to the surface of the semiconductor substrate is referred to as the X direction, a direction parallel to the surface of the semiconductor substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the surface of the semiconductor substrate is referred to as the Z direction.

[0021] In addition, in this specification, the direction along a predetermined plane is sometimes referred to as the first direction, the direction along the predetermined plane and intersecting the first direction is referred to as the second direction, and the direction intersecting the predetermined plane is referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0022] In addition, in this specification, expressions such as "upper" and "lower" are based on the semiconductor substrate. For example, the direction away from the semiconductor substrate along the Z direction is referred to as upper, and the direction approaching the semiconductor substrate along the Z direction is referred to as lower. In addition, when referring to the lower surface or the lower end of a certain structure, it means the surface or the end on the semiconductor substrate side of the structure, and when referring to the upper surface or the upper end, it means the surface or the end on the side opposite to the semiconductor substrate of the structure. In addition, a plane intersecting the X direction or the Y direction is referred to as a side surface, etc.

[0023] In addition, in this specification, when it is mentioned that the first structure is "electrically connected" to the second structure, the first structure may be directly connected to the second structure, or the first structure may be connected to the second structure via wirings, semiconductor components, transistors, etc. For example, when three transistors are connected in series, even if the second transistor is in the cut-off (OFF) state, the first transistor is "electrically connected" to the third transistor.

[0024] In addition, when it is mentioned in this specification that the first structure is connected between the second structure and the third structure, it sometimes means that the first structure, the second structure, and the third structure are connected in series and the first structure is provided in the current path of the second structure and the third structure.

[0025] In addition, when it is mentioned in this specification that a circuit or the like makes two wirings or the like "conductive", for example, it sometimes means that the circuit or the like includes transistors or the like, the transistors or the like are provided in the current path between the two wirings, and the transistors or the like are in the conductive (ON) state.

[0026] [First Embodiment]

[0027] Hereinafter, the structure of the semiconductor memory device according to the first embodiment will be described with reference to the drawings. In addition, the following drawings are schematic, and for the sake of convenience of explanation, some structures may be omitted.

[0028] [Structure]

[0029] Figure 1 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 2 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 3 is Figure 2Schematic enlarged cross-sectional view of the portion represented by A. Figure 4 is Figure 2 Schematic enlarged cross-sectional view of the portion represented by B. In addition, in Figure 3 and Figure 4 also shown are components that are not shown in Figure 2 due to omission of illustration.

[0030] [Structure of semiconductor memory device]

[0031] As Figure 1 shown, the semiconductor memory device of this embodiment includes a semiconductor substrate 100 and a plurality of memory blocks BLK and inter-block structures 150 that are alternately arranged in the Y direction above the semiconductor substrate 100.

[0032] For example, as Figure 2 shown, the memory block BLK includes: a plurality of conductive layers 110 and a plurality of insulating layers 101 that are alternately stacked in the Z direction, a semiconductor pillar 120 that extends in the Z direction and faces the plurality of conductive layers 110 and the plurality of insulating layers 101, an insulating layer 102 that covers the outer peripheral surface of the upper end portion of the semiconductor pillar 120, and an etch stop portion 133A.

[0033] [Structure of semiconductor substrate 100]

[0034] Figure 1 and Figure 2 shown, the semiconductor substrate 100 is, for example, a semiconductor substrate formed of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, for example, provided are: an N-type well region (not shown) containing N-type impurities such as phosphorus (P), a P-type well region 100P containing P-type impurities such as boron (B), a semiconductor substrate region (not shown) where neither the N-type well region nor the P-type well region 100P is provided, and an insulating region (not shown).

[0035] [Structure of conductive layer 110 and insulating layer 101]

[0036] The conductive layer 110 is a substantially plate-shaped conductive layer that extends in the X direction. The conductive layer 110 is a metal film of molybdenum (Mo) in this embodiment, but may also be a metal film of tungsten (W), ruthenium (Ru), etc. An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction. In addition, for example, as Figure 3 shown, an insulating film 133B containing aluminum oxide (Al2O3) or other metal oxide films is provided between the conductive layer 110 and the insulating layer 101.

[0037] The plurality of conductive layers 110 are electrically independent for each memory block BLK and function as word lines, select gate lines, etc., respectively.

[0038] A conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110.

[0039] The conductive layer 111 functions as a select gate line or the like. The conductive layer 111 is electrically independent for each memory block BLK.

[0040] [Structure of semiconductor pillar 120]

[0041] As Figure 2 shown, the semiconductor pillar 120 extends in the Z direction and is arranged in a predetermined pattern in the X direction and the Y direction. The semiconductor pillar 120 functions as a channel region of a plurality of memory cells and select transistors.

[0042] The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. In addition, the outer peripheral surface of the semiconductor pillar 120 is surrounded by a plurality of conductive layers 110 and a plurality of insulating layers 101, and faces the plurality of conductive layers 110 and the plurality of insulating layers 101.

[0043] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end portion of the semiconductor pillar 120. The impurity region 121 is connected to the bit line via a contact portion 120C or the like.

[0044] The lower end portion of the semiconductor pillar 120 is connected to the P-type well region 100P of the semiconductor substrate 100 via a semiconductor layer 122 formed of single-crystalline silicon (Si) or the like. The semiconductor layer 122 functions as a channel region of a select transistor. The outer peripheral surface of the semiconductor layer 122 is surrounded by the conductive layer 111 and faces the conductive layer 111. An insulating layer 123 such as silicon oxide is provided between the semiconductor layer 122 and the conductive layer 111.

[0045] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120.

[0046] For example, as Figure 3 and Figure 4As shown, the gate insulating film 130 includes a tunneling insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor pillar 120 and the conductive layer 110. The tunneling insulating film 131 is an insulating film such as silicon oxide (SiO2), for example, the charge storage film 132 is a film capable of storing charges such as silicon nitride (Si3N4), and the block insulating film 133 is an insulating film containing aluminum oxide (Al2O3) or other metal oxide films, for example. The tunneling insulating film 131 and the charge storage film 132 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120. The block insulating film 133 is provided on the opposite surface of the conductive layer 110 to the semiconductor pillar 120 and is continuously formed with the insulating films 133B formed on the upper and lower surfaces of the conductive layer 110. The block insulating film 133 has a substantially cylindrical shape and faces the outer peripheral surface of the semiconductor pillar 120 with the tunneling insulating film 131 and the charge storage film 132 interposed therebetween.

[0047] In addition, in Figure 3 and Figure 4 an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride is shown. However, the gate insulating film 130 may also include a floating gate such as polysilicon containing N-type or P-type impurities, for example.

[0048] [Structure of the insulating layer 102]

[0049] As Figure 2 and Figure 4 shown, the upper surface of the laminate formed by alternately laminating a plurality of conductive layers 110 and a plurality of insulating layers 101 in the Z direction is covered by the insulating layer 102. The insulating layer 102 is formed of silicon oxide (SiO2) or the like. The insulating layer 102 covers the outer peripheral surface of the upper end portion of the semiconductor pillar 120 with the gate insulating film 130 (the tunneling insulating film 131 and the charge storage film 132) interposed therebetween.

[0050] In addition, the upper surfaces of the insulating layer 102 and the semiconductor pillar 120 are covered by an insulating layer 103 such as silicon oxide (SiO2).

[0051] [Structure of the inter-block structure 150]

[0052] As described with reference to Figure 1 the inter-block structure 150 is disposed between two memory blocks BLK adjacent in the Y direction and extends in the Z direction and the X direction. For example, as Figure 2 and Figure 4As shown, the inter-block structure 150 includes a conductive layer 151 extending in the Z direction and the X direction, and an insulating layer 152 provided on the side surface of the conductive layer 151. The conductive layer 151 is formed of a conductive layer such as tungsten (W), for example. The insulating layer 152 is formed of an insulating layer such as silicon oxide (SiO2), for example. Through this insulating layer 152, insulation between the conductive layer 151 and the plurality of stacked conductive layers 110 is ensured.

[0053] The lower end of the conductive layer 151 of the inter-block structure 150 is connected to the P-type well region 100P of the semiconductor substrate 100, and the conductive layer 151 functions as a source contact portion. In addition, a silicide, an N-type impurity layer, etc. may also be provided between the conductive layer 151 and the P-type well region 100P.

[0054] The lower end of the insulating layer 152 of the inter-block structure 150 abuts against the P-type well region 100P of the semiconductor substrate 100. In addition, the height of the insulating layer 152 of the inter-block structure 150 in the Z direction is higher than the upper surface of the insulating layer 102. In the present embodiment, the height of the insulating layer 152 in the Z direction is substantially equal to the height of the upper surface of the insulating layer 103.

[0055] In addition, the upper surfaces of the insulating layer 103 and the inter-block structure 150 are covered with an insulating layer 104 such as silicon oxide (SiO2).

[0056] [Structure of the etching stopper 133A]

[0057] As Figure 2 and Figure 4 shown, the etching stopper 133A is provided on the side surface in the Y direction of the insulating layer 102 and the insulating layer 103, on the side of the inter-block structure 150. The etching stopper 133A is an insulating film containing aluminum oxide (Al2O3) or other metal oxide films, for example. The etching stopper 133A has a lower etching rate (higher etching resistance under predetermined conditions) compared to the insulating layers 102 and 103 formed of silicon oxide (SiO2), etc.

[0058] [First manufacturing method of the semiconductor memory device of the first embodiment]

[0059] Next, a part of the first manufacturing method of the semiconductor memory device of the first embodiment will be described with reference to Figures 5 to 16 .

[0060] First, as Figure 5As shown, a plurality of insulating layers 101 and sacrificial layers 110A are alternately stacked on a semiconductor substrate 100 (not shown). The sacrificial layer 110A is formed of, for example, silicon nitride (Si3N4) or the like. The insulating layer 101 and the sacrificial layer 110A are formed by, for example, CVD (Chemical Vapor Deposition).

[0061] Next, as Figure 6 shown, an opening OP1 is formed at a position corresponding to the semiconductor pillar 120. The opening OP1 is a through hole that extends in the Z direction, penetrates the insulating layer 101 and the sacrificial layer 110A, and exposes the upper surface of the semiconductor substrate 100 (not shown). The opening OP1 can be formed, for example, by forming an insulating layer 102 having an opening at a portion corresponding to the opening OP1 on the upper surface of the stacked plurality of insulating layers 101 and sacrificial layers 110A, and performing RIE (Reactive Ion Etching) using the insulating layer 102 as a mask.

[0062] Next, as Figure 7 shown, a charge storage film 132, a tunnel insulating film 131, and a semiconductor pillar 120 are formed in the opening OP1, and further, an insulating layer 125 or the like is formed.

[0063] Next, as Figure 8 shown, an opening OP2 is formed at a position corresponding to the inter-block structure 150. The opening OP2 is a groove that extends in the Z direction and the X direction, penetrates the insulating layer 101 and the sacrificial layer 110A, and divides them in the Y direction, and exposes the upper surface of the semiconductor substrate 100 (not shown). The opening OP2 can be formed, for example, by forming an insulating layer 103 having a groove at a portion corresponding to the opening OP2 on the upper surface of the insulating layer 102, and performing RIE using the insulating layer 103 as a mask.

[0064] Next, as Figure 9 shown, the sacrificial layer 110A is removed through the opening OP2. The sacrificial layer 110A is removed by, for example, wet etching using phosphoric acid.

[0065] Next, as Figure 10 shown, a metal oxide film 133D is formed on the upper surface, lower surface, and side surfaces of the insulating layer 101, the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, the lower surface of the insulating layer 102, and the outer peripheral surface of the charge storage film 132 through the opening OP2. The portion of the metal oxide film 133D that covers the outer peripheral surface of the charge storage film 132 becomes the block insulating film 133 ( Figure 3 、 Figure 4)。In addition, the portions of the metal oxide film 133D covering the upper and lower surfaces of the insulating layer 101 become the insulating film 133B( Figure 3 、 Figure 4 ). In addition, the portions of the metal oxide film 133D covering the side surfaces of the insulating layers 102 and 103 become the etch stopper portion 133A( Figure 2 、 Figure 4 ). The metal oxide film 133D is formed, for example, by forming aluminum oxide (Al2O3) using CVD or the like.

[0066] Next, a conductive layer 110 is formed on the upper surface, lower surface, and side surfaces of the insulating layer 101 on which the metal oxide film 133D is formed, the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, the lower surface of the insulating layer 102, and the outer peripheral surface of the charge storage film 132 via the opening OP2. The conductive layer 110 is formed, for example, by forming molybdenum (Mo) or the like using CVD or the like.

[0067] In addition, when a conductive layer 110 such as molybdenum (Mo) is formed on the metal oxide film 133D, molybdenum (Mo) or the like is also formed at the grain boundaries between the grains of the aluminum oxide (Al2O3) constituting the metal oxide film 133D.

[0068] Next, as Figure 11 shown, unnecessary portions in the conductive layer 110 are removed. Specifically, the conductive layer 110 formed on the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, and the side surface of the insulating layer 101 is removed by dry etching using a fluorine (F)-based gas, such as nitrogen trifluoride (NF3).

[0069] If the conductive layer 110 is removed in this way by dry etching using a fluorine (F)-based gas, aluminum fluoride (AlF3) is generated. Then, an aluminum fluoride layer 140 formed of aluminum fluoride (AlF3) is formed on the metal oxide film 133D formed on the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, and the side surface of the insulating layer 101.

[0070] At this time, at the portion of the metal oxide film 133D such as aluminum oxide (Al2O3) covered by the aluminum fluoride layer 140, for example, Figure 11 at the portion represented by C, the molybdenum (Mo) formed at the grain boundaries of the aluminum oxide (Al2O3) is sandwiched and remains between the grains of the metal oxide film 133D and the aluminum fluoride layer 140.

[0071] Next, as Figure 12As shown, a capping layer 145 is formed. The capping layer 145 covers the metal oxide film 133D and the aluminum fluoride layer 140 formed on the upper surface of the insulating layer 103 and the side surfaces of the insulating layers 102 and 103. On the other hand, the capping layer 145 does not cover the metal oxide film 133D and the aluminum fluoride layer 140 formed on the upper surface, lower surface, and side surfaces of the insulating layer 101 and the like. The capping layer 145 is formed, for example, by forming silicon dioxide (SiO2) by plasma CVD using silane (SiH4) as a raw material. Since such a film-forming method has poor coverage, a capping layer 145 can be formed that selectively covers the metal oxide film 133D and the aluminum fluoride layer 140 formed on the upper surface of the insulating layer 103 and the side surfaces of the insulating layers 102 and 103 without covering the structure within the opening OP2.

[0072] Next, as Figure 13 shown, the metal oxide film 133D and the aluminum fluoride layer 140 formed on the side surface of the insulating layer 101 are removed by dry etching using a chlorine (Cl2)-based gas or the like. Thereby, at the portion represented by C in Figure 11 , the molybdenum (Mo) remaining sandwiched between the crystal grains in the metal oxide film 133D and the aluminum fluoride layer 140 is also removed.

[0073] Next, as Figure 14 shown, the capping layer 145 of silicon dioxide (SiO2) and the aluminum fluoride layer 140 covered by the capping layer 145 are removed using hydrofluoric acid obtained by diluting hydrogen fluoride HF about 1000 times with an aqueous solution.

[0074] In addition, the removal of the capping layer 145 and the aluminum fluoride layer 140 covered by the capping layer 145 can also be performed by etchback.

[0075] Next, as Figure 15 shown, the metal oxide film 133D formed on the upper surface of the insulating layer 103 is removed by anisotropic etching such as RIE. In addition, the etch stop portion 133A formed on the side surfaces of the insulating layers 102 and 103 is not removed in this process. The etch stop portion 133A is disposed on the side surfaces of the insulating layers 102 and 103, that is, the upper side portion of the inner surface of the opening OP2.

[0076] Next, as Figure 16 shown, the insulating layer 152 is formed. The insulating layer 152 is formed by forming silicon dioxide (SiO2) or the like on the inner surface (side surfaces of the conductive layer 110, the insulating layer 101, and the etch stop portion 133A) of the opening OP2 and the bottom surface (upper surface of the semiconductor substrate 100) of the opening OP2 by means of CVD or the like.

[0077] Next, the portion of the insulating layer 152 covering the bottom surface of the opening OP2 is removed. This process is performed, for example, by anisotropic etching such as RIE.

[0078] When removing a part of the bottom surface of the opening OP2 in the insulating layer 152 by anisotropic etching such as RIE, the etching stopper portion 133A with a low etching rate (high etching resistance) becomes a mask. As a result, in the upper side portion of the opening OP2, etching in the lateral (Y direction) does not progress. Therefore, according to such a method, the insulating layers 102 and 103 formed of silicon oxide (SiO2) etc. are not removed by etching based on RIE etc., and a part of the insulating layer 152 can be selectively removed.

[0079] Next, a conductive layer 151 is formed between the insulating layers 152. The conductive layer 151 is formed by depositing tungsten (W) etc. by means such as CVD.

[0080] After that, by forming insulating layers 104 and contact portions 120C as Figure 2 shown, a semiconductor memory device as Figures 1 to 4 shown is manufactured.

[0081] [Second manufacturing method of the semiconductor memory device of the first embodiment]

[0082] Next, with reference to Figures 17 to 28 , a part of the second manufacturing method of the semiconductor memory device of the first embodiment will be described. In addition, here, the characteristic parts in the second manufacturing method will be described. Also, in Figures 17 to 28 , the semiconductor pillar 120 and the constituent members around it, and the constituent members on the right side of the opening OP2 are not shown.

[0083] First, in the same manner as the first manufacturing method, the processes described with reference to Figures 5 to 10 are performed. Then, as Figure 17 shown, a metal oxide film 133D formed of aluminum oxide (Al2O3) is deposited on the upper surface, lower surface and side surfaces of the insulating layer 101, the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, the lower surface of the insulating layer 102, and the outer peripheral surface of the charge storage film 132 (not shown in Figure 17 ), and then a conductive layer 110 formed of molybdenum (Mo) etc. is deposited on the metal oxide film 133D.

[0084] At this time, as described above, molybdenum (Mo) is also deposited at the grain boundaries between the grains of the aluminum oxide (Al2O3) constituting the metal oxide film 133D.

[0085] Next, as Figure 18As shown, a capping layer 146 is formed. The capping layer 146 covers the metal oxide film 133D and the conductive layer 110 formed on the upper surface of the insulating layer 103 and the side surfaces of the insulating layers 102 and 103. On the other hand, the capping layer 146 does not cover the metal oxide film 133D and the conductive layer 110 formed on the side surfaces of the insulating layer 101 and the like. The capping layer 146 is formed, for example, by forming a silicon oxide (SiO2) film using plasma CVD with silane (SiH4) as a raw material.

[0086] Next, as Figure 19 shown, unnecessary portions in the conductive layer 110 are removed. Specifically, the conductive layer 110 formed on the lower side portion of the side surface of the insulating layer 102 and the side surfaces of the insulating layer 101 and the like is removed by dry etching using a fluorine (F)-based gas, such as nitrogen trifluoride (NF3).

[0087] When the conductive layer 110 is removed by dry etching using a fluorine (F)-based gas in this way, aluminum fluoride (AlF3) is generated. Then, an aluminum fluoride layer 140 formed of aluminum fluoride (AlF3) is formed on the metal oxide film 133D formed on the lower side portion of the side surface of the insulating layer 102 and the side surfaces of the insulating layer 101.

[0088] At this time, at a portion of the metal oxide film 133D such as aluminum oxide (Al2O3) covered by the aluminum fluoride layer 140, for example, Figure 19 at the portion indicated by D, molybdenum (Mo) formed at the grain boundaries of the aluminum oxide (Al2O3) is sandwiched between the grains in the metal oxide film 133D and the aluminum fluoride layer 140 and remains.

[0089] Next, as Figure 20 shown, the metal oxide film 133D and the aluminum fluoride layer 140 formed on the lower side portion of the side surface of the insulating layer 102 and the side surfaces of the insulating layer 101 are removed by dry etching using a chlorine (Cl2)-based gas. As a result, at Figure 19 the portion indicated by D and the like, the molybdenum (Mo) sandwiched between the grains in the metal oxide film 133D and the aluminum fluoride layer 140 is also removed.

[0090] Next, as Figure 21 shown, the capping layer 146 of silicon oxide (SiO2) is removed using hydrofluoric acid obtained by diluting hydrogen fluoride HF with an aqueous solution about 1000 times.

[0091] Next, as Figure 22As shown, a portion of the conductive layer 110 that is formed on the upper surface and the upper side portion of the side surface of the insulating layer 103 is removed by anisotropic etching or the like. In addition, the etching stopper portion 133A formed on the upper surface and the side surface of the insulating layer 103 and the upper side portion of the side surface of the insulating layer 102 is not removed in this process. The etching stopper portion 133A is disposed on the upper side portion of the inner surface of the opening OP2.

[0092] Next, as Figure 23 shown, the insulating layer 152a is formed. The insulating layer 152a is formed by depositing silicon oxide (SiO2) or the like on the upper surface of the etching stopper portion 133A, the inner surface of the opening OP2 (the side surfaces of the conductive layer 110, the insulating layer 101, and the etching stopper portion 133A), and the bottom surface of the opening OP2 (the upper surface of the semiconductor substrate 100) by means such as CVD.

[0093] Next, as Figure 24 shown, the upper side portion of the insulating layer 152a made of silicon oxide (SiO2) is removed by a method such as RIE. In this process, the insulating layer 152a is removed until the conductive layer 110 in contact with the etching stopper portion 133A appears.

[0094] Next, as Figure 25 shown, the conductive layer 110 in contact with the etching stopper portion 133A is etched using a hydrogen peroxide solution (H2O2).

[0095] Next, as Figure 26 shown, the insulating layer 152b is formed. The insulating layer 152b is formed by depositing silicon oxide (SiO2) or the like on the inner surface and the bottom surface of the insulating layer 152a and the side surface and the upper surface of the etching stopper portion 133A by means such as CVD.

[0096] The insulating layer 152 is formed by the insulating layer 152a and the insulating layer 152b.

[0097] Next, the portion of the insulating layer 152 (152a, 152b) that covers the bottom surface of the opening OP2 is removed. This process is performed, for example, by anisotropic etching such as RIE.

[0098] When removing the portion of the insulating layer 152 (152a, 152b) that covers the bottom surface of the opening OP2 by anisotropic etching such as RIE in this way, the etching stopper portion 133A with a low etching rate (high etch resistance) becomes a mask. As a result, in the upper portion of the opening OP2, etching in the lateral (Y direction) does not progress. Therefore, according to such a method, the insulating layers 102 and 103 made of silicon oxide (SiO2) or the like are not removed by etching based on RIE or the like, and a part of the insulating layer 152 can be selectively removed.

[0099] Next, as Figure 27 shown, a conductive layer 151 is formed on the side surfaces of the insulating layers 152 (152a, 152b), the upper surfaces of the insulating layers 152 (152a, 152b), and the upper surface of the etch stopper 133A. The conductive layer 151 is formed by depositing tungsten (W) or the like by means such as CVD.

[0100] Next, as Figure 28 shown, the upper portions of the conductive layer 151, the upper portions of the insulating layers 152 (152a, 152b), the upper portions of the etch stopper 133A, and the upper portions of the insulating layer 103 are removed by chemical mechanical polishing (CMP: Chemical Mechanical Polishing) for planarization.

[0101] After that, by forming an insulating layer 104 and a contact portion 120C as Figure 2 and Figure 4 shown, a semiconductor memory device as Figures 1 to 4 shown is manufactured.

[0102] [Manufacturing method of comparative example]

[0103] Next, the main points of the manufacturing method of the semiconductor memory device of the comparative example will be described with reference to Figures 29 to 32 .

[0104] [Manufacturing method of the first comparative example]

[0105] In the manufacturing method of the first comparative example, first, the same processes as those described with reference to Figures 5 to 10 are performed as in the first manufacturing method of the semiconductor memory device of the first embodiment. When the processes as Figure 10 shown are completed, as described above, a metal oxide film 133D formed of aluminum oxide (Al2O3) is deposited on the upper surface, lower surface, and side surfaces of the insulating layer 101, the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, the lower surface of the insulating layer 102, and the outer peripheral surface of the charge storage film 132, and a conductive layer 110 formed of molybdenum (Mo) or the like is deposited on the metal oxide film 133D.

[0106] At this time, as described above, molybdenum (Mo) is also deposited at the grain boundaries between the grains of the aluminum oxide (Al2O3) constituting the metal oxide film 133D.

[0107] Next, as Figure 29 shown, the conductive layer 110 formed on the upper surface of the insulating layer 103, the side surfaces of the insulating layers 102 and 103, and the side surface of the insulating layer 101 in the conductive layer 110 is removed by dry etching using a fluorine (F)-based gas, such as nitrogen trifluoride (NF3).

[0108] If the conductive layer 110 is removed by dry etching using a fluorine (F)-based gas or the like, an aluminum fluoride layer 140 formed of aluminum fluoride (AlF3) is formed on the metal oxide film 133D formed on the upper surface of the insulating layer 103, on the sides of the insulating layers 102 and 103, and on the sides of the insulating layer 101.

[0109] At this time, at a portion of the metal oxide film 133D formed of aluminum oxide (Al2O3) covered by the aluminum fluoride layer 140, for example, Figure 29 at the portion indicated by E, molybdenum (Mo) formed at the grain boundaries of the aluminum oxide (Al2O3) is sandwiched and remains between the grains in the metal oxide film 133D and the aluminum fluoride layer 140.

[0110] Next, as Figure 30 shown, the aluminum fluoride layer 140 is removed using hydrogen fluoride (HF) or the like.

[0111] In this case, molybdenum (Mo) formed at the grain boundaries of the aluminum oxide (Al2O3) remains in the metal oxide film 133D formed on the side of the insulating layer 101.

[0112] Therefore, two adjacent conductive layers 110 in the Z direction may be electrically connected via molybdenum (Mo) remaining at the grain boundaries in the metal oxide film 133D, resulting in a short circuit.

[0113] [Manufacturing Method of the Second Comparative Example]

[0114] In the manufacturing method of the second comparative example, first, the same processes as those described with reference to Figures 5 to 10 the first manufacturing method of the semiconductor memory device of the first embodiment are performed.

[0115] When Figure 10 the processes shown are completed, as described above, molybdenum (Mo) is also formed at the grain boundaries between the grains of the aluminum oxide (Al2O3) constituting the metal oxide film 133D.

[0116] Next, as Figure 31 shown, the conductive layer 110 formed on the upper surface of the insulating layer 103, on the sides of the insulating layers 102 and 103, and on the sides of the insulating layer 101 in the conductive layer 110 is removed by dry etching using a chlorine (Cl2)-based gas or the like. In addition, the metal oxide film 133D formed on the upper surface of the insulating layer 103, on the sides of the insulating layers 102 and 103, and on the sides of the insulating layer 101 is removed.

[0117] Since the metal oxide film 133D formed on the side surface of the insulating layer 101 is removed in this way, the molybdenum (Mo) formed on the surface of the metal oxide film 133D formed of aluminum oxide (Al2O3) on the side surface of the insulating layer 101 (the surface on the opening OP2 side) is also removed.

[0118] Therefore, the problem in the manufacturing method of the first comparative example, that is, the possibility that two adjacent conductive layers 110 in the Z direction are electrically connected to each other via the molybdenum (Mo) at the grain boundary remaining in the metal oxide film 133D, disappears.

[0119] Next, as Figure 32 shown, an insulating layer 152 is formed on the inner surface and the bottom surface of the opening OP2. After that, the insulating layer 152 at the bottom surface portion of the opening OP2 is removed by anisotropic etching such as RIE. If this anisotropic etching is performed, in the upper side portion of the opening OP2, the etching in the lateral direction (Y direction) also progresses, and the insulating layers 102 and 103 formed of silicon oxide (SiO2) or the like are also removed, and sometimes the opening width expands in the Y direction in the upper side portion of the opening OP2.

[0120] If the conductive layer 151 is formed by film formation such as tungsten (W) in a state where the opening width has expanded in the Y direction in the upper side portion of the opening OP2, the conductive layer 151 sometimes has a shape expanded in the Y direction in its upper side portion.

[0121] After that, if the contact portion 120C is formed, the contact portion 120C may be short-circuited with the conductive layer 151 expanded in the Y direction.

[0122] [Effects of the First Embodiment]

[0123] In the first embodiment, in the process described with reference to, for example, Figure 13 the metal oxide film 133D formed of aluminum oxide (Al2O3) formed on the side surface of the insulating layer 101 and the molybdenum (Mo) formed at its grain boundary are removed together. Therefore, it is possible to suppress the problem that two adjacent conductive layers 110 in the Z direction are electrically connected to each other via the remaining molybdenum (Mo) and short-circuited, and it is possible to ensure the insulation between these two conductive layers 110.

[0124] In addition, in the present embodiment, when removing the portion covering the bottom surface of the opening OP2 in the insulating layer 152 by anisotropic etching such as RIE, the etching stopper 133A serves as a mask. Therefore, it is possible to suppress the progress of etching in the lateral direction (Y direction) in the upper side portion of the opening OP2 and suppress the expansion of the opening width in the upper side portion of the opening OP2.

[0125] Therefore, it is possible to suppress the expansion of the conductive layer 151 in the Y direction and suppress the short circuit between the contact portion 120C and the conductive layer 151.

[0126] [Second Embodiment]

[0127] Next, the structure of the semiconductor memory device according to the second embodiment will be described with reference to the drawings. In addition, in the following description, the same reference numerals are given to the same components as those in the first embodiment, and the description is simplified or omitted.

[0128] [Structure]

[0129] Figure 33 FIG. is a schematic cross-sectional view showing the main part of the semiconductor memory device according to the second embodiment. In the second embodiment, the structure of the inter-block structure 150A and the arrangement state of the etching stopper 133A are different from those of the inter-block structure 150 and the arrangement state of the etching stopper 133A in the first embodiment illustrated in Figure 2 and Figure 4 etc.

[0130] In the second embodiment, the inter-block structure 150A includes, for example, an insulating layer 153 extending in the Z direction and the Y direction, and a pair of insulating layers 154 provided on the side surfaces of the insulating layer 153, respectively. The insulating layers 153 and 154 are formed of an insulating material such as silicon oxide (SiO2), for example.

[0131] The Y-direction width of the upper side portion of the inter-block structure 150A is, for example, narrower than the Y-direction width of the portion below it.

[0132] A pair of insulating layers 154 separated in the Y direction with the insulating layer 153 therebetween have a gradually decreasing Y-direction width as they extend upward along the Z direction at the upper side portion.

[0133] The etching stopper 133A is provided on the side surface of the insulating layer 102 and the insulating layer 103 on the side of the inter-block structure 150A. In the second embodiment, for example, the side surface of the insulating layer 102 and the insulating layer 103 on the side of the inter-block structure 150A is inclined. That is, the side surfaces of the insulating layers 102 and 103 separated in the Y direction with the inter-block structure 150A therebetween are inclined surfaces that gradually approach each other as they extend upward along the Z direction. Therefore, a pair of etching stoppers 133A provided on the side surfaces of the insulating layers 102 and 103 are arranged to be inclined so as to gradually approach each other as they extend upward along the Z direction.

[0134] In the present embodiment, the upper surface of the inter-block structure 150A, that is, the upper surface of the insulating layer 153, is flat, and the upper surface of the insulating layer 153 and the upper surface of the insulating layer 103 form a continuous plane.

[0135] [Manufacturing Method of Semiconductor Memory Device of Second Embodiment]

[0136] Next, a main point of an example of the manufacturing method of the semiconductor memory device of the second embodiment will be described.

[0137] First, the same processes as those described with reference to the first manufacturing method of the semiconductor memory device of the first embodiment are performed. Figures 5 to 7 The processes described above are performed.

[0138] Next, for example, as Figure 34 shown, the opening OP2 is formed in the same manner as the processes described with reference to Figure 8 However, in the second embodiment, the opening OP2 is formed such that the width in the Y direction of the upper portion is narrower than the width in the Y direction of the portion below it. Therefore, the side surfaces of the insulating layers 102 and 103 on the side of the opening OP2 become inclined surfaces.

[0139] Next, for example, as Figure 35 shown, by performing the processes described with reference to Figures 9 to 15 the etching stopper portion 133A is formed on the inclined side surfaces of the insulating layers 102 and 103 on the side of the opening OP2.

[0140] Next, for example, as Figure 36 shown, the insulating layer 154 is formed by depositing silicon oxide (SiO2) or the like by means of CVD or the like on the inner surface (side surfaces of the conductive layer 110, the insulating layer 101, and the etching stopper portion 133A) of the opening OP2 and the bottom surface (upper surface of the semiconductor substrate 100) of the opening OP2. At this time, since the width in the Y direction of the upper portion of the opening OP2 is narrower, the upper portions of one insulating layer 154 and the upper portions of the other insulating layer 154 overlap, and the upper portion of the opening OP2 is closed by the overlapping insulating layers 154 on both sides. In addition, a gap (void) exists between one insulating layer 154 and the other insulating layer 154 at a portion below the upper portion of the opening OP2.

[0141] Next, for example, as Figure 37 shown, a part of the upper portions of the insulating layer 154 that closes the upper portion of the opening OP2 is removed by anisotropic etching such as RIE. As a result, the gap (void) formed between one insulating layer 154 and the other insulating layer 154 becomes open at the upper portion.

[0142] Here, when removing the upper portion of the insulating layer 154 that closes the upper side of the opening OP2 by anisotropic etching such as RIE, the etching stopper portion 133A with a low etching rate (high etching resistance) serves as a mask. As a result, in the upper portion of the opening OP2, etching in the lateral (Y direction) does not progress. Therefore, according to such a method, the insulating layers 102 and 103 formed of silicon oxide (SiO2) or the like are not removed by etching based on RIE or the like, and the upper portion of the insulating layer 154 that closes the upper side of the opening OP2 can be selectively removed.

[0143] Next, for example, as Figure 38 shown, an insulating layer 153 is formed by depositing silicon oxide (SiO2) or the like by means such as CVD from the upper portion of the opening OP2 that has become an open state into the gap (void) formed between one insulating layer 154 and the other insulating layer 154. At this time, the insulating layer 153 is also formed on the upper surface of the insulating layer 103.

[0144] After that, the insulating layer 153 formed on the upper surface of the insulating layer 103 is removed, and the insulating layer 104 and the contact portion 120C are formed, thereby manufacturing the semiconductor memory device of the second embodiment.

[0145] [Third Comparative Example]

[0146] Next, with reference to Figure 39 the structure of the semiconductor memory device of the third comparative example will be described. In addition, for the same components as those in the second embodiment, the same reference numerals are given, and the description is simplified or omitted.

[0147] As Figure 39 shown, the semiconductor memory device of the third comparative example does not include the etching stopper portion 133A included in the semiconductor memory device of the second embodiment.

[0148] In addition, the upper surface of the inter-block structure 150A (insulating layer 153) is recessed, and the insulating layer 104 enters this recessed portion, and the upper surface of the insulating layer 104 is also in a recessed state.

[0149] The reason for the appearance of the recessed portions on the upper surfaces of the inter-block structure 150A and the insulating layer 104 is as follows.

[0150] That is, as described with reference to Figure 36 if the insulating layer 154 is formed on the inner surface and the bottom surface of the opening OP2 whose Y-direction width of the upper portion is narrower than the Y-direction width of the portion below it, the upper portions of the two insulating layers 154 overlap, and the upper portion of the opening OP2 is closed.

[0151] Therefore, in the manufacturing method of the second embodiment, as described with reference to Figure 37As described above, the upper portion of the insulating layer 154 that closes the upper side of the opening OP2 is removed by anisotropic etching such as RIE. At this time, the opening OP2 is suppressed from expanding in the lateral direction (Y direction) by the etching stopper portion 133A.

[0152] Here, when the etching stopper portion 133A is not provided in the opening OP2, for example, as Figure 40 shown, at the upper portion of the opening OP2, etching in the lateral direction (Y direction) also progresses, and the insulating layer 154 and the insulating layers 102 and 103 formed of silicon oxide (SiO2) or the like are also removed, and the opening width at the upper portion of the opening OP2 expands in the Y direction.

[0153] In a state where the opening width at the upper portion of the opening OP2 expands in the Y direction like this, when the insulating layer 153 is formed by depositing silicon oxide (SiO2) or the like by means such as CVD in the gap (void) formed between one insulating layer 154 and the other insulating layer 154 from the upper portion of the opening OP2, for example, as Figure 41 shown, the upper surface of the insulating layer 153 is recessed. This is because: since the filling amount of silicon oxide (SiO2) or the like that will become the insulating layer 153 is set on the condition that the opening width of the opening OP2 does not expand in the Y direction, if the opening width of the opening OP2 expands in the Y direction, an amount of silicon oxide (SiO2) or the like will be used in excess to fill the expanded portion, and as a result, the upper surface of the insulating layer 153 is recessed.

[0154] If the upper surface of the insulating layer 153 is recessed like this, a recess will also be generated on the upper surface of the insulating layer 104 formed on the insulating layer 153. Thus, for example, a recess will be generated in a wiring layer or the like formed above the insulating layer 104, and it may not be possible to appropriately form the wiring layer or the like.

[0155] [Effects of the Second Embodiment]

[0156] In the second embodiment, since the upper surfaces of the insulating layers 153 and 154, which are the upper surface of the inter-block structure 150A, are flat, the upper surface of the insulating layer 104 is also flat. Thus, for example, a wiring layer or the like formed above the insulating layer 104 can be appropriately formed.

[0157] [Others]

[0158] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Claims

1. A semiconductor storage device comprising: substrate; A plurality of first conductive layers and a plurality of first insulating layers are alternately stacked above the substrate in a first direction intersecting the surface of the substrate; a second insulating layer on the stack of the plurality of first conductive layers and the plurality of first insulating layers; a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, the plurality of first insulating layers, and the second insulating layer; a second semiconductor layer, which is provided as a part of the substrate, or is provided between the substrate and the stack of the plurality of first conductive layers and the plurality of first insulating layers, is connected to the lower end of the first semiconductor layer in the first direction, and extends in a second direction intersecting the first direction; and a third insulating layer, which cuts off the plurality of first conductive layers, the plurality of first insulating layers, and the second insulating layer in the second direction, extends in the first direction and a third direction, and is in contact with the second semiconductor layer at a lower end in the first direction, and the third direction intersects the first direction and the second direction, At least a portion of the third insulating layer is in contact with the second insulating layer via a metal oxide film. Each of the plurality of first insulating layers is in contact with the third insulating layer without a metal oxide film interposed therebetween.

2. The semiconductor memory device according to claim 1, comprising: a charge storage film provided between the plurality of first conductive layers and the first semiconductor layer; and A plurality of first metal oxide films are provided between the plurality of first conductive layers and the charge storage film.

3. The semiconductor memory device according to claim 2, A plurality of second metal oxide films are provided between the plurality of first conductive layers and the plurality of first insulating layers and are formed continuously with the first metal oxide film.

4. The semiconductor memory device according to claim 3, The metal oxide film provided on a surface of the second insulating layer on the third insulating layer side in the second direction is separated from any of the plurality of second metal oxide films in the first direction.

5. The semiconductor memory device according to any one of claims 1 to 4, The substrate is a semiconductor substrate, The second semiconductor layer is a portion of the semiconductor substrate.

6. The semiconductor memory device according to claim 1, The upper end of the third insulating layer is located above the upper surface of the second insulating layer. The metal oxide film is provided from between the third insulating layer and the second insulating layer along the side surface of the third insulating layer to a position above the upper surface of the second insulating layer.

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