Array substrate and display terminal

Abstract

The application provides an array substrate and a display terminal. The array substrate comprises a substrate, a light shielding layer arranged on the substrate, an active layer arranged on the light shielding layer, and a connecting piece arranged on the active layer. The light shielding layer comprises a plurality of spaced light shielding portions. The active layer comprises a plurality of spaced active portions. One active portion corresponds to one light shielding portion. Adjacent two active portions are electrically connected through a bridging piece. The toughness of the bridging piece is greater than that of the active portion. The application connects adjacent two active portions through the bridging piece. The toughness of the bridging piece is greater than that of the active portion. The active layer can be kept continuous at a climbing position between adjacent two light shielding portions. The risk of abnormal crystallization or fracture of the active layer at the climbing position is reduced. The possibility of a large decrease in the on-state current of a thin film transistor is avoided or reduced. The display defects such as dark spots are reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display terminal. Background Technology

[0002] To improve the off-state leakage current problem of thin-film transistors in low-frequency displays, two active-layer thin-film transistors connected in series are usually set in a sub-pixel to increase the channel region ratio, thereby increasing the impedance value of the thin-film transistors. A metal light-shielding layer is also set to shield the channel regions of multiple thin-film transistors to reduce the off-state leakage current of the thin-film transistors.

[0003] Currently, the metal light-shielding layers corresponding to two series-connected thin-film transistors are generally spaced apart. However, when the active layers of the two series-connected thin-film transistors are connected at the interval of the metal light-shielding layers, there is a ramp. The ramp position is prone to crystallization abnormalities or active layer fractures, which leads to a significant reduction in the on-state current of the thin-film transistor and causes display defects such as dark spots. Summary of the Invention

[0004] This application provides an array substrate and a display terminal to improve the technical problem that the current array substrate has a ramp at the interval position of the metal light-shielding layer, which causes a significant reduction in the on-state current of the thin film transistor and results in display defects such as dark spots.

[0005] To solve the above-mentioned technical problems, the technical solution provided in this application is as follows:

[0006] This application provides an array substrate, comprising:

[0007] Substrate;

[0008] A light-shielding layer is disposed on the substrate, the light-shielding layer comprising a plurality of light-shielding portions spaced apart;

[0009] An active layer is disposed on the light-shielding layer, the active layer comprising a plurality of spaced-apart active portions, one active portion corresponding to one light-shielding portion; and

[0010] A bridging element is disposed on the active layer, and two adjacent active parts are electrically connected through the bridging element. The toughness of the bridging element is greater than that of the active part.

[0011] In the array substrate of this application, the spacing between two adjacent active parts connected by the bridging member is 2 micrometers to 5 micrometers.

[0012] In the array substrate of this application, the orthographic projection of the active portion onto the corresponding light-shielding portion is located within the light-shielding portion;

[0013] In the array substrate, the edge of the active part and the edge of the light shielding part are spaced apart by 1-3 microns in the top view of the array substrate.

[0014] In the array substrate, the thickness of the bridge is greater than the thickness of the light shielding layer in the direction perpendicular to the array substrate.

[0015] In the array substrate, the active part includes a channel region and first and second doped regions on both sides of the channel region, and the bridge connects the first and second doped regions of two adjacent active parts.

[0016] In the array substrate, the array substrate further includes a signal line and a pixel electrode layer disposed on the active layer.

[0017] The active layer includes at least a first active part and a second active part, wherein the signal line is connected to the first active part through a via, and the second active part is connected to the pixel electrode layer through a via.

[0018] In the array substrate, the array substrate further includes a first source-drain part disposed on the first doped region of the first active part and a second source-drain part disposed on the second doped region of the second active part.

[0019] The signal line is connected to the first source-drain part through a via, and the bridge connects the second doped region of the first active part and the first doped region of the second active part.

[0020] In the array substrate, the array substrate further includes a gate layer disposed on the active layer, and the channel regions of the plurality of active parts are orthogonally projected on the gate layer.

[0021] In the array substrate, the array substrate further includes a gate insulating layer disposed between the active layer and the bridge, and the bridge is connected to the active layer through a via.

[0022] The application also provides a display terminal, which includes a terminal body and the array substrate as described above, and the array substrate and the terminal body are combined into one.

[0023] Advantages:

[0024] The application can improve the channel area proportion in the two series thin film transistors, and further improve the impedance value and reduce the off-state leakage current of the thin film transistor by connecting the adjacent two active parts through the bridge part. In addition, the light shielding parts corresponding to the adjacent two active parts are also arranged at intervals, which can solve or improve the problem of poor electrostatic protection process caused by the large metal layer. In addition, the toughness of the bridge part is greater than that of the active part, so that the continuity can be maintained at the climbing position between the adjacent two light shielding parts, the risk of abnormal crystallization or fracture of the "active layer" at the climbing position is reduced, and the possibility of large on-state current of the thin film transistor is avoided or reduced, and the display defects such as dark spots are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 is a schematic view of the planar structure of the active layer and the light shielding layer in the background art of the application;

[0027] Figure 2 is a schematic view of the planar structure of the active layer and the light shielding layer in the array substrate described in the application;

[0028] Figure 3 is a first cross-sectional view of the array substrate along the A-A line in the application; Figure 2

[0029] Figure 4 is a second cross-sectional view of the array substrate along the A-A line in the application. Figure 2 BRIEF DESCRIPTION OF DRAWINGS

[0030] Substrate 100, light shielding part 200, active part 300, first active part 301, second active part 302, first doped region 310, channel region 320, second doped region 330, bridge part 400, first insulating layer 510, second insulating layer 520, third insulating layer 530, signal line 600, data line 610, scan line 620, pixel electrode layer 700, source-drain electrode layer 800, first source-drain electrode part 810, second source-drain electrode part 820, gate layer 900.

[0031] DETAILED DESCRIPTION

[0032] ​​The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower positions of the device in the actual use or working state, and the specific direction is the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device.

[0033] Low-frequency display technology has become the focus of current display technology development because it can better improve the endurance of display devices. In order to improve the off-state leakage current problem of thin film transistors in low-frequency display, two thin film transistors with series-connected active layers are usually arranged in one sub-pixel to increase the channel area ratio, thereby increasing the impedance value of the thin film transistor, and a metal light shielding layer is arranged to shield the channel regions of the plurality of thin film transistors, so as to reduce the off-state leakage current of the thin film transistor. At the same time, in order to reduce the coupling capacitance between the metal light shielding layer and the data line on the array substrate and avoid the problem of low-frequency flicker, the current method is to connect the metal light shielding layers corresponding to two or more sub-pixels together, and by using the opposite polarity of the adjacent two data lines, the flicker deterioration caused by the coupling capacitance can be effectively offset, thereby improving the low-frequency flicker effect.

[0034] However, connecting the metal light shielding layers corresponding to two or more sub-pixels together, as shown in Figure 1 , is equivalent to increasing the area of the metal light shielding layer, and a large metal layer will cause the problem of poor electrostatic protection process. In order to solve this problem, the metal light shielding layers corresponding to each sub-pixel are usually arranged at intervals, and the metal light shielding layers corresponding to the two series-connected thin film transistors are also arranged at intervals, so as to reduce the area of a single metal light shielding layer and thereby avoid the problem of poor electrostatic protection process.

[0035] However, when the active layers of the two series-connected thin film transistors are connected at the interval position of the metal light shielding layer, there is a climbing problem, and the climbing position is prone to crystallization abnormality or active layer fracture, which causes a large decrease in the on-state current of the thin film transistor and causes display defects such as dark spots. Based on the above technical problems, the present application proposes the following solutions.

[0036] Please refer to Figures 2 to 4 , the present application provides an array substrate, comprising:

[0037] a substrate 100;

[0038] A light shielding layer is arranged on the substrate 100, and the light shielding layer comprises a plurality of light shielding portions 200 arranged at intervals;

[0039] An active layer is arranged on the light shielding layer, and the active layer comprises a plurality of active portions 300 arranged at intervals, and one active portion 300 corresponds to one light shielding portion 200.

[0040] A bridge 400 is arranged on the active layer, and two adjacent active portions 300 are electrically connected through the bridge 400, and the toughness of the bridge 400 is greater than the toughness of the active portion 300.

[0041] In the present application, the bridge 400 is arranged to connect two adjacent active portions 300, so that the two adjacent active portions 300 of the thin film transistor are connected in series, so that the proportion of the channel region 320 in the two series-connected thin film transistors can be increased, and the impedance value is increased, and the off-state leakage current of the thin film transistor is reduced. Moreover, in the present application, the light shielding portions 200 corresponding to the two adjacent active portions 300 are also arranged at intervals, so that the problem of poor electrostatic protection process caused by a large metal layer can be solved or improved. In addition, in the present application, the toughness of the bridge 400 is greater than the toughness of the active portion 300, so that the continuity of the climbing position between the two adjacent light shielding portions 200 can be maintained, the risk of crystallization abnormality or fracture of the "active layer" at the climbing position is reduced, and the possibility of a large decrease in the on-state current of the thin film transistor is avoided or reduced, and the display defects such as dark spots are reduced.

[0042] The technical solutions of the present application will be described in combination with specific embodiments. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0043] In the array substrate of the present application, the substrate 100 can be a glass substrate or a polyimide substrate.

[0044] In the present embodiment, the light shielding layer can be a metal layer, such as copper, aluminum, molybdenum, titanium, or other conductive metal or alloy materials.

[0045] In the present embodiment, the active layer can be prepared from a low-temperature polysilicon (LTPS) material.

[0046] In the present embodiment, the plurality of active portions 300 of the active layer are arranged in an array, and every two adjacent active portions 300 are connected through the bridge 400 to form a series active structure of a thin film transistor for driving / controlling the work of one sub-pixel.

[0047] In the embodiment, the bridge 400 can be made of a conductive metal material with greater toughness than low-temperature polysilicon material, such as aluminum, silver, copper, or other metal or alloy material, so that the bridge 400 is not easily broken at the climbing position between the two adjacent light shielding parts 200, and there is no abnormal crystallization phenomenon, thereby reducing display abnormal phenomenon such as dark spots.

[0048] In the array substrate of the present application, the array substrate can further include a first insulating layer 510 disposed between the light shielding layer and the active layer, and a second insulating layer 520 disposed between the active layer and the bridge 400. In the embodiment, the first insulating layer 510 and the second insulating layer 520 can be made of inorganic insulating material such as SiNx or SiOx.

[0049] Please refer to Figure 2 , Figure 2 FIG. 2 is a schematic diagram of the planar structure of the active layer and the light shielding layer in the array substrate of the present application. In the array substrate of the present application, the distance d1 between the two adjacent active parts 300 connected by the bridge 400 is 2-5 microns. In the embodiment, the two active parts 300 connected by the bridge 400 are two active parts 300 connected in series in one sub-pixel, and the distance between the two active parts 300 connected in series in one sub-pixel is 2-5 microns, so that the distance between the light shielding parts 200 corresponding to the active parts 300 is appropriate, avoiding or reducing the short circuit problem caused by too small distance between the light shielding parts 200, thereby avoiding or reducing the problem of poor Electrostatic Discharge (ESD) process caused by the short circuit problem, or avoiding or reducing the problem of increased pixel area and reduced resolution of the display panel caused by too large distance between the active parts 300.

[0050] Please refer to Figure 2 In the array substrate of the present application, the orthographic projection of the active part 300 on the corresponding light shielding part 200 is located in the light shielding part 200, so that the light shielding part 200 can sufficiently shield the channel region 320 of the active part 300, preventing light from irradiating the channel region 320 of the active part 300, thereby reducing the light leakage current of the channel region 320.

[0051] It should be noted that in the embodiment, the orthographic projection of the active part 300 on the light shielding layer is entirely located in the corresponding light shielding part 200, so that there is no climbing problem caused by the fact that part of the position of each active part 300 corresponds to a light shielding part 200 and part of the position does not correspond to a light shielding part 200, and there is no crystallization abnormality or breakage problem in each active part 300, further reducing display abnormal phenomenon such as dark spots.

[0052] In the embodiment, the distance d2 between the edge of the active part 300 and the edge of the light shielding part 200 in the top view of the array substrate is 1-3 microns, that is, the width of the edge of the light shielding part 200 beyond the edge of the active part 300 in the top view of the array substrate is 1-3 microns. The above arrangement in the embodiment can not only sufficiently shield the corresponding active part 300, but also maintain a proper distance between the light shielding parts 200 corresponding to the two active parts 300 connected in series in one pixel, thereby avoiding or reducing the short circuit problem caused by the too small distance between the light shielding parts 200 and the problem of the increased pixel area and the reduced resolution of the display panel caused by the too large distance between the active parts 300.

[0053] Please refer to Figure 3 , Figure 3 The array substrate described in the present application is along Figure 2 the first cross-sectional view of line A-A in the array substrate in the present application. In the array substrate in the present application, the thickness of the bridge part 400 is greater than the thickness of the light shielding layer in the direction perpendicular to the array substrate, so that the bridge part 400 further improves the risk of being pulled or torn by increasing the thickness on the basis of the better toughness of the material, thereby more stably connecting the two active parts 300 in series.

[0054] In the embodiment, the thickness of the light shielding layer can be to that is, 70-80 nm.

[0055] In the embodiment, the thickness of the bridge part 400 can be greater than that is, greater than 400 nm.

[0056] Please refer to Figure 3 In the array substrate in the present application, the active part 300 can include a channel region 320 and first and second doped regions 310 and 330 located on both sides of the channel region 320, and the bridge part 400 connects the first and second doped regions 310 and 330 of the two adjacent active parts 300.

[0057] In the embodiment, the distance between the first doped region 310 of one of the two adjacent active parts 300 and the second doped region 330 of the other active part 300 is 2-5 microns, and the bridge part 400 connects the first doped region 310 of one of the active parts 300 and the second doped region 330 of the other active part 300 within the distance.

[0058] The bridge piece 400 is connected at the nearest position between the two adjacent active sections 300, which reduces the material cost of the bridge piece 400 and facilitates reducing the climbing span between the two adjacent active sections 300 and improving the bridging stability of the bridge piece 400.

[0059] Please refer to Figure 3 In the array substrate, a plurality of signal lines 600 and a pixel electrode layer 700 are arranged on the active layer, and the active layer includes at least a first active section 301 and a second active section 302 adjacent to each other, wherein the signal line 600 is connected to the first active section 301 through a via, and the second active section 302 is connected to the pixel electrode layer 700 through a via.

[0060] In the embodiment, the first active section 301 and the second active section 302 are connected in series through the bridge piece 400. In the embodiment, the signal line 600 can be a data line 610, and the signal in the data line 610 flows through the first active section 301, the bridge piece 400, and the second active section 302, and then is transmitted to the pixel electrode layer 700 through a via, thereby achieving the signal driving effect on the array substrate.

[0061] The array substrate can further include a source-drain layer 800 arranged on the active section 300, and the source-drain layer 800 can include a first source-drain section 810 arranged on the first doped region 310 of the first active section 301 and a second source-drain section 820 arranged on the second doped region 330 of the second active section 302. The signal line 600 is connected to the first source-drain section 810 through a via, the bridge piece 400 connects the second doped region 330 of the first active section 301 and the first doped region 310 of the second active section 302, and the second source-drain section 820 of the second active section 302 is connected to the pixel electrode layer 700 through a via.

[0062] The above arrangement of the embodiment realizes the driving control of the same sub-pixel by two series-connected thin film transistors, and the length of the channel region 320 is larger after the two active sections 300 are connected in series, so that the off-state leakage current of the thin film transistor can be more effectively reduced, thereby improving the low-frequency flicker problem.

[0063] Please refer to Figure 3 and Figure 4 , Figure 4 The array substrate of the present application is arranged along Figure 2A second cross-sectional view of the AA line in this application shows that, in the array substrate, the array substrate may further include a gate layer 900 disposed on the active layer, and the orthographic projection of the channel regions 320 of the plurality of active portions 300 on the gate layer 900 lies within the gate layer 900. In this embodiment, the gate layer 900 may include a plurality of spaced-apart gate portions, each of which corresponds one-to-one with a plurality of active portions 300. That is, the orthographic projection of the channel region 320 of each active portion 300 on the corresponding gate portion lies within that gate portion, so that the gate portion can act as a shield when the active portion 300 is doped, thereby forming an undoped channel region 320.

[0064] In this embodiment, the array substrate may further include multiple scan lines 620 disposed on the active layer. The multiple scan lines 620 and multiple data lines 610 are arranged in a crisscrossing manner, and the scan lines 620 and the data lines 610 may be conductive metal lines. In this embodiment, multiple gate portions on a certain row or column may be connected to the same data line 610 to achieve synchronous gate driving.

[0065] In this embodiment, the bridging member 400 is connected to the two adjacent active portions 300 via vias. Specifically, the first end of the bridging member 400 extends downward through the via into the second doped region 330 of the first active portion 301, and the second end of the bridging member 400 extends downward through the via into the first doped region 310 of the second active portion 302. The middle portion of the bridging member 400 slopes up within the interval between the two adjacent light-shielding portions 200, forming a bridging structure with higher ends and a lower middle portion.

[0066] In this embodiment, as Figure 3 As shown, the second insulating layer 520 can be a gate insulating layer disposed between the active layer and the gate layer 900. The gate layer 900 can be disposed in the same layer as the bridging member 400 to reduce the film thickness of the array substrate and achieve thinning.

[0067] In this embodiment, as Figure 4 As shown, the gate layer 900 can also be located on the active layer and disposed on a different layer from the bridging member 400. In this case, a third insulating layer 530 needs to be provided between the gate layer 900 and the bridging member 400 to achieve insulation. The third gate insulating layer can be made of SiN. x SiO x Preparation of inorganic insulating materials.

[0068] The embodiment of the present application connects two adjacent active parts 300 by setting a bridge piece 400, so that the two adjacent active parts 300 are connected in series, thereby the channel area 320 proportion of the two series thin film transistors can be improved, and the impedance value is improved, and the off-state leakage current of the thin film transistor is reduced; moreover, the light shielding parts 200 corresponding to the two adjacent active parts 300 are also arranged at intervals, so that the problem of poor electrostatic protection process caused by the large metal layer can be solved or improved; in addition, the toughness of the bridge piece 400 is greater than the toughness of the active part 300, so that the continuity of the climbing position between the two adjacent light shielding parts 200 can be maintained, the risk of abnormal crystallization or fracture of the "active layer" of the climbing position is reduced, thereby the possibility of the large on-state current of the thin film transistor is avoided or reduced, and the display defects such as dark spots are reduced.

[0069] The embodiment of the present application also provides a display terminal, which can include a terminal body and the array substrate, and the array substrate and the terminal body are combined into one body.

[0070] The array substrate and the display terminal provided by the embodiment of the present application are described in detail above, and the principle and the implementation manner of the present application are described by using specific examples; the above embodiment is only used to help understand the method of the present application and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application range can be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. An array substrate, characterized in that, include: Substrate; A light-shielding layer is disposed on the substrate, the light-shielding layer comprising a plurality of light-shielding portions spaced apart; An active layer is disposed on the light-shielding layer, the active layer comprising a plurality of spaced-apart active portions, one of the active portions corresponding to one of the light-shielding portions; as well as A bridging element is disposed on the active layer, and two adjacent active parts are electrically connected through the bridging element. The toughness of the bridging element is greater than that of the active part. Wherein, the orthographic projection of the active part on the corresponding light-shielding part is located within the light-shielding part, such that there is a ramp area between two adjacent active parts, the ramp area has a first bottom wall and a second bottom wall, the first bottom wall is connected to the bottom wall of the active part through the second bottom wall, the first bottom wall corresponds to the gap between two adjacent active parts, and the second bottom wall corresponds to the part of the light-shielding part that extends beyond the active part, so that the first bottom wall is lower than the second bottom wall; the bridging member is located within the ramp area and crosses the first bottom wall.

2. The array substrate according to claim 1, characterized in that, The distance between two adjacent active units connected by the bridging member is 2 micrometers to 5 micrometers.

3. The array substrate according to claim 1, characterized in that, In the top view of the array substrate, the distance between the edge of the active part and the edge of the light-shielding part is 1 micrometer to 3 micrometers.

4. The array substrate according to claim 1, characterized in that, In a direction perpendicular to the array substrate, the thickness of the bridging element is greater than the thickness of the light-shielding layer.

5. The array substrate according to claim 1, characterized in that, The active portion includes a channel region and a first doped region and a second doped region located on both sides of the channel region, and the bridging member connects the first doped region and the second doped region of two adjacent active portions.

6. The array substrate according to claim 5, characterized in that, The array substrate further includes signal lines and pixel electrode layers disposed on the active layer; The active layer includes at least an adjacent first active portion and a second active portion, wherein the signal line is connected to the first active portion through a via, and the second active portion is connected to the pixel electrode layer through a via.

7. The array substrate according to claim 6, characterized in that, The array substrate further includes a first source / drain portion disposed on a first doped region of the first active portion and a second source / drain portion disposed on a second doped region of the second active portion; The signal line is connected to the first source / drain portion via a via, and the bridging member connects the second doped region of the first active portion and the first doped region of the second active portion.

8. The array substrate according to claim 5, characterized in that: The array substrate further includes a gate layer disposed on the active layer, and the orthogonal projection of the channel regions of the plurality of active portions on the gate layer is located within the gate layer.

9. The array substrate according to claim 1, characterized in that, The array substrate further includes a gate insulating layer disposed between the active layer and the bridging member, wherein the bridging member is connected to the active layer through a via.

10. A display terminal, characterized in that, It includes a terminal body and an array substrate as described in any one of claims 1 to 9, wherein the array substrate and the terminal body are integrated into one unit.

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