A high-reliability dual-state ion-gated synaptic field-effect transistor

Abstract

The invention discloses a highly reliable dual-state ion-gated synaptic field effect transistor, wherein the channel material of the field effect transistor is placed on a substrate material, the source and the drain are placed on both sides of the channel material for detecting the current passing through the channel material, an intermediate layer is introduced between the channel material and the ion source, the ion source is placed on the upper side of the intermediate layer for providing free ions, and the gate is placed on the upper side of the ion source for providing a gate pulse to migrate free ions to change the conductance of the channel material, simulating a biological memory function; the channel material is MoS2, the intermediate layer is Ti3C2O2, and when the channel material and the intermediate layer are stacked, the bottom C atoms of the intermediate layer Ti3C2O2 correspond vertically to the top S atoms of the channel material MoS2. The field effect transistor of the invention has a working state and a resting state, and the Schottky barrier formed by the intermediate layer and the channel material can suppress the tunneling of electrons, and reduce the formation probability of dendrites at the intermediate layer-ion source interface when no gate voltage is applied.

Description

Technical Field

[0001] The invention relates to the technical field of electronic devices, in particular to a dual-state ion-gated synapse-like field effect transistor with high reliability. Background Art

[0002] In order to break through the von Neumann bottleneck, people have proposed using brain-like chips to achieve brain-like computing to solve the power consumption and speed problems when processing large amounts of information. Synaptic devices, as the basic components of brain-like chips, simulate the long-term or short-term memory effects of neurons to achieve information processing, transmission and storage. Ion-gated synaptic field-effect transistors are a type of synaptic device that has been widely studied. They are usually composed of a source electrode, a drain electrode, a gate electrode, an ion source and a channel material.

[0003] The gate voltage acts as a presynaptic stimulus, affecting the speed at which ions in the ion source are adsorbed on the surface of the channel material or inserted into the middle of the channel material, which will dynamically change the conductivity of the channel material and realize the plasticity of the synaptic-like device. Due to the slow ion diffusion rate, the ion-gated synaptic-like field effect transistor can obtain a larger plasticity range and show better long-term or short-term memory effects. However, when the gate voltage is zero, the ions in the device are easy to combine with free electrons at the interface of the channel material and the ion source to form dendrites, which affects the reliability of the field effect transistor. Synaptic-like devices are in a state of zero gate voltage most of the time, so it is very important to suppress the formation of dendrites. It can be suppressed from two aspects: one is to reduce the aggregation of ions at the interface of the channel material-ion source; the other is to suppress the tunneling of free electrons in the channel material to the interface. Previous reports have proposed introducing a single-layer graphene as an intermediate layer between the channel material MoS2 and the ion source to isolate the ions from the channel material. However, due to the low Schottky barrier of the van der Waals heterojunction formed by the single-layer graphene and MoS2, the suppression of electron tunneling is not obvious. Summary of the invention

[0004] The purpose of the present invention is to provide a dual-state ion-gated synaptic field effect transistor, which introduces a higher Schottky barrier to inhibit the tunneling of electrons from the channel material to the intermediate layer-ion source interface, reduce the probability of dendrite formation, and make the device have better reliability.

[0005] The technical solution to achieve the purpose of the present invention is: a highly reliable dual-state ion-gated synaptic field effect transistor, the field effect transistor is composed of a source, a gate, a drain, an ion source, a channel material, a substrate and an intermediate layer; the channel material of the field effect transistor is placed on the substrate material, the source and the drain are placed on both sides of the channel material for detecting the current passing through the channel material, an additional intermediate layer is introduced between the channel material and the ion source, the ion source is placed on the upper side of the intermediate layer for providing free ions, and the gate is placed on the upper side of the ion source for providing gate pulses to migrate free ions to change the conductivity of the channel material and simulate biological memory function; the channel material is MoS2, and the intermediate layer is Ti3C2O2. When the channel material and the intermediate layer are stacked, the bottom C atoms of the intermediate layer Ti3C2O2 vertically correspond to the top S atoms of the channel material MoS2;

[0006] The field effect tube has a working state and a resting state; the Schottky barrier formed by the middle layer and the channel material can suppress the tunneling of electrons and reduce the probability of dendrite formation at the middle layer-ion source interface when no gate voltage is applied.

[0007] Compared with the prior art, the present invention has the following significant advantages: (1) The field effect transistor introduces an additional layer of two-dimensional material as an intermediate layer between the channel material and the ion source. According to the presence or absence of ions in the intermediate layer and the channel material, the state of the field effect transistor can be divided into a working state and a resting state; (2) When no gate voltage is applied, since the intermediate layer and the channel material form a van der Waals heterojunction, a higher Schottky barrier is introduced, thereby suppressing the tunneling of electrons from the channel material to the intermediate layer-ion source interface (ion aggregation area), reducing the probability of dendrite formation and making the device more reliable; (3) This ion-gated synaptic field effect transistor has important potential applications in the design and development of a new generation of brain-like chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a structural schematic diagram of a high-reliability dual-state ion-gated synapse-like field effect transistor of the present invention.

[0009] Figure 2 The diagram is a working principle diagram of a high-reliability dual-state ion-gated synapse-like field effect transistor of the present invention.

[0010] Figure 3 Schematic diagram of six different types of stacking of intermediate layer Ti3C2O2 and channel material MoS2 in the embodiment.

[0011] Figure 4It is the energy band diagram of the six stacked MoS2 / Ti3C2O2 heterojunctions in the embodiment and the state density diagram of MoS2 in the corresponding heterojunction. The energy bands marked with bold parts in the energy band diagram are the conduction band bottom and valence band top of the energy band contributed by MoS2, and the numbers marked in the energy band diagram are the calculated Schottky barriers. DETAILED DESCRIPTION

[0012] The present invention has a highly reliable dual-state ion-gated synaptic field effect transistor, in which an additional layer of two-dimensional material is introduced as an intermediate layer between the channel material and the ion source. Since ions need to overcome a relatively high energy barrier to pass through the intermediate layer, a certain gate voltage is required to assist in achieving a higher ion flux. According to the presence or absence of ions in the intermediate layer and the channel material, the state of the field effect transistor can be divided into a working state and a resting state. When no gate voltage is applied, since the intermediate layer and the channel material form a van der Waals heterojunction, a relatively high Schottky barrier is introduced, so that the tunneling of electrons from the channel material to the intermediate layer-ion source interface (ion aggregation area) is suppressed, the probability of dendrite formation is reduced, and the device has better reliability.

[0013] Combination Figure 1 The present invention discloses a highly reliable dual-state ion-gated synaptic field effect transistor, which is composed of a source, a gate, a drain, an ion source, a channel material, a substrate and an intermediate layer; the channel material of the field effect transistor is placed on the substrate material, the source and the drain are placed on both sides of the channel material to detect the current passing through the channel material, an additional intermediate layer is introduced between the channel material and the ion source to improve the reliability of the field effect transistor, the ion source is placed on the upper side of the intermediate layer to provide free ions, and the gate is placed on the upper side of the ion source to provide a gate pulse to migrate free ions to change the conductivity of the channel material and simulate the biological memory function; the channel material is MoS2, and the intermediate layer is Ti3C2O2. When the channel material and the intermediate layer are stacked, the bottom C atoms of the intermediate layer Ti3C2O2 vertically correspond to the top S atoms of the channel material MoS2;

[0014] The field effect tube has a working state and a resting state; the high Schottky barrier formed by the middle layer and the channel material can suppress the tunneling of electrons and reduce the probability of dendrite formation at the middle layer-ion source interface when no gate voltage is applied, so that the field effect tube has high reliability.

[0015] Furthermore, the channel material of the field effect transistor is transferred to the substrate by a mechanical stripping method and is selected according to the measurement results of an optical microscope and an atomic force microscope.

[0016] Furthermore, the source and drain of the field effect tube are arranged on the upper side of the channel material by vacuum evaporation, and the gate is arranged on the upper side of the ion source by vacuum evaporation. The intermediate layer material of the field effect tube is prepared by wet etching and transferred to the upper side of the channel material. The ion source of the field effect tube is evenly covered on the upper side of the intermediate layer by spin coating.

[0017] Furthermore, the rest state is the state of the field effect transistor when there are no ions in the intermediate layer and the channel material, and the working state is the state of the field effect transistor when there are ions in the intermediate layer and the channel material.

[0018] Furthermore, in the resting state, the ions in the ion source obtain energy close to or higher than the ion energy barrier of the middle layer with the assistance of the gate voltage, and the ions can pass through the middle layer to reach the channel material, and the field effect tube changes from the resting state to the working state, and the corresponding gate voltage is the stimulation voltage V e In the working state, the ions in the middle layer and the channel material obtain an ion energy barrier with energy close to or higher than that of the middle layer with the assistance of the reverse gate voltage, and the ions can reversely pass through the middle layer back to the ion source, and the field effect tube changes from the working state to the resting state. The reverse gate voltage is the suppression voltage V i .

[0019] Furthermore, in the working state, ions are inserted into the channel material or adsorbed on the surface of the channel material under the action of the gate voltage, so that the conductivity of the channel material changes, thereby generating a long-term or short-term memory effect. The gate voltage is the working voltage V w .

[0020] Furthermore, in the resting state, if the gate voltage is greater than the stimulation voltage V e The ions are small, and cannot overcome the ion energy barrier of the middle layer, that is, they cannot pass through the middle layer to reach the channel material, so they will not change the conductivity of the channel material and will not produce long-term or short-term memory effect.

[0021] Furthermore, when no gate voltage is applied, some ions gather at the interface between the intermediate layer and the ion source. At the same time, the heterojunction formed by the intermediate layer and the channel material has a higher Schottky barrier, which can inhibit the tunneling of electrons in the channel material to the interface between the intermediate layer and the ion source, i.e., the ion gathering area, thereby reducing the probability of dendrite formation and making the field effect transistor highly reliable.

[0022] The present invention is further described in detail below with reference to the accompanying drawings and specific examples.

[0023] Example 1

[0024] Combination Figure 2The present invention proposes a dual-state ion-gated synaptic field effect transistor with high reliability, and the specific working principle is as follows.

[0025] 1. Figure 2 (a) Initial state, no gate voltage is applied, and the field effect tube is in a resting state. The ions are evenly distributed in the ion source, and a small part is gathered on the upper surface of the middle layer. Due to the existence of the middle layer, it is difficult for the ions to spontaneously diffuse to the upper surface of the channel material, and the field effect tube is maintained in a resting state. Since the heterojunction composed of the middle layer and the channel material has a high Schottky barrier, the probability of electrons in the channel material tunneling to the middle layer-ion source interface (ion gathering area) is very low, which reduces the probability of dendrites forming on the upper surface of the middle layer, eliminates the possibility of dendrites forming on the upper surface of the channel material, and makes the device highly reliable.

[0026] 2. Figure 2 (b) The FET is in a resting state, where the gate voltage is much smaller than the stimulus voltage (V g <<V e ), the energy obtained by the ions is much smaller than the energy barrier of the middle layer, that is, the probability of tunneling through the middle layer is close to zero, so the field effect tube shown is maintained in a resting state.

[0027] 3. Figure 2 (c) The FET is in working state, when the gate voltage is greater than or equal to the stimulus voltage (V g ≥V e ), the energy obtained by the ions in the ion source is close to or higher than the ion energy barrier of the middle layer, and can pass through the middle layer, and the field effect tube completes the transition from the resting state to the working state.

[0028] 4. Figure 2 The field effect transistor shown in (d) is in a working state. Under the stimulation of a working pulse, ions are adsorbed or inserted into the channel material, and the conductivity of the channel material is changed, so that the field effect transistor produces a short-term or long-term memory effect to simulate the function of neural synapses in the human brain.

[0029] 5. Figure 2 (e) The FET is in a quiescent state. If the reverse gate voltage is greater than or equal to the suppression voltage (|V g |≥|V i |), the energy obtained by the ions is close to or higher than the ion energy barrier of the intermediate layer, then the ions leave the channel material and pass through the intermediate layer, and the field effect transistor completes the transition from the working state to the resting state.

[0030] 6. Figure 2 (f) shows the relationship between the source-drain current of the field effect tube and time under different gate pulses. At the initial moment, the field effect tube is in a resting state. At this time, when the gate is applied with a working voltage less than the stimulation voltage (V w<V e ), the source-drain current has no obvious change, indicating that the ions in the ion source have failed to pass through the middle layer, and the field effect tube is still in a resting state. In the resting state, when the stimulation voltage is applied to the gate, the source-drain current gradually rises, indicating that the ions in the ion source have passed through the middle layer, and the field effect tube has changed from the resting state to the working state. In the working state, the working voltage applied to the gate causes the source-drain current to increase and decrease nonlinearly, and the field effect tube works normally. In the working state, when the suppression voltage is applied to the gate, the source-drain current gradually decreases, indicating that the ions leave the channel material and pass through the middle layer, and the field effect tube completes the transition from the working state to the resting state.

[0031] 1. Device design

[0032] Taking gel-like LiClO4 as the ion source, double-layer two-dimensional material MoS2 as the channel material, and single-layer two-dimensional material Ti3C2O2 as the intermediate layer as an example, the resting state, working state and stability of the ion-gated synaptic field-effect transistor are studied.

[0033] In an ion-gated synaptic field effect transistor, ions migrate and insert into the channel material or adsorb on the surface of the channel material under the action of the gate voltage. After the gate voltage is removed, the ions gradually diffuse out of the channel material due to the concentration difference. When lithium ions are introduced to the surface or between the layers of the double-layer two-dimensional material MoS2, it will transform from the 2H phase to the 1T phase, resulting in a corresponding change in conductivity. When the gate working pulse arrives, since the ion diffusion rate is slower than the migration rate, the MoS2 conductivity will increase with the increase in the number of applied gate working pulses, that is, the memory effect of MoS2 conductivity is exhibited. The middle layer Ti3C2O2 has a high ion energy barrier, which makes the field effect transistor have obvious resting state and working state, and a high gate pulse voltage needs to be applied to it to complete the transition between the two states. When no gate voltage is applied, the middle layer Ti3C2O2 forms a van der Waals heterojunction with the channel material MoS2, introducing a higher Schottky barrier. This inhibits the tunneling of electrons from the channel material to the middle layer Ti3C2O2-ion source LiClO4 interface (ion aggregation area), reduces the probability of dendrite formation, and makes the device highly reliable.

[0034] 2. Structural optimization

[0035] In order to ensure the correctness of the calculation results of Schottky barrier and energy barrier, density functional theory is first used to optimize the structure of the two-dimensional materials MoS2, Ti3C2O2 and the MoS2 / Ti3C2O2 van der Waals heterojunction they constitute. The lattice constant of MoS2 after structure optimization is The lattice constant of Ti3C2O2 after structure optimization is For the MoS2 / Ti3C2O2 heterojunction, six different stackings were considered, such as Figure 3 As shown. According to the difference in relative positions between Mo and S atoms in MoS2 and Ti and C atoms in Ti3C2O2, Figure 3 The stacking modes of (a) to (f) are named Type I, Type II, Type III, Type IV, Type V and Type VI respectively. The interlayer spacing and interlayer adsorption energy after structural optimization are shown in Table 1.

[0036] Table 1 Interlayer spacing and interlayer binding energy of MoS2 / Ti3C2O2 heterojunctions under six different stacking modes

[0037]

[0038] 1. Schottky barrier calculation

[0039] The Schottky barrier is calculated as the difference between the bottom energy of the conduction band attributed to MoS2 and the Fermi level in the energy band of the heterojunction. Therefore, the energy band diagram of the MoS2 / Ti3C2O2 heterojunction was calculated using density functional theory, and the partial wave state density diagrams of Mo, S and MoS2 were analyzed, as shown in Figure 2. Figure 4 As shown, Figure 4 The stacking methods of (a) to (f) are named Type Ⅰ, Type Ⅱ, Type Ⅲ, Type Ⅳ, Type Ⅴ and Type Ⅵ respectively. It can be seen that there are still clear conduction bands and valence bands in the band structure attributed to MoS2 in the figure. According to the calculation method of Schottky barrier, the Schottky barrier of MoS2 / Ti3C2O2 heterojunctions with six different stacking methods is in the range of 1.373eV to 1.632eV. The formula for electron tunneling probability is as follows:

[0040]

[0041] in is Planck constant, m is electron mass, V0 is barrier size, and D is barrier thickness. Here, the stacking mode with the highest Schottky barrier (Type III) is selected, and the barrier height is substituted into the formula to obtain the probability of electron tunneling of 1.98%. At the same time, the Schottky barrier and electron tunneling probability formed by stacking Ti3C2X2 (X=F, OH) containing two other common groups and graphene and MoS2 are also calculated, as shown in Table 2. Compared with graphene and other Ti3C2X2 (X=F, OH) adsorbed with different groups, the probability of electron tunneling in the heterojunction formed by Ti3C2O2 and MoS2 is the lowest.

[0042] Table 2: Schottky barriers and corresponding electron tunneling probabilities of MoS2 / Ti3C2F2, MoS2 / Ti3C2OH2, MoS2 / Ti3C2O2, and MoS2 / Graphene heterojunctions

[0043]

[0044] 2. Energy barrier calculation

[0045] By combining density functional theory with transition state search, it is calculated that the energy barrier that lithium ions need to overcome to pass through a single layer of Ti3C2O2 is 12.85 eV. The tunneling probability of ions can be obtained by the following formula:

[0046] k p =e -βU

[0047] Where β is a constant and U is the barrier height. Substituting the energy barrier into the formula, we can obtain that the probability of ion tunneling is close to zero (3.6×10 -197 %), which means that after the introduction of the intermediate layer Ti3C2O2, ions can hardly pass through the intermediate layer in the rest state and without gate voltage to complete the transition to the working state. The flux of ions passing through the intermediate layer Ti3C2O2 is different under different gate voltages, and the relevant formula is as follows:

[0048]

[0049] Where β is a constant, U is the barrier height, and V is the energy obtained by lithium ions from the gate pulse. Here, the working pulse is defined as 3V, the stimulation pulse is 12V, and the inhibition pulse is -12V (equal to the stimulation pulse but opposite in direction). In the resting state, if the working voltage is applied to the gate, according to the flux formula, the flux of ions passing through the middle layer Ti3C2O2 is almost negligible (1.679×10 -127 atoms·μm -2 ·s -1 ). If the gate is stimulated by a voltage in the resting state, according to the flux formula, the flux of ions passing through the middle layer Ti3C2O2 is 2.288×10 7 atoms·μm -2 ·s -1 If the number of lithium ions entering the working state is required to just occupy all the surface adsorption sites of MoS2 (that is, each MoS2 unit cell adsorbs one lithium ion), it only needs to apply a 44ms stimulation pulse to meet the requirement. In the working state, if the suppression voltage is not applied, the ions cannot diffuse back to the ion source due to the existence of the middle layer. Only after the suppression voltage is applied can the ions pass through the middle layer and return to the ion source.

[0050] In summary, the working voltage cannot complete the conversion between the two states of the field effect tube. Only when a specific stimulation voltage and inhibition voltage arrive can the field effect tube undergo state conversion, and the high level duration of the stimulation pulse and the inhibition pulse is relatively short. At the same time, when there is no gate voltage, the ions at the interface of the middle layer Ti3C2O2-ion source LiClO4 cannot diffuse to the surface of the channel material. At the same time, combined with the calculation results of the Schottky barrier of the above-mentioned MoS2 / Ti3C2O2 heterojunction and the probability of electron tunneling, the tunneling probability of electrons from the channel material to the interface of the middle layer Ti3C2O2-ion source LiClO4 (ion aggregation area) is very small, which reduces the probability of dendrite formation and makes the device highly reliable.

Claims

1. A high-reliability dual-state ion-gated synaptic field effect transistor, characterized in that: The field effect tube is composed of a source, a gate, a drain, an ion source, a channel material, a substrate and an intermediate layer; the channel material of the field effect tube is placed on the substrate, the source and the drain are placed on both sides of the channel material for detecting the current passing through the channel material, an additional intermediate layer is introduced between the channel material and the ion source, the ion source is placed on the upper side of the intermediate layer for providing free ions, and the gate is placed on the upper side of the ion source for providing gate pulses to migrate free ions to change the conductivity of the channel material and simulate biological memory function; the channel material is MoS2, and the intermediate layer is Ti3C2O2. When the channel material and the intermediate layer are stacked, the bottom C atoms of the intermediate layer Ti3C2O2 vertically correspond to the top S atoms of the channel material MoS2; The field effect tube has a working state and a resting state; the Schottky barrier formed by the middle layer and the channel material can suppress the tunneling of electrons and reduce the probability of dendrite formation at the middle layer-ion source interface when no gate voltage is applied.

2. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 1, characterized in that: The channel material of the field effect transistor is transferred to the substrate by a mechanical stripping method and is selected according to the measurement results of an optical microscope and an atomic force microscope.

3. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 1, characterized in that: The source and drain of the field effect tube are arranged on the upper side of the channel material by vacuum evaporation method, and the gate is arranged on the upper side of the ion source by vacuum evaporation method.

4. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 1, characterized in that: The middle layer of the field effect tube is prepared by a wet etching method and transferred to the upper side of the channel material.

5. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 1, characterized in that: The ion source of the field effect tube is evenly covered on the upper side of the middle layer through a spin coating process.

6. The highly reliable dual-state ion-gated synaptic field effect transistor according to any one of claims 1 to 5, characterized in that: The resting state is the state of the field effect transistor when there are no ions in the intermediate layer and the channel material, and the working state is the state of the field effect transistor when there are ions in the intermediate layer and the channel material.

7. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 6, characterized in that: In the resting state, the ions in the ion source obtain energy equal to or higher than the ion energy barrier of the middle layer with the assistance of the gate voltage, and the ions can pass through the middle layer to reach the channel material, and the field effect tube changes from the resting state to the working state. The corresponding gate voltage is the stimulation voltage. V e In the working state, the ions in the middle layer and the channel material obtain an ion energy barrier with energy close to or higher than that of the middle layer with the assistance of the reverse gate voltage, and the ions can reversely pass through the middle layer and return to the ion source, and the field effect tube changes from the working state to the resting state. The reverse gate voltage is the suppression voltage. V i .

8. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 6, characterized in that: In the working state, ions are inserted into the channel material or adsorbed on the surface of the channel material under the action of the gate voltage, causing the conductivity of the channel material to change, thereby producing a long-term or short-term memory effect. The gate voltage is the working voltage. V w .

9. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 7, characterized in that: In the resting state, if the gate voltage is greater than the stimulation voltage V e The ions are small, and cannot overcome the ion energy barrier of the middle layer, that is, they cannot pass through the middle layer to reach the channel material, so they will not change the conductivity of the channel material and will not produce long-term or short-term memory effect.

10. The high-reliability dual-state ion-gated synaptic field effect transistor according to claim 7, characterized in that: When no gate voltage is applied, some ions gather at the interface between the intermediate layer and the ion source. At the same time, the heterojunction formed by the intermediate layer and the channel material has a Schottky barrier, which can inhibit the tunneling of electrons in the channel material to the interface between the intermediate layer and the ion source, i.e., the ion gathering area, and reduce the probability of dendrite formation.

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