Silicon carbide power semiconductor device structure

Abstract

The application provides a silicon carbide power semiconductor device structure, which comprises a first conductive type substrate, a first conductive type drift region, a second conductive type body region, a first conductive type source region, a second conductive type base region, a junction field effect transistor region, a second conductive type shielding region, a gate structure, an insulating layer and a source metal layer. The source contact window is arranged to have at least one side line which does not exceed the edge of the second conductive type body region corresponding to the side line, so as to reduce the area of the source contact window and make the source metal layer only locally contact the first conductive type source region. The application can effectively reduce the total area of the silicon carbide power semiconductor device structure, increase the channel length and the ratio of the area of the junction field effect transistor region to the total area of the device structure, i.e. increase the channel density and the density of the junction field effect transistor region, and further reduce the specific on-resistance of the device structure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor device design, and particularly relates to a silicon carbide power semiconductor device structure. BACKGROUND

[0002] The development of power electronic devices based on silicon material has reached a bottleneck period, and it is difficult to meet the requirements of rectifier and switching devices in the future power electronic system in terms of super high voltage, high frequency, high temperature and the like. As the third generation of semiconductor materials, silicon carbide semiconductor material not only has three times the band gap of silicon semiconductor material and ten times the critical breakdown field of silicon material, but also has a very high electron saturation drift speed and thermal conductivity, so that the power device based on silicon carbide material has great advantages in high temperature, high frequency and high power fields.

[0003] Silicon carbide metal oxide semiconductor field effect transistor (silicon carbide power semiconductor) devices have high input impedance and fast switching speed, and are currently widely used in low-voltage and high switching frequency fields. However, with the development of power electronic systems, the blocking voltage of power devices is increasing, and the disadvantages of silicon carbide MOSFET devices are gradually revealed. As unipolar devices, the on-resistance of silicon carbide power semiconductor devices increases rapidly with the increase of their blocking voltage, and in addition to the problems of low power loss and system efficiency, it is difficult for them to play an important role in the super high voltage field, and therefore lack of good competitiveness. The silicon carbide bipolar power device will occur in its drift layer in the normal conduction state. The conductance modulation effect greatly reduces the on-resistance of the drift layer and the on-voltage drop of the entire device, and greatly overcomes the shortcomings of high-voltage silicon carbide MOSFET devices.

[0004] However, the channel density and JFET device area density of the existing silicon carbide power semiconductor device are not high, so that the on-resistance of the existing silicon carbide power semiconductor device is difficult to further reduce. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a silicon carbide power semiconductor device structure, which solves the problem that the channel density and JFET device area density of the silicon carbide power semiconductor device structure in the prior art are not high, thereby making the on-resistance of the existing silicon carbide power semiconductor device difficult to further reduce.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a silicon carbide power semiconductor device structure, which comprises: a first conductive type substrate; a first conductive type drift region located on the first conductive type substrate;

[0007] a second conductive type body region in the first conductive type drift region; a first conductive type source region surrounding the second conductive type body region; a second conductive type base region surrounding the first conductive type source region; a second conductive type shield region surrounding the second conductive type body region and under the first conductive type source region and the second conductive type base region; a junction field effect transistor region surrounding the second conductive type base region and the second conductive type shield region;

[0008] a gate structure covering the junction field effect transistor region, the second conductive type base region and part of the first conductive type source region; an insulating layer covering the surface of the device structure, the insulating layer having a source contact window, at least one edge line of the source contact window not exceeding the edge of the second conductive type body region corresponding to the edge line; a source metal layer filling the source contact window.

[0009] Optionally, the source contact window has two edge lines not exceeding the edges of the second conductive type body region corresponding to the two edge lines, and the source contact window is axisymmetric with respect to the central axis of the second conductive type body region.

[0010] Optionally, the source contact window has three edge lines not exceeding the edges of the second conductive type body region corresponding to the three edge lines.

[0011] Optionally, the distance between the outer edge of the second conductive type body region and the inner edge of the gate structure is 0.5-0.6 microns.

[0012] Optionally, the distance between the outer edge of the second conductive type body region and the outer edge of the first conductive type source region is 1-1.1 microns.

[0013] Optionally, the distance between the outer edge of the contact window and the inner edge of the gate structure is 0.8-0.9 microns.

[0014] Optionally, the distance between the edge of the contact window exceeding the second conductive type body region and the second conductive type body region is 1-1.1 microns.

[0015] Optionally, the distance between the inner edge of the gate structure and the outer edge of the second conductive type base region is 1-1.1 microns.

[0016] Optionally, the distance between the outer edge of the first conductive type source region and the outer edge of the second conductive type base region is 0.5-0.6 microns.

[0017] Optionally, the distance between the outer edge of the second conductive type base region and the outer edge of the junction field effect transistor region is 0.5-0.6 microns.

[0018] Optionally, the width of the second-conductivity-type body region is 1.8-2 microns.

[0019] Optionally, the doping concentration of the second-conductivity-type base region, the second-conductivity-type shield region and the second-conductivity-type base region decreases in turn.

[0020] Optionally, the doping concentration of the junction field effect transistor region is greater than the doping concentration of the first-conductivity-type drift region.

[0021] Optionally, the channel density of the silicon carbide power semiconductor device structure is greater than or equal to 0.48 microns -1 , the junction field effect transistor region density of the silicon carbide power semiconductor device structure is greater than or equal to 0.29, and the specific on-resistance of the junction field effect transistor region is less than or equal to 3.6 mohm*cm 2 , wherein the channel density is the ratio of the channel length to the total area of the silicon carbide power semiconductor device structure, and the junction field effect transistor region density is the ratio of the area of the junction field effect transistor region to the total area of the silicon carbide power semiconductor device structure.

[0022] As described above, the silicon carbide power semiconductor device structure of the present application has the following beneficial effects:

[0023] The present application realizes a silicon carbide power semiconductor device structure with low specific on-resistance without changing the design rule, by setting the source contact window to have at least one side line not exceeding the edge of the second-conductivity-type body region corresponding to the side line, thereby reducing the area of the source contact window and making the source metal layer only contact the first-conductivity-type source region in a local area. The present application can effectively further reduce the total area of the silicon carbide power semiconductor device structure, increase the channel length and the ratio of the area of the junction field effect transistor region to the total area of the device structure, i.e., increase the channel density and the density of the junction field effect transistor region, and thereby reduce the specific on-resistance of the device structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A layout design schematic diagram of the silicon carbide power semiconductor device structure of the embodiment 1 of the present application is shown.

[0025] Figure 2 A cross-sectional structure schematic diagram of the silicon carbide power semiconductor device structure of the embodiment 1 of the present application is shown.

[0026] Figure 3 A layout design schematic diagram of the silicon carbide power semiconductor device structure of the embodiment 2 of the present application is shown.

[0027] ELEMENT NUMBER EXPLANATION

[0028] 101 First type of conductivity substrate

[0029] 102 Drain metal layer

[0030] 103 First conductivity type drift region

[0031] 104 Second type of conductivity volume region

[0032] 105 First conductivity type source region

[0033] 106 Second conductivity type base region

[0034] 107 Second conductivity type shielding area

[0035] 108 Junction Field-Effect Transistor Region

[0036] 109 Gate dielectric layer

[0037] 110 Polycrystalline Silicon Gate Layer

[0038] 111 Insulation layer

[0039] 112 Source Contact Window

[0040] 113 Source Metal Layer Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0043] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0044] In the context of this application, a structure described as being "on" a second feature "over" a first feature can include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features can not be in direct contact.

[0045] It should be noted that the drawings provided in this embodiment only schematically illustrate the basic concept of the present application, and thus only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and proportion of each component in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0046] Embodiment 1

[0047] As shown in Figure 1 and Figure 2 , wherein, Figure 2 is shown as Figure 1 a cross-sectional structure schematic diagram at a-a'. This embodiment provides a silicon carbide power semiconductor device structure, which includes a first conductive type substrate 101, a first conductive type drift region 103, a second conductive type body region 104, a first conductive type source region 105, a second conductive type base region 106, a junction field effect transistor region 108, a second conductive type shielding region 107, a gate structure, an insulating layer 111 and a source metal layer 113. During the on-state operation of the silicon carbide power semiconductor device structure, a suitable gate voltage (for example, at or above the threshold voltage of the silicon carbide power semiconductor device structure) can cause a reverse type layer to be formed in the channel region (the second conductive type base region 106) under the gate structure, and cause the conduction path to be enhanced due to the accumulation of carriers in the junction field effect transistor region 108 (JFET region), thereby allowing current to flow from the drain metal layer 102 to the source metal layer 113, realizing the conduction of the silicon carbide power semiconductor device structure.

[0048] In one embodiment, the first conductive type is N-type conduction, and the second conductive type is P-type conduction. In other embodiments, the first conductive type can also be P-type conduction, and the second conductive type can also be N-type conduction.

[0049] As shown in Figure 2 , the first conductive type substrate 101 is an N-type heavily doped silicon carbide substrate, and the thickness of the substrate can be 300-400 microns, and the resistivity of the substrate can be about 0.02 Ω*cm. A drain metal layer 102 is formed on the back surface of the substrate, and the drain metal layer 102 can be formed by a metal evaporation process and an annealing process.

[0050] As shown in Figure 2As shown, the first conductivity type drift region 103 is located on the first conductivity type substrate 101 and can be formed by epitaxial processing. The doping concentration of the first conductivity type drift region 103 can be 6 × 10⁻⁶. 15 cm -1 ~9×10 15 cm -1 For example, it can be 8×10 15 cm -1 The thickness of the conductive drift region can be 8 to 12 micrometers, for example, 10 micrometers.

[0051] like Figure 2 As shown, the second conductivity type body region 104 is located within the first conductivity type drift region 103. The second conductivity type body region 104 can be, for example, rectangular, and can be formed by ion implantation.

[0052] like Figure 2 As shown, the first conductivity type source region 105 is a rectangular ring surrounding the second conductivity type body region 104, and it can be formed by ion implantation.

[0053] like Figure 2 As shown, the second conductivity type base region 106 is a rectangular annular ring surrounding the first conductivity type source region 105, and it can be formed by ion implantation. In one embodiment, the thickness of the second conductivity type base region 106 is the same as the thickness of the first conductivity type source region 105.

[0054] like Figure 2 As shown, the junction field-effect transistor region 108 (JFET region) is a rectangular ring surrounding the second conductivity type base region 106, and it can be formed by ion implantation. The bottom of the junction field-effect transistor region 108 is in contact with the first conductivity type drift region 103. In one embodiment, the doping concentration of the junction field-effect transistor region 108 is greater than the doping concentration of the first conductivity type drift region 103. For example, in this embodiment, the doping concentration of the junction field-effect transistor region 108 can be 3 × 10⁻⁶. 16 cm -1 ~5×10 16 cm -1 Specifically, it can be 3×10 16 cm -1 .

[0055] like Figure 2 As shown, the second conductivity type shielding region 107 is located below the first conductivity type source region 105 and the second conductivity type base region 106, and is formed in a rectangular ring around the second conductivity type body region 104. It can be formed by ion implantation process.

[0056] In one embodiment, the doping concentrations of the second conductivity type base region 106, the second conductivity type shielding region 107, and the second conductivity type base region 106 decrease sequentially. For example, in this embodiment, the doping concentration of the second conductivity type base region 106 can be 5 × 10⁻⁶. 19 cm -1 The doping concentration of the second conductivity type shielding region 107 can be 5 × 10⁻⁶. 19 cm -1 The doping concentration of the base region 106 of the second conductivity type can be 9 × 10⁶. 18 cm -1 The second conductivity type base region 106, the second conductivity type shielding region 107, and the second conductivity type base region 106 together enclose the first conductivity type source region 105. In one embodiment, the bottoms of the second conductivity type base region 106, the second conductivity type shielding region 107, and the junction field-effect transistor region 108 are flush.

[0057] like Figure 2 As shown, the gate structure covers the junction field-effect transistor region 108, the second conductivity type base region 106, and a portion of the first conductivity type source region 105. In one embodiment, the gate structure includes a gate dielectric layer 109 and a polysilicon gate layer 110 stacked sequentially. For example, the gate dielectric layer 109 can be formed by thermal oxidation or deposition, the polysilicon upper layer can be formed by deposition, and a gate structure of a corresponding shape can be formed by photolithography and etching processes.

[0058] like Figure 2 As shown, the insulating layer 111 covers the surface of the device structure. The insulating layer 111 can be, for example, silicon dioxide, and can be formed by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). The insulating layer 111 has a source contact window 112, and the source contact window 112 has at least one edge that does not extend beyond the edge of the second conductivity type body region 104 corresponding to the edge. The source metal layer 113 fills the source contact window 112. The aforementioned edge and the edge corresponding to the edge refer to the edge that is close to the edge and parallel to the edge.

[0059] For example, in this embodiment, such as Figure 1 As shown, the source contact window 112 has three side lines that do not extend beyond the edges corresponding to the three side lines of the second conductivity type body region 104. In this embodiment, by setting the three side lines of the source contact window 112 to not extend beyond the edges corresponding to the three side lines of the second conductivity type body region 104, the area of ​​the source contact window 112 can be greatly reduced, thereby significantly reducing the total area of ​​the silicon carbide power semiconductor device structure.

[0060] like Figure 1 As shown, as an example, the distance A between the outer edge of the second conductivity type body region 104 and the inner edge of the gate structure is 0.5 to 0.6 micrometers. The distance B between the outer edge of the second conductivity type body region 104 and the outer edge of the first conductivity type source region 105 is 1 to 1.1 micrometers. The distance C between the outer edge of the contact window and the inner edge of the gate structure is 0.8 to 0.9 micrometers. The distance D between the edge of the contact window extending beyond the second conductivity type body region 104 and the second conductivity type body region 104 is 1 to 1.1 micrometers. The distance E between the inner edge of the gate structure and the outer edge of the second conductivity type base region 106 is 1 to 1.1 micrometers. The distance F between the outer edge of the first conductivity type source region 105 and the outer edge of the second conductivity type base region 106 is 0.5 to 0.6 micrometers. The distance G between the outer edge of the second conductivity type base region 106 and the outer edge of the junction field-effect transistor region 108 is 0.5 to 0.6 micrometers. The width I of the second conductive type body region 104 is 1.8 to 2 micrometers.

[0061] In one embodiment, the distance A between the outer edge of the second conductivity type body region 104 and the inner edge of the gate structure is 0.5 micrometers. The distance B between the outer edge of the second conductivity type body region 104 and the outer edge of the first conductivity type source region 105 is 1 micrometer. The distance C between the outer edge of the contact window and the inner edge of the gate structure is 0.8 micrometers. The distance D between the edge of the contact window extending beyond the second conductivity type body region 104 and the second conductivity type body region 104 is 1 micrometer. The distance E between the inner edge of the gate structure and the outer edge of the second conductivity type base region 106 is 1 micrometer. The distance F between the outer edge of the first conductivity type source region 105 and the outer edge of the second conductivity type base region 106 is 0.5 micrometers. The distance G between the outer edge of the second conductivity type base region 106 and the outer edge of the junction field-effect transistor region 108 is 0.5 micrometers. The width I of the second conductivity type body region 104 is 1.8 micrometers. In this embodiment, the total area of ​​the silicon carbide power semiconductor device structure can be reduced to 6 micrometers × 6.7 micrometers.

[0062] Since this embodiment sets the three edges of the source contact window 112 to not exceed the edges corresponding to the three edges of the second conductivity type body region 104, the distance A between the outer edge of the second conductivity type body region 104 and the inner edge of the gate structure and the distance B between the outer edge of the second conductivity type body region 104 and the outer edge of the first conductivity type source region 105 can be greatly reduced, thereby greatly reducing the overall area of ​​the silicon carbide power semiconductor device structure. At the same time, the distance F (i.e., channel length) between the outer edge of the first conductivity type source region 105 and the outer edge of the second conductivity type base region 106 and the distance G between the outer edge of the second conductivity type base region 106 and the outer edge of the junction field-effect transistor region 108 can be kept almost unchanged, thereby increasing the ratio of the channel length and the area of ​​the junction field-effect transistor region 108 to the total area of ​​the device structure, that is, increasing the channel density and the density of the junction field-effect transistor region 108, thereby reducing the specific on-resistance of the device structure.

[0063] In one embodiment, through the above design, the channel density of the silicon carbide power semiconductor device structure is greater than or equal to 0.48 μm. -1 The junction field-effect transistor (JFET) region 108 density of the silicon carbide power semiconductor device structure is greater than or equal to 0.29, and the specific on-resistance of the JFET region 108 is less than or equal to 3.6 mol / cm². 2 The channel density is the ratio of the channel length to the total area of ​​the silicon carbide power semiconductor device structure, and the junction field-effect transistor region 108 density is the ratio of the area of ​​the junction field-effect transistor region 108 to the total area of ​​the silicon carbide power semiconductor device structure.

[0064] Example 2

[0065] like Figure 3 As shown, this embodiment provides a silicon carbide power semiconductor device structure, the basic structure of which is as in Embodiment 1. The difference from Embodiment 1 is that the source contact window 112 has two side lines that do not extend beyond the edges of the second conductivity type body region 104 and the corresponding two side lines, and the source contact window 112 is axially symmetrical with respect to the central axis of the second conductivity type body region 104.

[0066] Compared with the embodiment 1, by the configuration of the present embodiment, the distance A between the outer edge of the second conductive type body region 104 and the inner edge of the gate structure and the distance B between the outer edge of the second conductive type body region 104 and the outer edge of the first conductive type source region 105 can also be effectively reduced, and the channel density and the density of the junction field effect transistor region 108 are increased, and the specific on-resistance of the device structure is reduced. Further, since the source contact window 112 is arranged symmetrically relative to the central axis of the second conductive type body region 104, the first conductive type source region 105 can be provided with larger and more symmetrical current, the uniformity of the current is improved, and the on performance of the device is improved.

[0067] As described above, the silicon carbide power semiconductor device structure of the present application has the following beneficial effects:

[0068] The present application realizes a low specific on-resistance silicon carbide power semiconductor device structure without changing the design rule, by setting the source contact window to have at least one edge line not exceeding the edge of the second conductive type body region corresponding to the edge line, thereby reducing the area of the source contact window, and making the source metal layer only locally contact the first conductive type source region. The present application can effectively further reduce the total area of the silicon carbide power semiconductor device structure, increase the ratio of the channel length and the area of the junction field effect transistor region to the total area of the device structure, i.e. increase the channel density and the density of the junction field effect transistor region, and further reduce the specific on-resistance of the device structure.

[0069] Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0070] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A silicon carbide power semiconductor device structure, characterized by, The device structure comprises: a first-conductivity-type substrate; a first-conductivity-type drift region on the first-conductivity-type substrate; a second-conductivity-type body region in the first-conductivity-type drift region; a first-conductivity-type source region surrounding the second-conductivity-type body region; a second-conductivity-type base region surrounding the first-conductivity-type source region; a second-conductivity-type shield region surrounding the second-conductivity-type body region and under the first-conductivity-type source region and the second-conductivity-type base region; a junction field effect transistor region surrounding the second-conductivity-type base region and the second-conductivity-type shield region; a gate structure covering the junction field effect transistor region, the second-conductivity-type base region, and part of the first-conductivity-type source region; an insulating layer covering a surface of the device structure, the insulating layer having a source contact window, at least one edge line of the source contact window not exceeding an edge of the second-conductivity-type body region corresponding to the edge line; a source metal layer filling the source contact window; the source contact window has three edge lines not exceeding edges of the second-conductivity-type body region corresponding to the three edge lines.

2. The silicon carbide power semiconductor device structure of Claim 1, wherein: A distance between an outer edge of the second-conductivity-type body region and an inner edge of the gate structure is 0.5-0.6 microns.

3. The silicon carbide power semiconductor device structure of Claim 1, wherein: A distance between an outer edge of the second-conductivity-type body region and an outer edge of the first-conductivity-type source region is 1-1.1 microns.

4. The silicon carbide power semiconductor device structure of Claim 1, wherein: A distance between an outer edge of the contact window and an inner edge of the gate structure is 0.8-0.9 microns.

5. The silicon carbide power semiconductor device structure of Claim 1, wherein: A distance between an edge line of the contact window exceeding the second-conductivity-type body region and the second-conductivity-type body region is 1-1.1 microns.

6. The silicon carbide power semiconductor device structure of Claim 1, further comprising: A distance between an inner edge of the gate structure and an outer edge of the second-conductivity-type base region is 1-1.1 microns.

7. The silicon carbide power semiconductor device structure of Claim 1, further comprising: A distance between an outer edge of the first-conductivity-type source region and an outer edge of the second-conductivity-type base region is 0.5-0.6 microns.

8. The silicon carbide power semiconductor device structure of Claim 1, further comprising: A distance between an outer edge of the second-conductivity-type base region and an outer edge of the junction field effect transistor region is 0.5-0.6 microns.

9. The silicon carbide power semiconductor device structure of Claim 1, further comprising: A width of the second-conductivity-type body region is 1.8-2 microns.

10. The silicon carbide power semiconductor device structure of Claim 1, further comprising: A doping concentration of the junction field effect transistor region is greater than a doping concentration of the first-conductivity-type drift region.

11. The silicon carbide power semiconductor device structure of Claim 1, further comprising: a channel density of the silicon carbide power semiconductor device structure is greater than or equal to 0.48 μm -1 a junction field effect transistor region density of the silicon carbide power semiconductor device structure is greater than or equal to 0.29, and a specific on-resistance of the junction field effect transistor region is less than or equal to 3.6 mohm*cm 2 wherein the channel density is a ratio of a channel length to a total area of the silicon carbide power semiconductor device structure, and the junction field effect transistor region density is a ratio of an area of the junction field effect transistor region to the total area of the silicon carbide power semiconductor device structure.

Images