Delay circuits and delay structures

Abstract

The present application provides a delay circuit and a delay structure. The circuit includes: a first delay unit, which is used to delay the rising edge and / or falling edge of a pulse signal, whose input end receives the pulse signal, and whose output end outputs the first delayed signal; a second delay unit, which is used to delay the first delayed signal, whose input end is connected to the output end of the first delay unit, and whose output end outputs the second delayed signal; the delay time between the rising edge of the second delayed signal and the rising edge of the pulse signal is recorded as the rising edge delay time, and the delay time between the falling edge of the second delayed signal and the falling edge of the pulse signal is recorded as the falling edge delay time; the change value of the rising edge delay time and / or the falling edge delay time with the change of the first parameter is within a first range, and the first parameter includes at least one of the manufacturing process of the delay circuit, the power supply voltage wave and the operating temperature.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a delay circuit and a delay structure. Background Art

[0002] Currently, delay circuits are often used in semiconductor components. Delay circuits are circuits that can delay a pulse signal for a certain period of time. Figure 1 It is a schematic diagram of an input signal and an output signal after a delay circuit. After the input signal passes through the delay circuit, a delayed signal is output. Figure 1 As shown, the output signal is the signal after the input signal is delayed by time T. Figure 1 The illustrated case is that both the rising edge and the falling edge of the input signal are delayed by time T. There is also a case that only the rising edge of the input signal is delayed by time T or only the falling edge of the input signal is delayed by time T.

[0003] In the existing delay circuit, the delay T of the output signal passing through the delay circuit will change greatly (increase or decrease) with the change of parameters such as power supply voltage, operating temperature and manufacturing process, which will affect the performance of the delay circuit. How to ensure that the change of delay T is small when the above parameters change is an urgent problem to be solved. Summary of the invention

[0004] The present application provides a delay circuit and a delay structure to ensure that the delay of an output signal passing through the delay circuit changes less when at least one of the manufacturing process, power supply voltage wave and operating temperature of the delay circuit changes.

[0005] In a first aspect, the present application provides a delay circuit, comprising:

[0006] A first delay unit, used for delaying a rising edge and / or a falling edge of a pulse signal, wherein an input end thereof receives the pulse signal and an output end thereof outputs a first delayed signal;

[0007] A second delay unit, used for delaying the first delay signal, wherein an input end thereof is connected to an output end of the first delay unit, and an output end thereof outputs a second delay signal;

[0008] Among them, the delay time between the rising edge of the second delayed signal and the rising edge of the pulse signal is recorded as the rising edge delay time, and the delay time between the falling edge of the second delayed signal and the falling edge of the pulse signal is recorded as the falling edge delay time. The change value of the rising edge delay time and / or the falling edge delay time with the change of the first parameter is within a first range, and the first parameter includes at least one of the manufacturing process, power supply voltage wave and operating temperature of the delay circuit.

[0009] Optionally, a change value of the charging current and / or discharging current of the first delay unit as the first parameter changes is within the first range; or,

[0010] A change value of the charging current and / or discharging current of the second delay unit as the first parameter changes is within the first range; or,

[0011] A change value of the charging current and / or the discharging current of the first delay unit and the second delay unit as the first parameter changes is within the first range.

[0012] Optionally, the first delay unit includes an inverter and a delay array; or,

[0013] The second delay unit includes an inverter and a delay array; or,

[0014] The first delay unit includes an inverter and a delay array, and the second delay unit includes an inverter and a delay array;

[0015] The output terminal of the inverter is connected to the input and output terminals of the delay array, and the inverter has a power supply terminal and a ground terminal; the charging current is from the power supply terminal through the inverter to the delay array; and the discharging current is from the delay array through the inverter to the ground terminal.

[0016] Optionally, the delay array includes N parallel delay sub-arrays, the first ends of the N delay sub-arrays serve as input and output ends of the delay array, and the second ends of the N delay sub-arrays are electrically connected to the ground end or the power supply end, and N is an integer greater than or equal to 2.

[0017] Optionally, the delay subarray includes a switch and a capacitor, the first end of the switch serves as the first end or the second end of the delay subarray, the second end of the switch is connected to the first end of the capacitor, and the second end of the capacitor serves as the second end or the first end of the delay subarray.

[0018] Optionally, there is an equivalent capacitance value between the first end and the second end of the delay subarray, and the equivalent capacitance values ​​of N delay subarrays are the same; the delay array also receives a capacitance value adjustment code, and each bit of the capacitance value adjustment code is connected to the control end of the switch.

[0019] Optionally, there is an equivalent capacitance value between the first end and the second end of the delay subarray, and the equivalent capacitance values ​​of the N delay subarrays are arranged in an arithmetic progression or a geometric progression; the delay array also receives a capacitance value adjustment code, and each bit of the capacitance value adjustment code is connected to the control end of the switch.

[0020] Optionally, the inverter includes a first transistor, a second transistor and a third transistor, the control end of the first transistor is connected to the control end of the second transistor, the first end of the first transistor is connected to the power supply end, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the first end of the third transistor, the second end of the third transistor is connected to the ground end, and the control end of the third transistor is connected to a bias voltage; the control end of the first transistor serves as the input end of the inverter, and the second end of the first transistor serves as the output end of the inverter.

[0021] Optionally, the inverter further includes a fourth transistor, a first terminal of the fourth transistor is connected to the first terminal of the third transistor, a second terminal of the fourth transistor is connected to the ground terminal, and a control terminal of the fourth transistor is connected to the power supply terminal.

[0022] Optionally, the inverter includes a first transistor, a second transistor and a third transistor, the first end of the first transistor is connected to the power supply end, the second end of the first transistor is connected to the first end of the second transistor, the control end of the second transistor is connected to the control end of the third transistor, the second end of the second transistor is connected to the first end of the third transistor, the second end of the third transistor is connected to the ground end, and the control end of the first transistor is connected to a bias voltage; the control end of the second transistor serves as the input end of the inverter, and the second end of the second transistor serves as the output end of the inverter.

[0023] Optionally, the inverter further includes a fourth transistor, a first terminal of the fourth transistor is connected to the power supply terminal, a second terminal of the fourth transistor is connected to the second terminal of the first transistor, and a control terminal of the fourth transistor is connected to the ground terminal.

[0024] Optionally, also include:

[0025] A voltage bias control unit, wherein the voltage bias control unit outputs the bias voltage and controls the charging current and / or the discharging current flowing through the inverter to change with the first parameter within the first range through the bias voltage.

[0026] Optionally, the voltage bias control unit includes a constant current source, a fifth transistor and a voltage follower;

[0027] The constant current source provides a supply current, and a change value of the supply current as the first parameter changes is within the first range;

[0028] The constant current source is connected to the first terminal and the control terminal of the fifth transistor, the second terminal of the fifth transistor is connected to the power terminal or the ground terminal, and the control terminal of the fifth transistor provides a reference voltage;

[0029] The control end of the fifth transistor is also connected to the input end of the voltage follower, and the output end of the voltage follower serves as the output end of the voltage bias control unit.

[0030] Optionally, also include:

[0031] A feedback loop, a first end of which is connected to the output end of the second delay unit and a second end of which is connected to the input end of the second delay unit, is used to reduce the time taken by the first delay signal from a level flip point to a low level or from a level flip point to a high level.

[0032] Optionally, the feedback loop includes a seventh transistor and an eighth transistor, the control end of the eighth transistor serves as the first end of the feedback loop, the first end of the eighth transistor is connected to the second end of the seventh transistor, the second end of the eighth transistor is connected to the ground end, the first end of the seventh transistor serves as the second end of the feedback loop, and the control end of the seventh transistor is connected to the input end of the first delay unit.

[0033] Optionally, the feedback loop includes a seventh transistor and an eighth transistor, the control end of the seventh transistor serves as the first end of the feedback loop, the second end of the seventh transistor is connected to the first end of the eighth transistor, the first end of the seventh transistor is connected to the power supply end, the second end of the eighth transistor serves as the second end of the feedback loop, and the control end of the eighth transistor is connected to the input end of the first delay unit.

[0034] Optionally, also include:

[0035] A buffer, whose input end is connected to the output end of the second delay unit and whose output end outputs the third delayed signal, is used for shaping the second delayed signal to obtain the third delayed signal.

[0036] In a second aspect, the present application provides a delay structure, including:

[0037] A plurality of delay circuits as described in any one of claims 1 to 17 are connected in series, the input end of the first delay circuit receives the pulse signal, the output end of the M-1th delay circuit is connected to the input end of the Mth delay circuit, and the output end of the Mth delay circuit outputs a delay signal with a preset delay time, wherein M is an integer greater than or equal to 2.

[0038] Optionally, the delay time between the rising edge of the preset delay signal and the rising edge of the pulse signal is recorded as the first preset delay time, and the delay time between the falling edge of the preset delay signal and the falling edge of the pulse signal is recorded as the second preset delay time, and the change value of the first preset delay time and / or the second preset delay time as the first parameter of the delay structure changes is within the first range.

[0039] Optionally, also include:

[0040] A control encoding module is connected to the delay circuit and is used to control the first preset delay time and / or the second preset delay time.

[0041] The delay circuit and delay structure provided by the present application include a first delay unit and a second delay unit. The first delay unit delays the rising edge and / or falling edge of a pulse signal and outputs a first delay signal. The second delay unit delays the first delay signal and outputs a second delay signal. The rising edge delay time and / or falling edge delay time of the second delay signal changes with at least one of the power supply voltage, the operating temperature and the manufacturing process within a first range. The first range is a smaller range, so that the delay of the output signal passing through the delay circuit can change less when at least one of the power supply voltage, the operating temperature and the manufacturing process changes, thereby improving the performance of the delay circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0043] Figure 1 A schematic diagram of an input signal and an output signal after a delay circuit;

[0044] Figure 2 A schematic diagram of an input signal and an output signal after a delay circuit;

[0045] Figure 3 A schematic diagram of an input signal and an output signal after a delay circuit;

[0046] Figure 4 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0047] Figure 5 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0048] Figure 6 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0049] Figure 7 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0050] Figure 8 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0051] Fig. 9 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0052] Fig.10 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0053] Fig.11 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0054] Fig.12 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0055] Fig.13 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0056] Fig.14 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0057] Fig.15 A schematic diagram of the structure of a voltage bias control unit in a delay circuit provided in an embodiment of the present application;

[0058] Fig.16 A schematic diagram of an input pulse signal and a second delayed signal output after passing through a delay circuit;

[0059] Fig.17 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0060] Fig.18 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0061] Fig.19 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0062] Fig. 20 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0063] Fig.21 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0064] Fig. 22 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0065] Fig.23 A schematic diagram of a delay structure provided in an embodiment of the present application;

[0066] Fig.24 A schematic diagram of a delay structure provided in an embodiment of the present application;

[0067] Fig.25 A schematic diagram of a delay structure provided in an embodiment of the present application;

[0068] Fig.26 A structural schematic diagram of a delay structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0070] First, the rising edge delay time and the falling edge delay time are explained for easier understanding.

[0071] 1. Rising edge delay time, Figure 1 is a schematic diagram of an input signal and an output signal after a delay circuit, such as Figure 1 As shown, the delay time T between the rising edge of the output signal and the rising edge of the input signal is the rising edge delay time.

[0072] 2. Falling edge delay time, such as Figure 1 As shown, the delay time T between the falling edge of the output signal and the falling edge of the input signal is the falling edge delay time.

[0073] The delay circuit provided in the present application can delay both the rising edge and the falling edge of the input signal by a time T, and the width of the pulse signal remains unchanged, such as Figure 1 As shown in , a rising edge delay time T of the input signal can be achieved, and a falling edge delay time T of the input signal can be achieved. Figure 2 is a schematic diagram of an input signal and an output signal after a delay circuit, such as Figure 2 As shown, the rising edge of the input signal is delayed by time T to obtain the output signal, and the width of the pulse signal is shortened by time T. Figure 3is a schematic diagram of an input signal and an output signal after a delay circuit, such as Figure 3 As shown, the falling edge of the input signal is delayed by time T to obtain the output signal, and the width of the pulse signal is extended by time T. It should be noted that Figure 1-Figure 3 Only one cycle of the pulse signal is shown.

[0074] In the existing delay circuit, the delay T of the output signal passing through the delay circuit will change greatly with the change of parameters such as power supply voltage, operating temperature and manufacturing process, which will affect the performance of the delay circuit. To solve this problem, the present application provides a delay circuit, including two delay units, wherein the first delay unit is used to delay the rising edge and / or falling edge of a pulse signal and output a first delay signal, and the second delay unit is used to delay the first delay signal and output a second delay signal, and the rising edge delay time and / or falling edge delay time of the second delay signal change with the change value of at least one of the power supply voltage, operating temperature and manufacturing process within a first range, and the first range is a smaller range, for example, a range close to 0, such as the first range is 1% or 3% or 5%, so that the delay of the output signal passing through the delay circuit can change less when at least one of the power supply voltage, operating temperature and manufacturing process changes, thereby improving the performance of the delay circuit. The specific structure of the delay circuit provided by the present application is described in detail below through specific embodiments.

[0075] Figure 4 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the delay circuit of this embodiment may include: a first delay unit 1 and a second delay unit 2, wherein the first delay unit 1 is used to delay the rising edge and / or falling edge of a pulse signal, the input end of the first delay unit 1 receives the pulse signal, the output end of the first delay unit 1 outputs the first delay signal, the second delay unit 2 is used to delay the first delay signal, the input end of the second delay unit 2 is connected to the output end of the first delay unit, and the output end of the second delay unit 2 outputs the second delay signal. The delay time between the rising edge of the second delay signal and the rising edge of the pulse signal is the rising edge delay time, and the delay time between the falling edge of the second delay signal and the falling edge of the pulse signal is the falling edge delay time. The change value of the rising edge delay time and / or the falling edge delay time with the change of the first parameter is within a first range, and the first range is a smaller range, for example, a range close to 0, such as the first range is 1% or 3% or 5%, wherein the first parameter includes at least one of the manufacturing process, power supply voltage and operating temperature of the delay circuit. That is, the pulse signal is Figure 1After the delay circuit shown is delayed, if the delay circuit delays the rising edge of the pulse signal, the change value of the rising edge delay time of the output signal with the change of the first parameter is within the first range and remains basically constant. If the delay circuit delays the falling edge of the pulse signal, the change value of the falling edge delay time of the output signal with the change of the first parameter is within the first range and remains basically constant. If the delay circuit delays the rising and falling edges of the pulse signal, the change value of the rising edge delay time and the falling edge delay time of the output signal with the change of the first parameter is within the first range and remains basically constant.

[0076] In the embodiment of the present application, the first delay unit may have different specific circuit structures, and the second delay unit may have different specific circuit structures. There are three optional ways to implement the functions of the first delay unit and the second delay unit:

[0077] Mode 1: A change value of the charging current and / or discharging current of the first delay unit as a function of a first parameter is within a first range.

[0078] Specifically, since the change value of the charging current and / or discharging current of the first delay unit as the first parameter changes is within a first range, the change value of the rising edge delay time and / or falling edge delay time of the first delay signal output after being delayed by the first delay unit as the first parameter changes is within a first range, and the first delay signal is output as a second delay signal after being delayed by the second delay unit, which can ensure that the change value of the rising edge delay time and / or falling edge delay time of the second delay signal as the first parameter changes is within a first range.

[0079] Mode 2: A change value of the charging current and / or discharging current of the second delay unit as the first parameter changes is within a first range.

[0080] Specifically, the pulse signal is delayed by the first delay unit and then outputs a first delayed signal. Since the change value of the charging current and / or discharging current of the second delay unit as the first parameter changes is within a first range, the first delayed signal is delayed by the second delay unit and then outputs a second delayed signal, which can ensure that the change value of the rising edge delay time and / or falling edge delay time of the second delayed signal as the first parameter changes is within a first range.

[0081] Mode three: a change value of the charging current and / or discharging current of the first delay unit and the second delay unit as the first parameter changes is within a first range.

[0082] Specifically, since the charging current and / or discharging current of the first delay unit and the second delay unit both change with the first parameter within a first range, the pulse signal is delayed by the first delay unit to output a first delay signal, and the first delay signal is delayed by the second delay unit to output a second delay signal, it can be ensured that the rising edge delay time and / or falling edge delay time of the second delay signal change with the first parameter within a first range.

[0083] The delay circuit provided in this embodiment includes a first delay unit and a second delay unit. The first delay unit delays the rising edge and / or falling edge of a pulse signal and outputs a first delay signal. The second delay unit delays the first delay signal and outputs a second delay signal. The rising edge delay time and / or falling edge delay time of the second delay signal changes with at least one of the power supply voltage, the operating temperature and the manufacturing process within a first range. The first range is a smaller range, so that the delay of the output signal passing through the delay circuit can change less when at least one of the power supply voltage, the operating temperature and the manufacturing process changes, thereby improving the performance of the delay circuit.

[0084] The structure of the delay circuit of the present application is described below in conjunction with specific embodiments. The specific structure of the delay circuit of the present application is not limited to any of the following structures.

[0085] Optionally, the delay circuit provided in this application has the following three circuit structures:

[0086] The first type: the first delay unit includes an inverter and a delay array. Figure 5 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the first delay unit includes an inverter 11 and a delay array 12 , and the output terminal of the inverter 11 is connected to the input and output terminals of the delay array 12 .

[0087] The second type: the second delay unit includes an inverter and a delay array. Figure 6 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the second delay unit includes an inverter 21 and a delay array 22 , and the output terminal of the inverter 21 is connected to the input and output terminals of the delay array 22 .

[0088] The third type: the first delay unit includes an inverter and a delay array, and the second delay unit includes an inverter and a delay array. Figure 7 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 7As shown, the first delay unit includes an inverter 11 and a delay array 12, and the second delay unit includes an inverter 21 and a delay array 22. The output of the inverter 11 is connected to the input and output of the delay array 12, and the output of the inverter 21 is connected to the input and output of the delay array 22.

[0089] Among these three circuit structures, the output terminal of the inverter is connected to the input and output terminals of the delay array, the inverter has a power supply terminal and a ground terminal, the charging current is from the power supply terminal through the inverter to the delay array, and the discharging current is from the delay array through the inverter to the ground terminal.

[0090] Further, the delay array may include N parallel delay sub-arrays, the first ends of the N delay sub-arrays serve as input and output ends of the delay array, the second ends of the N delay sub-arrays are electrically connected to a ground end or a power supply end, and N is an integer greater than or equal to 2.

[0091] Taking the first circuit structure as an example, Figure 8 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the first delay unit 1 includes an inverter 11 and a delay array 12, and the second delay unit 2 includes an inverter 21, wherein the output terminal of the inverter 11 is connected to the input and output terminals of the delay array 12, and the inverter 11 has a power supply terminal V cc and ground terminal V ss ; The charging current is from the power supply terminal V dd The discharge current is from the delay array 12 through the inverter 11 to the ground terminal V ss .

[0092] Among them, as an optional method, such as Figure 8 As shown in FIG. 1 , the delay array 12 may include N parallel delay sub-arrays 121, the first ends of the N delay sub-arrays 121 serving as input and output ends of the delay array, and the second ends of the N delay sub-arrays 121 being electrically connected to the ground end V ss , N is an integer greater than or equal to 2.

[0093] Optional, such as Figure 8As shown in , the delay subarray 121 may include a switch and a capacitor, the first end of the switch serves as the first end or the second end of the delay subarray 121, the second end of the switch is connected to the first end of the capacitor, and the second end of the capacitor serves as the second end or the first end of the delay subarray 121. That is, in an optional manner, the delay subarray 121 may include a switch and a capacitor, the first end of the switch serves as the first end of the delay subarray 121, the second end of the switch is connected to the first end of the capacitor, and the second end of the capacitor serves as the second end of the delay subarray 121. Alternatively, the first end of the switch serves as the second end of the delay subarray 121, the second end of the switch is connected to the first end of the capacitor, and the second end of the capacitor serves as the first end of the delay subarray 121.

[0094] Further, as an implementable manner, there is an equivalent capacitance value between the first end and the second end of the delay subarray 121, and the equivalent capacitance values ​​of the N delay subarrays 121 are the same; the delay array 12 also receives a capacitance value adjustment code, and each bit of the capacitance value adjustment code is connected to the control end of the switch. For example, Figure 8 As shown in , the number N of delay sub-arrays 121 is 3. For example, the capacitance value adjustment code received by the delay array 12 is "101", "0" indicates that the switch is closed, and "1" indicates that the switch is open. Figure 8 The control end control switches of the first delay subarray 121 and the third delay subarray 121 shown in the figure are turned on, and the control end control switch of the second delay subarray 121 is turned off. By adjusting the control of the capacitance value coding, the number of delay subarrays 121 turned on can be adjusted, so that different delay times can be achieved.

[0095] As another practicable manner, there is an equivalent capacitance value between the first end and the second end of the delay subarray 121, and the equivalent capacitance values ​​of the N delay subarrays are arranged in an arithmetic progression or a geometric progression. The delay array 12 also receives a capacitance value adjustment code, and each bit of the capacitance value adjustment code is connected to the control end of the switch. For example, Figure 8 As shown in , the number N of delay sub-arrays 121 is 5. For example, the capacitance value adjustment code received by the delay array 12 is "10101", "0" indicates that the switch is closed, and "1" indicates that the switch is open. Figure 8The control end control switches of the first delay subarray 121, the third delay subarray 121 and the fifth delay subarray 121 shown in the figure are turned on, and the control end control switches of the second delay subarray 121 and the fourth delay subarray 121 are turned off. By controlling the capacitance value adjustment coding, the number of delay subarrays 121 connected can be adjusted, so that different delay times can be achieved. The difference between this embodiment and the previous embodiment is that the equivalent capacitance values ​​of the N delay subarrays 121 in the previous embodiment are the same, and the equivalent capacitance values ​​of the N delay subarrays in this embodiment are different, and are arranged in an arithmetic progression or a geometric progression. When adjusting different delay times, it can be more flexible.

[0096] Figure 8 The delay circuit shown can delay the rising edge of the pulse signal.

[0097] Taking the first circuit structure as an example, Fig. 9 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig. 9 The delay circuit shown can delay the falling edge of the pulse signal. Fig. 9 As shown, Fig. 9 The delay circuit shown is Figure 8 The difference between the delay circuits shown is, Figure 8 The second terminals of the N delay sub-arrays 121 are electrically connected to the ground terminal V ss ,and Fig. 9 The second terminals of the N delay sub-arrays 121 are electrically connected to the power supply terminal V cc The other structures and connection methods are the same and will not be described here.

[0098] Combine the following Fig.10 and Fig.11 illustrate Figure 8 The specific structure of the inverter shown in Figure 8 A specific structure of the delay subarray 121 is shown in FIG.

[0099] Fig.10 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.10 is a specific circuit structure corresponding to 8, such as Fig.10As shown, the inverter 11 includes a first transistor, a second transistor and a third transistor. The first transistor may be a PMOS transistor TP1, the second transistor may be an NMOS transistor TN1, and the third transistor may be an NMOS transistor TN2. The control end of TP1 is connected to the control end of the second transistor TN1, the first end of TP1 is connected to the power supply end, the second end of TP1 is connected to the first end of TN1, the second end of TN1 is connected to the first end of TN2, the second end of TN2 is connected to the ground end, and the control end of TN2 is connected to the bias voltage; the control end of TP1 serves as the input end of the inverter 11, and the second end of TP1 serves as the output end of the inverter 11. Fig.10 As shown, the delay sub-array 121 includes a switch and a capacitor. The switch may be a PMOS transistor TP2, and the capacitor is formed by grounding the first end and the second end of the NMOS transistor TN3.

[0100] Fig.11 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.10 On the basis of the delay circuit shown in FIG. 1 , the inverter 11 further includes a fourth transistor, which may be an NMOS transistor TN4, wherein a first terminal of TN4 is connected to a first terminal of TN2, a second terminal of TN4 is connected to a ground terminal, and a control terminal of TN4 is connected to a power terminal V cc The current flowing through TN2 is a basically constant current, which does not change with the manufacturing process, power supply voltage and operating temperature. The current flowing through TN4 changes with the power supply terminal V cc (power supply voltage) increases, and increases with the power supply terminal V cc (power supply voltage) decreases, so that the current flowing through TN1 increases with the increase of power supply voltage and decreases with the decrease of power supply voltage, so that the discharge current flowing through TN1 of the delay array 12 follows the change of power supply voltage, and then the delay time caused by the inverter 11 and the delay array 12 remains basically unchanged or within the first range. For example, when the operating temperature increases, the current flowing through TN2 and TN4 remains basically unchanged or within the first range, so that the discharge current flowing through TN1 of the delay array 12 remains basically unchanged or within the first range, and then the delay time caused by the inverter 11 and the delay array 12 remains basically unchanged or within the first range. For another example, when the power supply voltage increases, the current flowing through TN2 remains basically unchanged or within the first range, and the current flowing through TN4 increases, so that the discharge current flowing through TN1 of the delay array 12 increases, but because the power supply voltage increases, the delay array 12 stores more charge (or the initial value of the discharge voltage is higher), and then the delay time caused by the inverter 11 and the delay array 12 remains basically unchanged or within the first range.

[0101] Combine the following Fig.12 and Fig.13 illustrate Fig. 9 The specific structure of the inverter shown in Fig. 9 A specific structure of the delay subarray 121 is shown in FIG.

[0102] Fig.12 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.12 For a Fig. 9 The corresponding specific circuit structure, such as Fig.12 As shown, the inverter includes a first transistor, a second transistor and a third transistor. The first transistor may be a PMOS transistor TP3, the second transistor may be a PMOS transistor TP4, the third transistor may be an NMOS transistor TN5, and the first terminal of TP3 is connected to the power supply terminal V cc The second end of TP3 is connected to the first end of TP4, the control end of TP4 is connected to the control end of TN5, the second end of TP4 is connected to the first end of TN5, and the second end of TN5 is connected to the ground end V ss , the control terminal of TP3 is connected to the bias voltage; the control terminal of TP4 is used as the input terminal of the inverter, and the second terminal of TP4 is used as the output terminal of the inverter. Fig.12 As shown, the delay sub-array 121 includes a switch and a capacitor. The switch may be an NMOS transistor TN6. The capacitor is connected to the power supply terminal V by connecting the first and second terminals of the PMOS transistor TP5. cc constitute.

[0103] Fig.13 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.12 On the basis of the delay circuit shown in the figure, further, the inverter 11 further includes a fourth transistor, which can be a PMOS transistor TP6, and the first terminal of TP6 is connected to the power supply terminal V cc The second end of TP6 is connected to the second end of TP3, and the control end of TP6 is connected to the ground end Vss.

[0104] exist Fig.13 In the example, the current flowing through TP3 is a substantially constant current, which does not change with the manufacturing process, power supply voltage and operating temperature, while the current flowing through TP6 changes with the power supply terminal V cc (power supply voltage) increases, and increases with the power supply terminal V cc(power supply voltage) decreases, so that the current flowing through TP4 increases with the increase of the power supply voltage and decreases with the decrease of the power supply voltage, so that the charging current flowing through TP4 for the delay array 12 follows the change of the power supply voltage, and then the delay time caused by the inverter 11 and the delay array 12 remains basically unchanged or remains within the first range. For example, when the operating temperature increases, the current flowing through TP3 and TP6 remains basically unchanged or remains within the first range, so that the charging current flowing through TP4 for the delay array 12 remains basically unchanged or remains within the first range, and then the delay time caused by the inverter 11 and the delay array 12 remains basically unchanged or remains within the first range. For another example, when the power supply voltage increases, the current flowing through TP3 remains basically unchanged or within the first range, and the current flowing through TP6 increases, so that the charging current flowing through TP4 for the delay array 12 increases, but because the power supply voltage increases, the delay array 12 needs to store more charge (or the final value of the charging voltage is basically equal to V cc , which becomes larger), thereby making the delay time caused by the inverter 11 and the delay array 12 substantially remain unchanged or remain within the first range.

[0105] Further, Figure 10-13 The bias voltage in can be output by the voltage bias control unit. Figure 10-13 Based on any delay circuit, the delay circuit may further include a voltage bias control unit to Fig.10 Based on the delay circuit shown as an example, Fig.14 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.10 On the basis of the delay circuit shown, a voltage bias control unit 13 may also be included. The voltage bias control unit 13 outputs a bias voltage and controls the charging current and / or discharging current flowing through the inverter 11 to change with the first parameter within a first range through the bias voltage.

[0106] Combine the following Fig.15 An optional specific structure of a voltage bias unit is described. Fig.15 A schematic diagram of the structure of a voltage bias control unit in a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.15 As shown, the voltage bias control unit 13 includes a constant current source 131 , a fifth transistor 132 and a voltage follower 133 .

[0107] The constant current source 131 provides a power supply current, and a change value of the power supply current as the first parameter changes is within a first range.

[0108] The constant current source 131 is connected to the first terminal and the control terminal of the fifth transistor 132. The second terminal of the fifth transistor 132 is connected to the power supply terminal or the ground terminal. The control terminal of the fifth transistor 132 provides a reference voltage. Optionally, the fifth transistor can be an NMOS tube.

[0109] The control end of the fifth transistor 132 is also connected to the input end of the voltage follower 133 , and the output end of the voltage follower 133 serves as the output end of the voltage bias control unit 13 .

[0110] Fig.16 is a schematic diagram of an input pulse signal and a second delayed signal output after passing through a delay circuit, such as Fig.16 As shown, after the input pulse signal is delayed by the delay circuit, the delay time between the rising edge of the first delayed signal and the rising edge of the input pulse signal is the rising edge delay time. After the rising edge delay time is delayed, it is necessary to make the first delayed signal quickly change from the level flip point to the low level, and reduce the time for the first delayed signal to change from the level flip point to the low level. There are two types of the above-mentioned level flip points, one is the critical state that the PMOS of the inverter is just turned on or the NMOS of the inverter is just turned off (for the input signal of the inverter to change from a high level to a low level), and the other is the critical state that the NMOS of the inverter is just turned on or the PMOS of the inverter is just turned off (for the input signal of the inverter to change from a low level to a high level). In the embodiment of the present application, on the basis of the above three circuit structures, further, a feedback loop can be included to Figure 5 Based on the delay circuit shown as an example, Fig.17 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 5 Based on the delay circuit shown, the delay circuit of this embodiment may further include a feedback loop 3, wherein a first end of the feedback loop 3 is connected to an output end of the second delay unit, and a second end of the feedback loop is connected to an input end of the second delay unit, for reducing the time taken by the first delay signal from a level flipping point to a low level or from a level flipping point to a high level.

[0111] Combine the following Fig.18 and Fig.19 Describe an alternative specific structure of the feedback loop, Fig.18 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.18 The delay circuit shown is Fig.10 The structural diagram of the feedback loop added to the delay circuit shown in FIG. Fig.18 As shown, the feedback loop 3 includes a seventh transistor and an eighth transistor. The seventh transistor may be an NMOS transistor TN7, and the eighth transistor may be an NMOS transistor TN8. The control end of TN8 serves as the first end of the feedback loop. The first end of TN8 is connected to the second end of TN7, and the second end of TN8 is connected to the ground end Vss , the first end of TN7 serves as the second end of the feedback loop, and the control end of TN7 is connected to the input end of the first delay unit.

[0112] Fig.19 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.19 The delay circuit shown is Fig.11 The structural diagram of the feedback loop added to the delay circuit shown in FIG. Fig.19 As shown, the feedback loop 3 includes a seventh transistor and an eighth transistor. The seventh transistor may be an NMOS transistor TN7, and the eighth transistor may be an NMOS transistor TN8. The control end of TN8 serves as the first end of the feedback loop. The first end of TN8 is connected to the second end of TN7, and the second end of TN8 is connected to the ground end V ss , the first end of TN7 serves as the second end of the feedback loop, and the control end of TN7 is connected to the input end of the first delay unit.

[0113] Combine the following Fig. 20 and Fig.21 Describing another alternative specific structure of the feedback loop, Fig. 20 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig. 20 The delay circuit shown is Fig.12 The structural diagram of the feedback loop added to the delay circuit shown in FIG. Fig. 20 As shown, the feedback loop includes a seventh transistor and an eighth transistor, the seventh transistor can be a PMOS transistor TP7, the eighth transistor can be a PMOS transistor TP8, the control end of TP7 serves as the first end of the feedback loop, the second end of TP7 is connected to the first end of TP8, the first end of TP7 is connected to the power supply end, the second end of TP8 serves as the second end of the feedback loop, and the control end of TP8 is connected to the input end of the first delay unit.

[0114] Fig.21 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.21 The delay circuit shown is Fig.13 The structural diagram of the feedback loop added to the delay circuit shown in FIG. Fig.21 As shown, the feedback loop includes a seventh transistor and an eighth transistor, the seventh transistor can be a PMOS transistor TP7, the eighth transistor can be a PMOS transistor TP8, the control end of TP7 serves as the first end of the feedback loop, the second end of TP7 is connected to the first end of TP, the first end of TP7 is connected to the power supply end, the second end of TP8 serves as the second end of the feedback loop, and the control end of TP8 is connected to the input end of the first delay unit.

[0115] In order to shape the second delayed signal, in the embodiment of the present application, based on the above three circuit structures, a buffer may be further included to Figure 5 Based on the delay circuit shown as an example, Fig. 22 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Figure 5 Based on the delay circuit shown, the delay circuit of this embodiment can also include a buffer 4, the input end of the buffer 4 is connected to the output end of the second delay unit 2, the output end of the buffer 4 outputs a third delayed signal, and the buffer 4 is used to shape the second delayed signal to obtain a third delayed signal.

[0116] Optionally, the buffer 4 may be composed of an even number of inverters.

[0117] The present application also provides a delay structure, including multiple Figure 4-Figure 14 and Figure 17-Figure 22 Any of the delay circuits shown are connected in series, Fig.23 A schematic diagram of a delay structure provided in an embodiment of the present application is shown in FIG. Fig.23 As shown, the input end of the 1st delay circuit receives a pulse signal, the output end of the M-1th delay circuit is connected to the input end of the Mth delay circuit, and the output end of the Mth delay circuit outputs a delay signal with a preset delay time, where M is an integer greater than or equal to 2.

[0118] In this embodiment, the delay time between the rising edge of the preset delay signal and the rising edge of the pulse signal is recorded as the first preset delay time, and the delay time between the falling edge of the preset delay signal and the falling edge of the pulse signal is recorded as the second preset delay time. The change value of the first preset delay time and / or the second preset delay time as the first parameter of the delay structure changes is within the first range.

[0119] Fig.24 A schematic diagram of a delay structure provided in an embodiment of the present application is shown in FIG. Fig.24 As shown, in Fig.23 On the basis of the delay structure shown, further, a control coding module may be included, which is connected to each delay circuit and is used to control the size of the first preset delay time and / or the second preset delay time.

[0120] The structure of the delay structure is explained below by taking two specific delay structures in which two delay circuits are connected in series as examples.

[0121] Fig.25 A schematic diagram of a delay structure provided in an embodiment of the present application is shown in FIG. Fig.25As shown, the delay structure of this embodiment includes a first delay circuit 30 and a second delay circuit 40 connected in series, an inverter 50 is connected in series between the first delay circuit 30 and the second delay circuit 40, and an inverter 60 is also connected in series after the second delay circuit 40. After the pulse signal passes through the delay structure, a delayed signal is output. The first delay circuit 30 and the second delay circuit 40 have the same structure, both of which are rising edge delay circuits. The delay structure can delay the rising edge of the pulse signal.

[0122] It should be noted that the first delay circuit 30 and the second delay circuit 40 can also be both falling edge delay circuits, or can also be both Fig.11 The circuit structure shown.

[0123] Fig.26 A schematic diagram of a delay structure provided in an embodiment of the present application is shown in FIG. Fig.26 As shown, the delay structure of this embodiment includes a first delay circuit 70 and a second delay circuit 80 connected in series, an inverter 90 is connected in series between the first delay circuit 70 and the second delay circuit 80, and an inverter 100 is further connected in series after the second delay circuit 80. After the pulse signal passes through the delay structure, a delayed signal is output. The structures of the first delay circuit 70 and the second delay circuit 80 are different. The first delay circuit 70 is a rising edge delay circuit, and the second delay circuit 80 is a falling edge delay circuit. The delay structure can delay the rising edge and the falling edge of the pulse signal.

[0124] It should be noted that the first delay circuit 70 can also be Fig.11 The second delay circuit 80 can also be Fig.13 The circuit structure shown.

[0125] Fig.25 and Fig.26 The delay structure shown is only an example and does not constitute a limitation on the delay structure of the present application. The number of delay circuits connected in series and the type of delay circuit (specifically rising edge delay circuit and falling edge delay circuit) can also be selected according to the actual required delay time.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A delay circuit, characterized in that: include: A first delay unit, used for delaying a rising edge and / or a falling edge of a pulse signal, wherein an input end thereof receives the pulse signal and an output end thereof outputs a first delayed signal; A second delay unit, used for delaying the first delay signal, wherein an input end thereof is connected to an output end of the first delay unit, and an output end thereof outputs a second delay signal; The delay time between the rising edge of the second delayed signal and the rising edge of the pulse signal is recorded as the rising edge delay time, and the delay time between the falling edge of the second delayed signal and the falling edge of the pulse signal is recorded as the falling edge delay time. The change value of the rising edge delay time and / or the falling edge delay time with the change of the first parameter is within a first range, and the first parameter includes at least one of the manufacturing process, the power supply voltage wave and the operating temperature of the delay circuit; wherein the change value of the charging current and / or discharging current of the first delay unit as the first parameter changes is within the first range; or, the change value of the charging current and / or discharging current of the second delay unit as the first parameter changes is within the first range; or, the change value of the charging current and / or discharging current of the first delay unit and the second delay unit as the first parameter changes is within the first range; Wherein, the first delay unit includes a first inverter and a first delay array; or, the second delay unit includes a second inverter and a second delay array; or, the first delay unit includes a first inverter and a first delay array, and the second delay unit includes a second inverter and a second delay array; The input end of the first inverter serves as the input end of the first delay unit, the output end of the first inverter is connected to the input end of the first delay array, the output end of the first delay array serves as the output end of the first delay unit, the input end of the second inverter serves as the input end of the second delay unit, the output end of the second inverter is connected to the output end of the second delay array, and the output end of the second delay array serves as the output end of the second delay unit; The first inverter and the second inverter have a power supply terminal and a ground terminal; the second delay array receives a charging current from the corresponding power supply terminal through the second inverter, and the first delay array receives a charging current from the corresponding power supply terminal through the first inverter; the discharge current is from the first delay array through the first inverter to the ground terminal, and from the second delay array through the second inverter to the ground terminal; a feedback loop, a first end of which is connected to the output end of the second delay unit, and a second end of which is connected to the input end of the second delay unit, for reducing the time of the first delay signal from the level flip point to the low level or from the level flip point to the high level; wherein the feedback loop comprises a seventh transistor and an eighth transistor, the control end of the eighth transistor serves as the first end of the feedback loop, the first end of the eighth transistor is connected to the second end of the seventh transistor, the second end of the eighth transistor is connected to the ground end, the first end of the seventh transistor serves as the second end of the feedback loop, and the control end of the seventh transistor is connected to the input end of the first delay unit; or, The feedback loop includes a seventh transistor and an eighth transistor, the control end of the seventh transistor serves as the first end of the feedback loop, the second end of the seventh transistor is connected to the first end of the eighth transistor, the first end of the seventh transistor is connected to the power supply end, the second end of the eighth transistor serves as the second end of the feedback loop, and the control end of the eighth transistor is connected to the input end of the first delay unit.

2. The delay circuit according to claim 1, characterized in that: The first delay array and the second delay array include N parallel delay sub-arrays, the first ends of the N delay sub-arrays serve as output ends of the first delay array or the second delay array, and the second ends of the N delay sub-arrays are electrically connected to the ground end or the power supply end, and N is an integer greater than or equal to 2.

3. The delay circuit according to claim 2, characterized in that: The delay subarray includes a switch and a capacitor, the first end of the switch serves as the first end or the second end of the delay subarray, the second end of the switch is connected to the first end of the capacitor, and the second end of the capacitor serves as the second end or the first end of the delay subarray.

4. The delay circuit according to claim 3, characterized in that: There is an equivalent capacitance value between the first end and the second end of the delay subarray, and the equivalent capacitance value of the N delay subarrays is the same; the first delay array and the second delay array also receive a capacitance value adjustment code, and each bit of the capacitance value adjustment code is connected to the control end of the switch.

5. The delay circuit according to claim 3, characterized in that: An equivalent capacitance value is provided between the first end and the second end of the delay subarray, and the equivalent capacitance values ​​of the N delay subarrays are arranged in an arithmetic progression or a geometric progression; the first delay array and the second delay array also receive a capacitance value adjustment code, and each bit of the capacitance value adjustment code is connected to the control end of the switch.

6. The delay circuit according to claim 1, characterized in that: The first inverter and the second inverter include a first transistor, a second transistor and a third transistor, the control end of the first transistor is connected to the control end of the second transistor, the first end of the first transistor is connected to the power supply end, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the first end of the third transistor, the second end of the third transistor is connected to the ground end, and the control end of the third transistor is connected to a bias voltage; the control end of the first transistor serves as an input end of the first inverter or the second inverter, and the second end of the first transistor serves as an output end of the first inverter or the second inverter.

7. The delay circuit according to claim 6, characterized in that: The first inverter and the second inverter further include a fourth transistor, a first terminal of the fourth transistor is connected to the first terminal of the third transistor, a second terminal of the fourth transistor is connected to the ground terminal, and a control terminal of the fourth transistor is connected to the power terminal.

8. The delay circuit according to claim 1, characterized in that: The first inverter and the second inverter include a first transistor, a second transistor and a third transistor, the first end of the first transistor is connected to the power supply end, the second end of the first transistor is connected to the first end of the second transistor, the control end of the second transistor is connected to the control end of the third transistor, the second end of the second transistor is connected to the first end of the third transistor, the second end of the third transistor is connected to the ground end, and the control end of the first transistor is connected to the bias voltage; the control end of the second transistor serves as the input end of the first inverter or the second inverter, and the second end of the second transistor serves as the output end of the first inverter or the second inverter.

9. The delay circuit according to claim 8, characterized in that: The first inverter and the second inverter further include a fourth transistor, a first terminal of the fourth transistor is connected to the power terminal, a second terminal of the fourth transistor is connected to the second terminal of the first transistor, and a control terminal of the fourth transistor is connected to the ground terminal.

10. The delay circuit according to any one of claims 6 to 9, characterized in that: Also includes: A voltage bias control unit, wherein the voltage bias control unit outputs the bias voltage and controls the charging current and / or the discharging current flowing through the inverter to change with the first parameter within the first range through the bias voltage.

11. The delay circuit according to claim 10, characterized in that: The voltage bias control unit includes a constant current source, a fifth transistor and a voltage follower; The constant current source provides a supply current, and a change value of the supply current as the first parameter changes is within the first range; The constant current source is connected to the first terminal and the control terminal of the fifth transistor, the second terminal of the fifth transistor is connected to the power terminal or the ground terminal, and the control terminal of the fifth transistor provides a reference voltage; The control end of the fifth transistor is also connected to the input end of the voltage follower, and the output end of the voltage follower serves as the output end of the voltage bias control unit.

12. The delay circuit according to claim 1, characterized in that: Also includes: A buffer, whose input end is connected to the output end of the second delay unit and whose output end outputs the third delayed signal, is used for shaping the second delayed signal to obtain the third delayed signal.

13. A time delay structure, characterized in that: include: A plurality of delay circuits as described in any one of claims 1 to 12 are connected in series, the input end of the first delay circuit receives the pulse signal, the output end of the M-1th delay circuit is connected to the input end of the Mth delay circuit, and the output end of the Mth delay circuit outputs a delay signal with a preset delay time, wherein M is an integer greater than or equal to 2.

14. The delay structure according to claim 13, characterized in that: The delay time between the rising edge of the preset delay signal and the rising edge of the pulse signal is recorded as the first preset delay time, and the delay time between the falling edge of the preset delay signal and the falling edge of the pulse signal is recorded as the second preset delay time. The change value of the first preset delay time and / or the second preset delay time as the first parameter of the delay structure changes is within the first range.

15. The time-delay structure according to claim 14, characterized in that: Also includes: A control encoding module is connected to the delay circuit and is used to control the first preset delay time and / or the second preset delay time.

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