A power-on reset circuit and method

Abstract

The present invention relates to the field of reset circuit technology, and specifically discloses a power-on reset circuit and method, the circuit comprising: a voltage divider, including a voltage-dividing MOS tube and a voltage-dividing resistor, provided with a voltage-dividing output point, used to generate a trigger voltage division and adjust the power consumption of the power-on reset circuit; a hysteresis device, including a hysteresis MOS tube, electrically connected to the voltage-dividing output point, used to avoid reset voltage jitter caused by power supply voltage jitter; a comparator, the input end of which is electrically connected to the voltage-dividing output point, and the output end of which is electrically connected to the input end of the hysteresis device, used to convert the trigger voltage division into a logic signal; a buffer, the input end of which is electrically connected to the output end of the comparator, and the output end is used as the output end of the power-on reset circuit, used to increase the driving capability of the power-on reset circuit. The present invention has a precise trigger point, is insensitive to process angle and temperature changes, the trigger point changes with process angle, temperature, and power supply voltage within + / -100mV, and does not rise with the increase of power supply voltage, has a small area, and is low in cost.

Description

Technical Field

[0001] The present invention relates to the technical field of reset circuits, and in particular to a power-on reset circuit and method. Background Art

[0002] The power-on reset provides an indication for the chip to start working after it is powered on. The power-on reset circuit generally generates a reset signal by using the different changes in different nodes during the power-on process. In high-precision products or when a memory cell IP is integrated on the chip, a relatively precise power-on reset point is required. This can not only ensure the minimum power supply voltage requirement of the memory cell IP, but also avoid the normal operation of other analog circuits affected by too low a power supply voltage. In addition, portable device applications usually have strict requirements on the overall power consumption of the chip, and it is inevitable to design a very low power power-on reset circuit. However, very low power circuits often mean a larger area, which will greatly increase the chip cost, thereby reducing the competitiveness of the chip.

[0003] A circuit structure of an existing power-on reset circuit is as follows Figure 1 As shown in the figure, the power-on reset circuit has the following disadvantages: 1. Large area. The voltage divider is composed of PMOS and NMOS tubes connected in series to achieve the connection between power supply and ground. In order to achieve low power consumption, the PMOS and NMOS tubes L / W of the voltage divider must be made very large; 2. The trigger point is highly dependent on the threshold voltage of PMOS and NMOS, and is sensitive to temperature and process corners; 3. The power consumption is highly dependent on the power supply voltage. The power consumption is large under high power supply voltage.

[0004] Another circuit structure of the existing power-on reset circuit is as follows Figure 2 As shown, the power-on reset circuit has the advantage of a simpler structure, but has the following disadvantages: 1. Large area: The voltage divider is composed of a PMOS tube, an NMOS tube and a resistor in series to achieve the connection from the power supply to the ground. In order to achieve low power consumption, the PMOS tube and the NMOS tube L / W of the voltage divider must be made very large; 2. The trigger point is highly dependent on the threshold voltage of the PMOS and NMOS, as well as the resistor, and is sensitive to temperature and process corners; 3. The power consumption is highly dependent on the power supply voltage. The power consumption is large under high power supply voltage, and the error is about + / -200mV.

[0005] Therefore, there is a particular need for a reset circuit that can achieve low power consumption, small area and temperature compensation, thereby improving the accuracy of the reset point.

[0006] Based on this technical background, the present invention studies a power-on reset circuit and method. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention proposes a power-on reset circuit and method. The circuit has a precise trigger point and is insensitive to process angle and temperature changes. The trigger point varies with process angle, temperature, and power supply voltage within + / -100mV, and does not increase with the increase of power supply voltage. It has a small area and low cost.

[0008] In order to achieve the above object, the present invention provides a power-on reset circuit in a first aspect, comprising:

[0009] A voltage divider, including a voltage-dividing MOS tube and a voltage-dividing resistor, is provided with a voltage-dividing output point, and is used to generate a trigger voltage divider and adjust the power consumption of the power-on reset circuit;

[0010] A hysteresis device, including a hysteresis MOS tube, electrically connected to the voltage division output point, and used to avoid reset voltage jitter caused by power supply voltage jitter;

[0011] A comparator, whose input terminal is electrically connected to the voltage division output point, and whose output terminal is electrically connected to the input terminal of the hysteresis device, and is used to convert the trigger voltage division into a logic signal;

[0012] A buffer, wherein the input end is electrically connected to the output end of the comparator, and the output end serves as the output end of the power-on reset circuit to output a reset voltage, so as to increase the driving capability of the power-on reset circuit.

[0013] A first aspect of the present invention provides a power-on reset method performed in the above-mentioned power-on reset circuit, comprising:

[0014] The trigger voltage division is generated by the voltage division MOS tube and the voltage division resistor and the power consumption of the power-on reset circuit is adjusted;

[0015] The trigger voltage division is transmitted to the input terminals of the hysteresis device and the comparator at the same time;

[0016] The hysteresis device performs signal hysteresis through the trigger voltage divider and the output signal of the comparator to avoid reset voltage jitter caused by power supply voltage jitter;

[0017] The comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer;

[0018] The buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit.

[0019] The beneficial effects of the present invention include:

[0020] (1) The power-on reset circuit proposed in the present invention has a precise trigger point and is insensitive to process angle and temperature changes. The trigger point varies with process angle, temperature, and power supply voltage within a range of + / -100mV and does not increase with the increase of power supply voltage. It has a small area and low cost.

[0021] (2) The power consumption of the power-on reset circuit proposed in the present invention is controlled by the leakage of the intrinsic NMOS tube and does not increase with the increase of the power supply voltage. The current in the voltage divider path can be flexibly changed by adjusting the resistance value of the voltage divider resistor, thereby achieving the extremely low power consumption target of the entire design.

[0022] (3) The power-on reset circuit proposed in the present invention controls the current by controlling the gate-source voltage of the intrinsic NMOS tube, thereby achieving an extremely low power consumption design and avoiding the use of large-sized MOS tubes, thereby saving costs.

[0023] (4) In the power-on reset circuit proposed in the present invention, the trigger voltage is controlled by the intrinsic NMOS tube, the first voltage-dividing NMOS tube and the second voltage-dividing NMOS tube. Since the three are NMOS transistors, better process and temperature tracking can be achieved, so that the trigger voltage changes less under different processes and temperatures.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0026] Figure 1 The present invention is a circuit structure schematic diagram of an existing power-on reset circuit.

[0027] Figure 2 The figure is another circuit structure schematic diagram of the existing power-on reset circuit.

[0028] Figure 3 The figure is a schematic structural diagram of a specific implementation mode of the power-on reset circuit proposed by the present invention.

[0029] Figure 4 The figure is a schematic diagram of voltage waveforms of each node in a specific implementation manner of the power-on reset circuit proposed by the present invention.

[0030] Description of reference numerals:

[0031] M0-second voltage-dividing NMOS tube, M1-first voltage-dividing NMOS tube, M2-intrinsic NMOS tube, M3-second hysteresis NMOS tube, M4-first hysteresis NMOS tube, M5-comparison NMOS tube, M6-comparison PMOS tube, M7-first buffer NMOS tube, M8-first buffer PMOS tube, M9-second buffer NMOS tube, M10-second buffer PMOS tube, R0-voltage-dividing resistor;

[0032] VDD-power supply, GND-ground, A-voltage divider output point, B-comparator output, PORB-output of the power-on reset circuit. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0034] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0035] The present invention provides a power-on reset circuit, such as Figure 3 As shown, including:

[0036] The voltage divider includes a voltage dividing MOS tube and a voltage dividing resistor R0, and is provided with a voltage dividing output point A, which is used to generate a trigger voltage divider and adjust the power consumption of the power-on reset circuit;

[0037] A hysteresis device, including a hysteresis MOS tube, is electrically connected to the voltage divider output point A and is used to avoid reset voltage jitter caused by power supply VDD voltage jitter;

[0038] A comparator, whose input terminal is electrically connected to the voltage division output point A, and whose output terminal is electrically connected to the input terminal of the hysteresis device, for converting the trigger voltage division into a logic signal;

[0039] The buffer has an input end electrically connected to the comparator output end B, and an output end serving as an output end PORB of the power-on reset circuit to output a reset voltage for increasing the driving capability of the power-on reset circuit.

[0040] In the present invention, the trigger point is accurate and insensitive to process angle and temperature changes. The trigger point changes with process angle, temperature, and power supply VDD voltage within + / -100mV and does not increase with the increase of power supply VDD voltage. It has a small area and low cost.

[0041] According to the present invention, the voltage-dividing MOS transistor includes an intrinsic NMOS transistor M2, a first voltage-dividing NMOS transistor M1, and a second voltage-dividing NMOS transistor M0;

[0042] The drain of the intrinsic NMOS tube M2 is electrically connected to the power supply VDD, and the source is electrically connected to one end of the voltage dividing resistor R0;

[0043] The other end of the voltage-dividing resistor R0 is electrically connected to the gate of the intrinsic NMOS transistor M2 and the drain of the first voltage-dividing NMOS transistor M1 at the same time, and serves as a voltage-dividing output point A;

[0044] The source of the first voltage-dividing NMOS tube M1 is electrically connected to the drain of the second voltage-dividing NMOS tube M0, and the gate is electrically connected to the power supply VDD;

[0045] The source of the second voltage-dividing NMOS tube M0 is electrically connected to the ground GND, and the gate is electrically connected to its own drain.

[0046] In the present invention, power consumption is controlled by leakage of the intrinsic NMOS tube M2 and does not increase with the increase of the power supply VDD voltage. The current in the voltage divider path can be flexibly changed by adjusting the resistance value of the voltage divider resistor R0, thereby achieving the extremely low power consumption target of the entire design.

[0047] In the present invention, the current is controlled by controlling the gate-source voltage of the intrinsic NMOS tube M2, thereby achieving an extremely low power consumption design and avoiding the use of a large-sized MOS tube, thereby saving costs.

[0048] In the present invention, the trigger voltage is controlled by the intrinsic NMOS tube M2, the first voltage-dividing NMOS tube M1 and the second voltage-dividing NMOS tube M0. Since all three are NMOS transistors, better process and temperature tracking can be achieved, so that the trigger point voltage changes less under different processes and temperatures.

[0049] In the present invention, the trigger point voltage refers to the voltage of the power supply corresponding to the moment when the reset voltage suddenly changes from a logic low level to a logic high level or from a logic high level to a logic low level as the power rises or falls; the trigger voltage is the voltage generated by the trigger point voltage at the voltage divider output point A of the voltage divider, such as Figure 3 shown.

[0050] According to the present invention, the hysteresis NMOS transistor includes a first hysteresis NMOS transistor M4 and a second hysteresis NMOS transistor M3;

[0051] The drain of the first hysteresis NMOS tube M4 is electrically connected to the voltage division output point A, and the source is electrically connected to the drain of the second hysteresis NMOS tube M3;

[0052] The source of the second hysteresis NMOS transistor M3 is electrically connected to the ground GND, and the gate is electrically connected to its own drain.

[0053] According to the present invention, the comparator includes a comparison PMOS tube M6 and a comparison NMOS tube M5;

[0054] The source of the comparison PMOS tube M6 is electrically connected to the power supply VDD, and the drain is electrically connected to the drain of the comparison NMOS tube M5;

[0055] The source of the comparison NMOS tube M5 is electrically connected to the ground GND, and the drain is electrically connected to the gate of the first hysteresis NMOS tube M4;

[0056] The gates of the comparison PMOS tube M6 and the comparison NMOS tube M5 are electrically connected to the voltage division output point A at the same time.

[0057] Preferably, the buffer comprises at least two stages of buffer units connected in series;

[0058] The input end of the first-stage buffer unit is electrically connected to the drain of the comparison NMOS tube M5;

[0059] The output end of the final buffer unit serves as the output end PORB of the power-on reset circuit;

[0060] Except for the last stage, the input end of each buffer unit is electrically connected to the output end of the buffer unit of the previous stage;

[0061] The number of buffer units connected in series at least two stages is an even number.

[0062] Preferably, each buffer unit comprises a buffer PMOS tube and a buffer NMOS tube;

[0063] The source of the buffer PMOS tube is electrically connected to the power supply VDD, and the drain is electrically connected to the drain of the buffer NMOS tube;

[0064] The source of the buffer NMOS tube is electrically connected to the ground GND;

[0065] The gates of the buffer PMOS tube and the buffer NMOS tube are electrically connected to each other and serve as the input end of the buffer unit;

[0066] The drain of the buffer NMOS tube serves as the output end of the buffer unit.

[0067] The present invention also provides a power-on reset method performed in the power-on reset circuit, comprising:

[0068] The trigger voltage is generated by the voltage-dividing MOS tube and the voltage-dividing resistor R0 and the power consumption of the power-on reset circuit is adjusted;

[0069] The trigger voltage is transmitted to the input of the hysteresis device and the comparator at the same time;

[0070] The hysteresis device delays the signal by triggering the voltage divider and the output signal of the comparator to avoid the reset voltage jitter caused by the power supply VDD voltage jitter;

[0071] The comparator converts the trigger voltage into a logic signal and outputs it to the buffer;

[0072] The buffer converts the logic signal output by the comparator into a driving signal to drive the external circuit.

[0073] According to the present invention, generating a trigger voltage divider through a voltage divider MOS tube and a voltage divider resistor R0 and adjusting the power consumption of a power-on reset circuit includes:

[0074] When the power supply VDD voltage is lower than the sum of the threshold voltages of the first voltage-dividing NMOS tube M1 and the second voltage-dividing NMOS tube M0, the first voltage-dividing NMOS tube M1 and the second voltage-dividing NMOS tube M0 are both turned off, the intrinsic NMOS tube M2 is turned on without current, and the trigger voltage division is high level;

[0075] When the power supply VDD voltage is not less than the sum of the threshold voltages of the first voltage-dividing NMOS tube M1 and the second voltage-dividing NMOS tube M0 and gradually increases, the voltage between the source and drain of the intrinsic NMOS tube M2 gradually increases, the current flowing through it gradually increases, and the voltage between the gate and source gradually decreases and its value is equal to the negative value of the product of the current flowing through the intrinsic NMOS tube M2 and the voltage-dividing resistor R0. In this process, the intrinsic NMOS tube M2 works in the linear region, and the trigger voltage is gradually reduced;

[0076] When the power supply VDD voltage increases to the trigger point voltage, the trigger voltage is low enough to make the reset voltage suddenly change from a logic low level to a logic high level;

[0077] When the power supply VDD voltage continues to increase, so that the decrease in the voltage between the gate and source of the intrinsic NMOS tube M2 causes the decrease in the current flowing through it to exceed the increase in the voltage between the source and drain causing the increase in the current flowing through it, the intrinsic NMOS tube M2 operates in the saturation region, the current flowing through it remains unchanged, and the value of the trigger voltage division is close to the gate-source voltage of the second voltage division NMOS tube M0 and remains unchanged;

[0078] By adjusting the size of the voltage regulating resistor, the current flowing through the voltage divider path is adjusted, thereby adjusting the power consumption of the power-on reset circuit.

[0079] Preferably, the hysteresis device performs signal hysteresis by triggering the voltage divider and the output signal of the comparator to avoid the reset voltage jitter caused by the power supply VDD voltage jitter, including:

[0080] When the trigger voltage is high, the output voltage of the comparator is low and the hysteresis is turned off;

[0081] When the trigger voltage is gradually reduced to the threshold voltage of the comparator, the output voltage of the comparator is high, the first hysteresis NMOS tube M4 is turned on due to the increase of the gate voltage, and the second hysteresis NMOS tube M3 is turned on to continue to lower the trigger voltage. If the power supply VDD voltage at power-off drops to the trigger point voltage when the power supply VDD rises, the trigger voltage prevents the reset voltage from changing from a logic high level to a logic low level unless the power supply VDD voltage continues to decrease, thereby avoiding reset voltage jitter caused by power supply VDD voltage jitter.

[0082] According to the present invention, the buffer converts the logic signal output by the comparator into a driving signal to drive the external circuit, including:

[0083] The logic signal output by the comparator is converted into a driving signal in stages to drive an external circuit through at least two stages of buffer units connected in series.

[0084] The present invention will be described in more detail below through specific embodiments. Example 1

[0085] like Figure 3 As shown, this embodiment provides a power-on reset circuit, including:

[0086] The voltage divider includes a voltage dividing MOS tube and a voltage dividing resistor R0, and is provided with a voltage dividing output point A, which is used to generate a trigger voltage divider and adjust the power consumption of the power-on reset circuit;

[0087] A hysteresis device, including a hysteresis MOS tube, is electrically connected to the voltage divider output point A and is used to avoid reset voltage jitter caused by power supply VDD voltage jitter;

[0088] A comparator, whose input terminal is electrically connected to the voltage division output point A, and whose output terminal is electrically connected to the input terminal of the hysteresis device, for converting the trigger voltage division into a logic signal;

[0089] A buffer, wherein the input end is electrically connected to the output end B of the comparator, and the output end serves as the output end PORB of the power-on reset circuit to output a reset voltage, so as to increase the driving capability of the power-on reset circuit;

[0090] The voltage-dividing MOS transistor includes an intrinsic NMOS transistor M2, a first voltage-dividing NMOS transistor M1, and a second voltage-dividing NMOS transistor M0;

[0091] The drain of the intrinsic NMOS tube M2 is electrically connected to the power supply VDD, and the source is electrically connected to one end of the voltage dividing resistor R0;

[0092] The other end of the voltage-dividing resistor R0 is electrically connected to the gate of the intrinsic NMOS transistor M2 and the drain of the first voltage-dividing NMOS transistor M1 at the same time, and serves as a voltage-dividing output point A;

[0093] The source of the first voltage-dividing NMOS tube M1 is electrically connected to the drain of the second voltage-dividing NMOS tube M0, and the gate is electrically connected to the power supply VDD;

[0094] The source of the second voltage-dividing NMOS tube M0 is electrically connected to the ground GND, and the gate is electrically connected to its own drain;

[0095] The hysteresis NMOS transistor includes a first hysteresis NMOS transistor M4 and a second hysteresis NMOS transistor M3;

[0096] The drain of the first hysteresis NMOS tube M4 is electrically connected to the voltage division output point A, and the source is electrically connected to the drain of the second hysteresis NMOS tube M3;

[0097] The source of the second hysteresis NMOS tube M3 is electrically connected to the ground GND, and the gate is electrically connected to its own drain;

[0098] The comparator includes a comparison PMOS tube M6 and a comparison NMOS tube M5;

[0099] The source of the comparison PMOS tube M6 is electrically connected to the power supply VDD, and the drain is electrically connected to the drain of the comparison NMOS tube M5;

[0100] The source of the comparison NMOS tube M5 is electrically connected to the ground GND, and the drain is electrically connected to the gate of the first hysteresis NMOS tube M4;

[0101] The gates of the comparison PMOS tube M6 and the comparison NMOS tube M5 are electrically connected to the voltage division output point A at the same time;

[0102] In this embodiment, the buffer includes two stages of buffer units connected in series;

[0103] The input end of the first-stage buffer unit is electrically connected to the drain of the comparison NMOS tube M5;

[0104] The output end of the second-stage buffer unit serves as the output end PORB of the power-on reset circuit;

[0105] The input end of the second-stage buffer unit is electrically connected to the output end of the first-stage buffer unit;

[0106] In this embodiment, the first-stage buffer unit includes a first buffer PMOS tube M8 and a second buffer NMOS tube M7; the second-stage buffer unit includes a second buffer PMOS tube M10 and a second buffer NMOS tube M9;

[0107] The source of each buffer PMOS tube is electrically connected to the power supply VDD, and the drain is electrically connected to the drain of the buffer NMOS tube;

[0108] The source of each buffer NMOS tube is electrically connected to the ground GND;

[0109] The gates of the buffer PMOS tube and the buffer NMOS tube of each stage are electrically connected to each other and serve as the input end of the buffer unit;

[0110] The drain of each buffer NMOS tube serves as the output end of the buffer unit.

[0111] This embodiment provides a power-on reset method, including:

[0112] When the power supply VDD voltage is low, the second voltage-dividing NMOS tube M0 or the first voltage-dividing NMOS tube M1 is not conducting, and the voltage divider path is closed; the intrinsic NMOS tube M2 can be conducting but no current flows through it, and its Vgs=0, Vds=0; the voltage-dividing output point A rises with the power supply VDD voltage; the comparator output terminal B is at a low level at this time, and the output terminal PORB of the power-on reset circuit is at a low level; at this time, the gate voltage of the first hysteresis NMOS tube M4 is at a low level, and the hysteresis path is in a closed state;

[0113] When the power supply VDD voltage gradually exceeds the sum of the threshold voltages of the second voltage-dividing NMOS tube M0 and the first voltage-dividing NMOS tube M1, the second voltage-dividing NMOS tube M0 and the first voltage-dividing NMOS tube M1 are gradually turned on, and the voltage-dividing output point A is sharply pulled down; at this time, the intrinsic NMOS tube M2 is in the linear region, and its Vds gradually increases, so the current gradually increases, but the Vgs of the intrinsic NMOS tube M2 also gradually decreases; Vgs_M2=-I*R0; when the voltage of the voltage-dividing output point A drops to the threshold voltage of the comparator, the voltage of the comparator output terminal B rises rapidly, and the output terminal PORB signal of the power-on reset circuit jumps from 0 to 1;

[0114] When the power supply VDD voltage reaches a certain value, the decrease in the Vgs of the intrinsic NMOS tube M2 will lead to a decrease in the current of the intrinsic NMOS tube M2, which will exceed the increase in the Vds, which will lead to an increase in the current of the intrinsic NMOS tube M2. After that, the current of the intrinsic NMOS tube M2 remains constant. A sufficiently large Vds allows the intrinsic NMOS tube M2 to enter the saturation region. The power supply VDD voltage continues to rise and the current of the intrinsic NMOS tube M2 remains unchanged. At this time, the voltage at the voltage divider output point A approaches the Vgs of the second voltage divider NMOS tube M0 and remains unchanged.

[0115] The hysteresis path is turned on due to the high gate voltage of the first hysteresis NMOS tube M4, and the current generated by the second hysteresis NMOS tube M3 and the first hysteresis NMOS tube M4 pulls the voltage-dividing output point A down to a lower level, so that the trigger point when the power supply VDD is powered off is lower than when the power supply VDD is raised, thereby avoiding the jitter of the output terminal PORB of the power-on reset circuit caused by the jitter of the power supply VDD;

[0116] By adjusting the resistance value of the voltage divider resistor R0, the current in the voltage divider path can be flexibly changed, thereby achieving the extremely low power consumption goal of the entire design;

[0117] In the circuit, the current is controlled by controlling the Vgs of the intrinsic NMOS tube M2, which not only realizes the extremely low power consumption design, but also avoids the use of large-sized MOS tubes, thereby saving costs.

[0118] The trigger voltage division of the voltage division output point A is limited by the intrinsic NMOS tube M2, the first voltage division NMOS tube M1 and the second voltage division NMOS tube M0; since the three are NMOS transistors, better process and temperature tracking can be achieved, so that the trigger point changes less under different processes and temperatures.

[0119] Figure 4 A schematic diagram of voltage waveforms of various nodes in a power-on reset circuit is shown, from which it can be seen that the power-on reset method proposed in the present invention achieves accurate triggering of the trigger point.

[0120] The power-on reset circuit proposed in the embodiment of the present invention has a precise trigger point and is insensitive to process angle and temperature changes. The trigger point varies with process angle, temperature, and power supply voltage within + / -100mV and does not increase with the increase of power supply voltage. It has a small area and low cost.

[0121] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A power-on reset circuit, characterized in that: include: A voltage divider, including a voltage-dividing MOS tube and a voltage-dividing resistor, is provided with a voltage-dividing output point, and is used to generate a trigger voltage divider and adjust the power consumption of the power-on reset circuit; A hysteresis device, including a hysteresis NMOS tube, electrically connected to the voltage-dividing output point, and used to avoid reset voltage jitter caused by power supply voltage jitter; A comparator, whose input terminal is electrically connected to the voltage division output point, and whose output terminal is electrically connected to the input terminal of the hysteresis device, and is used to convert the trigger voltage division into a logic signal; A buffer, whose input end is electrically connected to the output end of the comparator, and whose output end serves as the output end of the power-on reset circuit to output the reset voltage, so as to increase the driving capability of the power-on reset circuit; The voltage-dividing MOS tube comprises an intrinsic NMOS tube, a first voltage-dividing NMOS tube and a second voltage-dividing NMOS tube; The drain of the intrinsic NMOS tube is electrically connected to the power supply, and the source is electrically connected to one end of the voltage dividing resistor; The other end of the voltage-dividing resistor is electrically connected to the gate of the intrinsic NMOS tube and the drain of the first voltage-dividing NMOS tube at the same time, and serves as the voltage-dividing output point; The source of the first voltage-dividing NMOS tube is electrically connected to the drain of the second voltage-dividing NMOS tube, and the gate is electrically connected to the power supply; The source of the second voltage-dividing NMOS tube is electrically connected to the ground, and the gate is electrically connected to its own drain.

2. The power-on reset circuit according to claim 1, characterized in that: The hysteresis NMOS transistor comprises a first hysteresis NMOS transistor and a second hysteresis NMOS transistor; The drain of the first hysteresis NMOS tube is electrically connected to the voltage division output point, and the source is electrically connected to the drain of the second hysteresis NMOS tube; The source of the second hysteresis NMOS tube is electrically connected to the ground, and the gate is electrically connected to its own drain.

3. The power-on reset circuit according to claim 2, characterized in that: The comparator comprises a comparison PMOS tube and a comparison NMOS tube; The source of the comparison PMOS tube is electrically connected to the power supply, and the drain is electrically connected to the drain of the comparison NMOS tube; The source of the comparison NMOS tube is electrically connected to the ground, and the drain is electrically connected to the gate of the first hysteresis NMOS tube; The gates of the comparison PMOS tube and the comparison NMOS tube are electrically connected to the voltage division output point at the same time.

4. The power-on reset circuit according to claim 3, characterized in that: The buffer comprises at least two stages of buffer units connected in series; The input end of the first-stage buffer unit is electrically connected to the drain of the comparison NMOS tube; The output end of the final buffer unit serves as the output end of the power-on reset circuit; Except for the last stage, the input end of each buffer unit is electrically connected to the output end of the buffer unit of the previous stage; The number of the at least two stages of buffer units connected in series is an even number.

5. The power-on reset circuit according to claim 4, characterized in that: Each buffer unit includes a buffer PMOS tube and a buffer NMOS tube; The source of the buffer PMOS tube is electrically connected to a power supply, and the drain is electrically connected to the drain of the buffer NMOS tube; The source of the buffer NMOS tube is electrically connected to the ground; The gates of the buffer PMOS tube and the buffer NMOS tube are electrically connected to each other and serve as the input end of the buffer unit; The drain of the buffer NMOS tube serves as the output end of the buffer unit.

6. A power-on reset method performed in the power-on reset circuit according to any one of claims 1 to 5, characterized in that: include: The trigger voltage division is generated by the voltage division MOS tube and the voltage division resistor and the power consumption of the power-on reset circuit is adjusted; The trigger voltage division is transmitted to the input terminals of the hysteresis device and the comparator at the same time; The hysteresis device performs signal hysteresis through the trigger voltage divider and the output signal of the comparator to avoid reset voltage jitter caused by power supply voltage jitter; The comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer; The buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit; Generating the trigger voltage division by the voltage division MOS tube and the voltage division resistor and adjusting the power consumption of the power-on reset circuit includes: When the power supply voltage is lower than the sum of the threshold voltages of the first voltage-dividing NMOS tube and the second voltage-dividing NMOS tube, the first voltage-dividing NMOS tube and the second voltage-dividing NMOS tube are both off, the intrinsic NMOS tube is on without current, and the trigger voltage division is high level; When the power supply voltage is not less than the sum of the threshold voltages of the first voltage-dividing NMOS tube and the second voltage-dividing NMOS tube and gradually increases, the voltage between the source and drain of the intrinsic NMOS tube gradually increases, the current flowing through it gradually increases, and the voltage between the gate and source gradually decreases and its value is equal to the negative value of the product of the current flowing through the intrinsic NMOS tube and the voltage-dividing resistor. In this process, the intrinsic NMOS tube works in the linear region, and the trigger voltage is gradually reduced; When the power supply voltage increases to the trigger point voltage, the trigger voltage is low enough to make the reset voltage suddenly change from a logic low level to a logic high level; When the power supply voltage continues to increase, so that the decrease in the voltage between the gate and source of the intrinsic NMOS tube causes the decrease in the current flowing through it to exceed the increase in the voltage between the source and drain causing the increase in the current flowing through it, the intrinsic NMOS tube operates in the saturation region, the current flowing through it remains unchanged, and the value of the trigger voltage division is close to the gate-source voltage of the second voltage division NMOS tube and remains unchanged; By adjusting the size of the voltage divider resistor, the current flowing through the voltage divider path is adjusted, thereby adjusting the power consumption of the power-on reset circuit.

7. The power-on reset circuit according to claim 6, characterized in that: The hysteresis device performs signal hysteresis through the trigger voltage divider and the output signal of the comparator to avoid reset voltage jitter caused by power supply voltage jitter, including: When the trigger voltage division is at a high level, the output voltage of the comparator is at a low level, and the hysteresis device is turned off; When the trigger voltage divider gradually decreases to the threshold voltage of the comparator, the output voltage of the comparator is high, the first hysteresis NMOS tube is turned on due to the increase in gate voltage, and the second hysteresis NMOS tube is turned on to continue to pull down the trigger voltage divider. If the power supply voltage at power-off drops to the trigger point voltage when the power supply rises, the trigger voltage divider prevents the reset voltage from changing from a logic high level to a logic low level unless the power supply voltage continues to decrease, thereby avoiding reset voltage jitter caused by power supply voltage jitter.

8. The power-on reset circuit according to claim 7, characterized in that: The buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit, including: The logic signal output by the comparator is converted into a driving signal in stages to drive an external circuit through at least two stages of buffer units connected in series.

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