Buffer circuit

Abstract

The buffer circuit is configured to receive first and second input signals via first and second input transistors coupled to a first power supply voltage node, and output a first output signal via a first output node and a second output signal via a second output node based on the first and second output signals. The load circuit is coupled between the first output node, the second output node, and a second power supply voltage node, and adjusts a resistance value based on at least one of the first output signal and the second output signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Application No. 10-2020-0111435 filed on September 2, 2020, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. Technical Field

[0003] Various embodiments relate generally to integrated circuit technology and, more particularly, to buffer circuits. Background Art

[0004] An electronic device includes many electronic components, and a computer system, which is the electronic device, includes many semiconductor devices, each of which is composed of a semiconductor. The semiconductor devices that make up the computer system can communicate with each other by sending and receiving clock signals and data. Each semiconductor device may include a buffer circuit configured to amplify and / or buffer an input signal to generate an output signal. Summary of the Invention

[0005] In one embodiment, the buffer circuit may include a first input transistor, a second input transistor, and a load circuit. The first input transistor may be coupled between a first power supply voltage node and a second output node and may be configured to change a voltage level of the second output node based on a first input signal. The second input transistor may be coupled between the first power supply voltage node and the first output node and may be configured to change a voltage level of the first output node based on a second input signal. The load circuit may be coupled between the first output node, the second output node, and the second power supply voltage node. The resistance value of the load circuit may be adjusted based on at least one of a first output signal output from the first output node and a second output signal output from the second output node.

[0006] In one embodiment, the buffer circuit may include a first input transistor, a second input transistor, a load control circuit, and a load circuit. The first input transistor may be coupled between a first power supply voltage node and a second output node, and may be configured to change a voltage level of the second output node based on a first input signal. The second input transistor may be coupled between the first power supply voltage node and the first output node, and may be configured to change a voltage level of the first output node based on a second input signal. The load control circuit may be configured to generate at least one load control signal based on a first output signal output from the first output node and a second output signal output from the second output node. The load circuit may be coupled between the first output node, the second output node, and a second power supply voltage node, and may be configured to adjust a resistance value between the first output node, the second output node, and the second power supply voltage node based on at least one load control signal.

[0007] In one embodiment, a buffer circuit may include a first input transistor, a second input transistor, a load control circuit, a first load resistor, a second load resistor, a first switching transistor, and a second switching transistor. The first input transistor may be coupled between a first power supply voltage node and a second output node and may be configured to change the voltage level of the second output node based on a first input signal. The second input transistor may be coupled between the first power supply voltage node and the first output node and may be configured to change the voltage level of the first output node based on a second input signal. The load control circuit may be configured to generate a first load control signal and a second load control signal based on a first output signal from the first output node and a second output signal from the second output node. The first load resistor may include one end coupled to the second output node and another end coupled to the second power supply voltage node. The second load resistor may include one end coupled to the first output node and another end coupled to the second power supply voltage node. The first switching transistor may be configured to couple one end of the first load resistor to one end of the second load resistor based on the first load control signal. The second switching transistor may be configured to couple one end of the first load resistor to one end of the second load resistor based on the second load control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing a configuration of a buffer circuit according to an embodiment.

[0009] Figure 2 is a diagram illustrating the operation of the buffer circuit according to the embodiment.

[0010] Figure 3 is a diagram showing a configuration of a buffer circuit according to an embodiment.

[0011] Figure 4 is a diagram showing a configuration of a buffer circuit according to an embodiment.

[0012] Figure 5 is a diagram showing a configuration of a buffer circuit according to an embodiment.

[0013] Figure 6 is a diagram showing a configuration of a buffer circuit according to an embodiment.

[0014] Figure 7 is a diagram showing a configuration of a buffer circuit according to an embodiment. DETAILED DESCRIPTION

[0015] Typically, a buffer circuit may be a differential amplifier configured to differentially amplify a positive input signal and a negative input signal to generate an output signal. As the operating speed of semiconductor devices increases, the output signal generated by the buffer circuit tends to have a distorted duty cycle. A buffer circuit has been proposed that incorporates a circuit configured to adjust the duty cycle of the output signal. However, due to the load added to the buffer circuit, the gain and bandwidth of the buffer circuit may decrease.

[0016] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0017] Figure 1 is a diagram showing the configuration of a buffer circuit 100 according to an embodiment. Figure 1Buffer circuit 100 may receive a first input signal INP and a second input signal INN to generate output signals OUTP and OUTN. Buffer circuit 100 may differentially amplify the first input signal INP and the second input signal INN to generate output signals OUTP and OUTN. The signal input to buffer circuit 100 may be a differential signal or a single-ended signal. When the signal input to buffer circuit 100 is a differential signal, the second input signal INN may be a complementary signal having a voltage level opposite to that of the first input signal INP. When the signal input to buffer circuit 100 is a single-ended signal, the second input signal INN may be a reference voltage. The reference voltage may have a voltage level corresponding to the middle of the voltage level range of the first input signal INP. Output signals OUTP and OUTN may include a first output signal OUTP and a second output signal OUTN. The first output signal OUTP may have a voltage level that varies according to the voltage level of the second input signal INN. The second output signal OUTN may have a voltage level opposite to that of the first output signal OUTP. The second output signal OUTN may be a complementary signal to the first output signal OUTP. The second output signal OUTN may have a voltage level that varies according to a voltage level change of the first input signal INP. The buffer circuit 100 may adjust the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN by adjusting the transition timing of the voltage level of the first output signal OUTP and / or the second output signal OUTN and the transition timing of the logic level of the first output signal OUTP and / or the second output signal OUTN. To adjust the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN, the buffer circuit 100 may control the load and / or current of the buffer circuit 100. For example, the buffer circuit 100 may adjust the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN by adjusting the resistance value of the load. The buffer circuit 100 may adjust the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN by adjusting the amount of current released from the node that outputs the first output signal OUTP and / or the second output signal OUTN.

[0018] Buffer circuit 100 may include a first input transistor 111, a second input transistor 112, and a load circuit 120. First input transistor 111 may be coupled between first power supply voltage node 101 and a second output node ON. First input transistor 111 may receive a first input signal INP. First input transistor 111 may change the voltage level of second output node ON based on the first input signal INP. First power supply voltage node 101 may be a voltage rail through which a first power supply voltage VDDH is provided. A second output signal OUTN may be output through second output node ON. Second output node ON may be a negative output node. Second input transistor 112 may be coupled between first power supply voltage node 101 and first output node OP. Second input transistor 112 may receive a second input signal INN. Second input transistor 112 may change the voltage level of first output node OP based on the second input signal INN. First output signal OUTP may be output through first output node OP. First output node OP may be a positive output node. Each of first input transistor 111 and second input transistor 112 may be a P-channel metal oxide semiconductor (MOS) transistor.

[0019] The load circuit 120 can be coupled between the first output node OP, the second output node ON, and the second power supply voltage node 102. The second power supply voltage node 102 can be a voltage rail through which the second power supply voltage VDDL is provided. The first power supply voltage VDDH can have a higher voltage level than the second power supply voltage VDDL. The resistance value of the load circuit 120 can be adjusted based on at least one of the first output signal OUTP and the second output signal OUTN. When the resistance value of the load circuit 120 is adjusted, the duty cycle and / or phase of the first output signal OUTP can be adjusted. For example, the buffer circuit 100 can increase or decrease the duty cycle of the first output signal OUTP by adjusting the resistance value of the load circuit 120. The buffer circuit 100 can advance the phase of the first output signal OUTP. To reduce the duty cycle of the first output signal OUTP, the buffer circuit 100 can reduce the resistance value of the load circuit 120 during the period when the voltage level of the first output signal OUTP is at a logic high level. The duty cycle of the first output signal OUTP can be defined as the ratio of the high-level portion of the first output signal OUTP to the low-level portion of the first output signal OUTP. To increase the duty cycle of the first output signal OUTP, the buffer circuit 100 may reduce the resistance of the load circuit 120 during a period when the voltage level of the second output signal OUTN is at a logic high level. To advance the phase of the first output signal OUTP, the buffer circuit 100 may reduce the resistance of the load circuit 120 during a period when the voltage level of the first output signal OUTP is at a logic high level, and may further reduce the resistance of the load circuit 120 during a period when the voltage level of the second output signal OUTN is at a logic high level.

[0020] The buffer circuit 100 may further include a load control circuit 130. The load control circuit 130 may receive the first output signal OUTP and the second output signal OUTN to generate at least one load control signal. To adjust the duty cycle of the first output signal OUTP, the load control circuit 130 may generate a load control signal based on the first output signal OUTP. To adjust the duty cycle of the first output signal OUTP, the load control circuit 130 may generate a load control signal based on the second output signal OUTN. To advance the phase of the first output signal OUTP, the load control circuit 130 may generate a load control signal based on the first output signal OUTP and another load control signal based on the second output signal OUTN. The load control circuit 130 may generate a first load control signal LC1 and a second load control signal LC2 based on the first output signal OUTP and the second output signal OUTN. The load control circuit 130 may provide the first output signal OUTP as the first load control signal LC1 and the second output signal OUTN as the second load control signal LC2. In one embodiment, to reduce the duty cycle of the first output signal OUTP, the load control circuit 130 may provide the first output signal OUTP as the first load control signal LC1 and disable the second load control signal LC2. For example, the load control circuit 130 may provide the first output signal OUTP as the first load control signal LC1 while keeping the second load control signal LC2 disabled. The second load control signal LC2 may be disabled to a logic low level. In one embodiment, to increase the duty cycle of the first output signal OUTP, the load control circuit 130 may provide the second output signal OUTN as the second load control signal LC2 and disable the first load control signal LC1. For example, the load control circuit 130 may provide the second output signal OUTN as the second load control signal LC2 while keeping the first load control signal LC1 disabled. The first load control signal LC1 may be disabled to a logic low level. To advance the phase of the first output signal OUTP, the load control circuit 130 may provide the first output signal OUTP as the first load control signal LC1 and may provide the second output signal OUTN as the second load control signal LC2.

[0021] The load circuit 120 may receive at least one load control signal from the load control circuit 130. The load circuit 120 may adjust the resistance value between the first output node OP, the second output node ON, and the second power supply voltage node 102 based on the at least one load control signal. The load circuit 120 may include a first load resistor RL1, a second load resistor RL2, and at least one switching transistor. The first load resistor RL1 may be coupled between the second output node ON and the second power supply voltage node 102. One end of the first load resistor RL1 may be coupled to the second output node ON, and the other end of the first load resistor RL1 may be coupled to the second power supply voltage node 102. The second load resistor RL2 may be coupled between the first output node OP and the second power supply voltage node 102. One end of the second load resistor RL2 may be coupled to the first output node OP, and the other end of the second load resistor RL2 may be coupled to the second power supply voltage node 102. The resistance value of the second load resistor RL2 may be substantially the same as the resistance value of the first load resistor RL1. In one embodiment, the resistance value of the second load resistor RL2 may be different from the resistance value of the first load resistor RL1. The first load resistor RL1 may form a current path from the second output node ON to the second power supply voltage node 102. The second load resistor RL2 may form a current path from the first output node OP to the second power supply voltage node 102.

[0022] At least one switching transistor can couple the first load resistor RL1 and the second load resistor RL2 in parallel with each other based on at least one load control signal. When the at least one switching transistor is turned on and couples the first load resistor RL1 and the second load resistor RL2 in parallel with each other, the resistance value of the load circuit 120 can be reduced. The load circuit 120 can include a first switching transistor 121 and a second switching transistor 122. The first switching transistor 121 can be coupled between one end of the first load resistor RL1 and one end of the second load resistor RL2. The first switching transistor 121 can receive a first load control signal LC1. The first switching transistor 121 can couple the first load resistor RL1 and the second load resistor RL2 in parallel with each other based on the first load control signal LC1. The second switching transistor 122 can be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The second switching transistor 122 can receive a second load control signal LC2. The second switching transistor 122 can couple the first load resistor RL1 and the second load resistor RL2 in parallel with each other based on the second load control signal LC2. When each of the first input transistor 111 and the second input transistor 112 is a P-channel MOS transistor, each of the first switch transistor 121 and the second switch transistor 122 may be an N-channel MOS transistor.

[0023] The load circuit 120 may further include a third load resistor RL3 and a fourth load resistor RL4. The third load resistor RL3 may be coupled in series to the first load resistor RL1 between the second output node ON and the first load resistor RL1. The fourth load resistor RL4 may be coupled in series to the second load resistor RL2 between the first output node OP and the second load resistor RL2. The resistance value of the fourth load resistor RL4 may be substantially the same as the resistance value of the third load resistor RL3. When one of the first switching transistor 121 and the second switching transistor 122 is turned on, an electrical connection may be formed between the first output node OP and the second output node ON. The third load resistor RL3 and the fourth load resistor RL4 may prevent the first output node OP and the second output node ON from being equal, so that: during an evaluation period in which a voltage level difference occurs between the first output node OP and the second output node ON, the voltage level of one of the first output node OP and the second output node ON does not affect the voltage level of the other of the first output node OP and the second output node ON.

[0024] Buffer circuit 100 may further include an enable transistor 140. Enable transistor 140 may be coupled between first power supply voltage node 101, first input transistor 111, and second input transistor 112. Enable transistor 140 may receive an enable signal EN. Enable signal EN may be a control signal for enabling buffer circuit 100. When enable signal EN is enabled to a logic low level, enable transistor 140 may couple first power supply voltage node 101 to first input transistor 111 and second input transistor 112, thereby forming a current path from first power supply voltage node 101 to first input transistor 111 and second input transistor 112, respectively.

[0025] Figure 2 is a diagram illustrating the operation of the buffer circuit according to the embodiment. Figure 2 Shown according to Figure 1 The operation of the buffer circuit 100 in FIG. 1 is a waveform of the first output signal OUTP and the second output signal OUTN output from the buffer circuit 100. In the following, referring to FIG. Figure 1 and Figure 2The operation of the buffer circuit 100 according to the embodiment will be described. When the buffer circuit 100 does not perform any compensation operation on the first output signal OUTP, both the first load control signal LC1 and the second load control signal LC2 may be disabled to a logic low level ("L"). Since the load circuit 120 receives the disabled first and second load control signals LC1 and LC2, the resistance value of the load circuit 120 may not change. Ideally, when the duty ratio of each of the first input signal INP and the second input signal INN is 50:50, the first output signal OUTP and the second output signal OUTN outputted from the buffer circuit 100 may each have a duty ratio of 50:50 ("duty ratio = 50%"). However, even when the duty ratio of each of the first input signal INP and the second input signal INN is 50:50, the first output signal OUTP may not maintain a 50% duty ratio due to characteristics of the buffer circuit (e.g., process variations) or offsets. Moreover, the output timing of the first output signal OUTP and the second output signal OUTN may be delayed. The buffer circuit 100 may compensate for process variations and offsets of the buffer circuit 100 by adjusting the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN.

[0026] To reduce the duty cycle of the first output signal OUTP, the load control circuit 130 may output the first output signal OUTP as the first load control signal LC1 while maintaining the second load control signal LC2 disabled at a logic low level ("L"). The first switching transistor 121 may be turned on during a period when the voltage level of the first load control signal LC1 is at a logic high level, that is, during a period when the voltage level of the first output signal OUTP is at a logic high level. When the first switching transistor 121 is turned on, the first load resistor RL1 and the second load resistor RL2 may be coupled in parallel with each other, thereby reducing the resistance value between the first output node OP, the second output node ON, and the second power supply voltage node 102. When the resistance value between the first output node OP, the second output node ON, and the second power supply voltage node 102 is reduced, the amount of current discharged from the first output node OP and the second output node ON to the second power supply voltage node 102 may increase, and the voltage level of the first output node OP and the second output node ON may decrease.

[0027] When the voltage level of the first output signal OUTP transitions from a logic low level to a logic high level and the voltage level of the second output signal OUTN transitions from a logic high level to a logic low level, the first load control signal LC1 may also transition to a logic high level. When the first switching transistor 121 is turned on and the first load resistor RL1 and the second load resistor RL2 are coupled in parallel to each other, the voltage level of the first output signal OUTP may decrease, and the swing range of the first output signal OUTP and the second output signal OUTN may decrease. For example, the swing range of a signal may be the amplitude of the signal, or may be the voltage range between the maximum voltage level and the minimum voltage level of the signal swing. When the voltage level of the first output signal OUTP decreases, the time required for the first output signal OUTP to transition from a logic high level to a logic low level may be reduced, and the duration of the high level portion of the first output signal OUTP may be reduced. Furthermore, the time required for the second output signal OUTN to transition from a logic low level to a logic high level may be reduced, and the duration of the low level portion of the second output signal OUTN may be reduced. Therefore, the duty cycle of the first output signal OUTP may be reduced (“duty cycle <50%”), and the duty cycle of the second output signal OUTN may be increased.

[0028] To increase the duty cycle of the first output signal OUTP, the load control circuit 130 may output the second output signal OUTN as the second load control signal LC2 while maintaining the first load control signal LC1 at a logic low level ("L"). The second switching transistor 122 may be turned on during a period when the voltage level of the second load control signal LC2 is at a logic high level, that is, during a period when the voltage level of the second output signal OUTN is at a logic high level. When the second switching transistor 122 is turned on, the first load resistor RL1 and the second load resistor RL2 may be coupled in parallel with each other, thereby reducing the resistance value between the first output node OP, the second output node ON, and the second power supply voltage node 102. When the resistance value between the first output node OP, the second output node ON, and the second power supply voltage node 102 is reduced, the amount of current released from the first output node OP and the second output node ON to the second power supply voltage node 102 may increase, and the voltage level of the first output node OP and the second output node ON may decrease. When the voltage level of the first output signal OUTP transitions from a logic high level to a logic low level and the voltage level of the second output signal OUTN transitions from a logic low level to a logic high level, the second load control signal LC2 may also transition to a logic high level. When the second switching transistor 122 is turned on and couples the first load resistor RL1 and the second load resistor RL2 in parallel with each other, the voltage level of the second output signal OUTN may decrease, and the swing range of the second output signal OUTN and the first output signal OUTP may decrease. When the voltage level of the second output signal OUTN decreases, the time required for the second output signal OUTN to transition from a logic high level to a logic low level may decrease, and the duration of the high level portion of the second output signal OUTN may decrease. Furthermore, the time required for the first output signal OUTP to transition from a logic low level to a logic high level may decrease, and the duration of the low level portion of the first output signal OUTP may decrease. Therefore, the duty cycle of the first output signal OUTP may increase ("duty cycle > 50%"), and the duty cycle of the second output signal OUTN may decrease.

[0029] To advance the phase of the first output signal OUTP, the load control circuit 130 may output the first output signal OUTP as a first load control signal LC1 and may output the second output signal OUTN as a second load control signal LC2. The first switching transistor 121 may be turned on during a period when the voltage level of the first load control signal LC1 is at a logic high level, i.e., during a period when the voltage level of the first output signal OUTP is at a logic high level. The second switching transistor 122 may be turned on during a period when the voltage level of the second load control signal LC2 is at a logic high level, i.e., during a period when the voltage level of the second output signal OUTN is at a logic high level. Thus, the first load resistor RL1 and the second load resistor RL2 may be continuously coupled in parallel with each other. During the period when the voltage level of the first output signal OUTP is at a logic high level, the voltage level of the first output signal OUTP may decrease, and the swing range of the first output signal OUTP and the second output signal OUTN may decrease. During the period in which the voltage level of the second output signal OUTN is at a logic high level, the voltage level of the second output signal OUTN can be reduced, and the swing range of the second output signal OUTN and the first output signal OUTP can be reduced. Therefore, the time required for the first output signal OUTP to transition from a logic low level to a logic high level, and the time required for the first output signal OUTP to transition from a logic high level to a logic low level, can be reduced. Similarly, the time required for the second output signal OUTN to transition from a logic low level to a logic high level, and the time required for the second output signal OUTN to transition from a logic high level to a logic low level, can be reduced. When the transition time of the first output signal OUTP and the second output signal OUTN is reduced, the delay time required to generate the first output signal OUTP and the second output signal OUTN can be reduced ("delay reduction"), while the duty cycle of the first output signal OUTP and the second output signal OUTN is maintained ("duty cycle = 50%"). Therefore, the phase of the first output signal OUTP and the second output signal OUTN can be advanced.

[0030] Figure 3 is a diagram showing a configuration of a buffer circuit 300 according to an embodiment. The buffer circuit 300 may have the same configuration as Figure 1 The buffer circuit 100 has the same configuration as shown. Figure 1 and Figure 3 The same elements have the same reference numerals between the embodiments, and redundant descriptions of the same elements will be omitted. Figure 3, the buffer circuit 300 may further include a common-mode load circuit 350. The common-mode load circuit 350 may be coupled between the first output node OP, the second output node ON, and the load circuit 120. The common-mode load circuit 350 may operate as a load of the buffer circuit 300 based on the common-mode voltage of the buffer circuit 300. The common-mode voltage may have a voltage level corresponding to the middle of the voltage level difference between the first output signal OUTP and the second output signal OUTN.

[0031] Common-mode load circuit 350 may include a first transistor 351, a second transistor 352, a first resistor 353, and a second resistor 354. First transistor 351 may be coupled to the second output node ON and one end of the first load resistor RL1. Second transistor 352 may be coupled to the first output node OP and one end of the second load resistor RL2. When each of first input transistor 111 and second input transistor 112 is a P-channel MOS transistor, each of first transistor 351 and second transistor 352 may be an N-channel MOS transistor. First transistor 351 may be coupled to the second output node ON at its drain and to the one end of the first load resistor RL1 at its source. Second transistor 352 may be coupled to the first output node OP at its drain and to the one end of the second load resistor RL2 at its source. One end of first resistor 353 may be coupled to the second output node ON, and the other end of first resistor 353 may be commonly coupled to the gates of first transistor 351 and second transistor 352. One end of the second resistor 354 may be coupled to the first output node OP, and the other end of the second transistor 354 may be commonly coupled to gates of the first transistor 351 and the second transistor 352 .

[0032] Figure 4 1 is a diagram showing a configuration of a buffer circuit 400 according to an embodiment. The buffer circuit 400 may have Figure 1 The buffer circuit 100 is similarly configured as shown. Figure 1 and Figure 4 Buffer circuit 400 may vary the amount of adjustment to be made in the duty cycle of first output signal OUTP and the amount of adjustment to be made in the phase of first output signal OUTP. Buffer circuit 400 may include a load circuit 420 and a load control circuit 430. Figure 1The load circuit 120 and the load control circuit 130 can be modified to form a load circuit 420 and a load control circuit 430, respectively. The load circuit 420 can have various resistance values to change the amount of adjustment in the duty cycle and / or phase of the first output signal OUTP. The load control circuit 430 can generate a greater number of load control signals to variously change the resistance value of the load circuit 420.

[0033] Reference Figure 4 The load control circuit 430 may receive the first output signal OUTP and the second output signal OUTN, and may further receive the resistance control signal CON<1:2>. The resistance control signal CON<1:2> may be a digital code signal having a plurality of bits. The resistance control signal CON<1:2> may be generated based on any control signal utilized in the semiconductor device including the buffer circuit 400. The number of bits included in the resistance control signal CON<1:2> may be proportional to the number of switching transistors included in the load circuit 420. The load control circuit 430 may generate a first load control signal LC1 and a third load control signal LC3 based on the first output signal OUTP and the resistance control signal CON<1:2>. The load control circuit 430 may generate a second load control signal LC2 and a fourth load control signal LC4 based on the second output signal OUTN and the resistance control signal CON<1:2>.

[0034] In order to reduce the duty cycle of the first output signal OUTP, the load control circuit 430 can provide the first output signal OUTP as the first load control signal LC1 and the third load control signal LC3 while keeping the second load control signal LC2 and the fourth load control signal LC4 disabled. Each of the second load control signal LC2 and the fourth load control signal LC4 can be disabled to a logic low level. Based on the resistance control signal CON<1:2>, the load control circuit 430 can selectively output each of the first load control signal LC1 and the third load control signal LC3. The resistance control signal CON<1:2> can have various logic values to adjust the amount to be reduced in the duty cycle of the first output signal OUTP. For example, when all bits of the resistance control signal CON<1:2> have a logic high level, the load control circuit 430 can output both the first load control signal LC1 and the third load control signal LC3. When the first bit CON<1:2> in the resistance control signal CON<1:2> is <1> With logic high and the second bit CON <2> When the second bit CON in the resistance control signal CON<1:2> is at a logic low level, the load control circuit 430 may output the first load control signal LC1 and may not output the third load control signal LC3. <2> With logic high and the first bit CON <1> With a logic low level, the load control circuit 430 may output the third load control signal LC3 and may not output the first load control signal LC1 .

[0035] In order to increase the duty cycle of the first output signal OUTP, the load control circuit 430 can provide the second output signal OUTN as the second load control signal LC2 and the fourth load control signal LC4 while keeping the first load control signal LC1 and the third load control signal LC3 disabled. Each of the first load control signal LC1 and the third load control signal LC3 can be disabled to a logic low level. Based on the resistance control signal CON<1:2>, the load control circuit 430 can selectively output each of the second load control signal LC2 and the fourth load control signal LC4. The resistance control signal CON<1:2> can have various logic values to adjust the amount to be increased in the duty cycle of the first output signal OUTP. For example, when all bits of the resistance control signal CON<1:2> have a logic high level, the load control circuit 430 can output both the second load control signal LC2 and the fourth load control signal LC4. When the first bit CON<1:2> in the resistance control signal CON<1:2> is <1> With logic high and the second bit CON <2> When the second bit CON in the resistance control signal CON<1:2> is at a logic low level, the load control circuit 430 may output the second load control signal LC2 and may not output the fourth load control signal LC4. <2> With logic high and the first bit CON <1> With a logic low level, the load control circuit 430 may output the fourth load control signal LC4 and may not output the second load control signal LC2 .

[0036] In order to advance the phase of the first output signal OUTP, the load control circuit 430 can provide the first output signal OUTP as the first load control signal LC1 and the third load control signal LC3, and can provide the second output signal OUTN as the second load control signal LC2 and the fourth load control signal LC4. Based on the resistance control signal CON<1:2>, the load control circuit 430 can selectively output each of the first to fourth load control signals LC1 to LC4. The resistance control signal CON<1:2> can have various logic values to change the amount to be adjusted in the phase of the first output signal OUTP. For example, when all bits of the resistance control signal CON<1:2> have a logic high level, the load control circuit 430 can output all of the first to fourth load control signals LC1 to LC4. When the first bit CON<1:2> in the resistance control signal CON<1:2> is <1> With logic high and the second bit CON <2> When the resistance control signal CON<1:2> is at a logic low level, the load control circuit 430 may output the first load control signal LC1 and the second load control signal LC2, and may not output the third load control signal LC3 or the fourth load control signal LC4. <2> With logic high and the first bit CON <1> With a logic low level, the load control circuit 430 may output the third load control signal LC3 and the fourth load control signal LC4 , and may not output the first load control signal LC1 or the second load control signal LC2 .

[0037] The load circuit 420 can adjust resistance values differently between the first output node OP, the second output node ON, and the second power supply voltage node 102 based on first to fourth load control signals LC1 to LC4. The load circuit 420 may include a first load resistor RL1, a second load resistor RL2, a first switching transistor 421, a second switching transistor 422, a third switching transistor 423, and a fourth switching transistor 424. The first switching transistor 421 may be coupled between one end of the first load resistor RL1 and one end of the second load resistor RL2. The first switching transistor 421 may receive the first load control signal LC1. The second switching transistor 422 may be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The second switching transistor 422 may receive the second load control signal LC2. The third switching transistor 423 may be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The third switching transistor 423 may receive the third load control signal LC3. The fourth switch transistor 424 can be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The fourth switch transistor 424 can receive a fourth load control signal LC4. The on-resistance value of the third switch transistor 423 can be the same as or different from the on-resistance value of the first switch transistor 421. For example, the on-resistance value of a transistor can refer to the resistance value of the transistor when the transistor is on. The on-resistance value of the fourth switch transistor 424 can be the same as or different from the on-resistance value of the second switch transistor 422. For example, when the on-resistance value of the first switch transistor 421 is less than the on-resistance value of the third switch transistor 423, the load control circuit 430 can output both the first load control signal LC1 and the third load control signal LC3 to adjust the amount by which the resistance value of the load circuit 420 is to be reduced to a maximum value. The load control circuit 430 can output only the third load control signal LC3 to adjust the amount by which the resistance value of the load circuit 420 is to be reduced to a minimum value. The load control circuit 430 may output only the first load control signal LC1 to adjust the amount by which the resistance value of the load circuit 420 is to be reduced between the maximum value and the minimum value. Similarly, when the on-resistance value of the second switching transistor 422 is less than the on-resistance value of the fourth switching transistor 424, the load control circuit 430 may output both the second load control signal LC2 and the fourth load control signal LC4 to adjust the amount by which the resistance value of the load circuit 420 is to be reduced to the maximum value. The load control circuit 430 may output only the fourth load control signal LC4 to adjust the amount by which the resistance value of the load circuit 420 is to be reduced to the minimum value. The load control circuit 430 may output only the second load control signal LC2 to adjust the amount by which the resistance value of the load circuit 420 is to be reduced between the maximum value and the minimum value.

[0038] The load circuit 420 may further include a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first resistor R1 may be coupled in series to the first switching transistor 421. The second resistor R2 may be coupled in series to the second switching transistor 422. The third resistor R3 may be coupled in series to the third switching transistor 423. The fourth resistor R4 may be coupled in series to the fourth switching transistor 424. The resistance value of the third resistor R3 may be the same as or different from the resistance value of the first resistor R1. The resistance value of the fourth resistor R4 may be the same as or different from the resistance value of the second resistor R2. The first resistor R1 and the third resistor R3 may be coupled in series to the first switching transistor 421 and the third switching transistor 423, respectively, to vary the amount by which the buffer circuit 400 adjusts the duty cycle of the first output signal OUTP or the phase of the first output signal OUTP. The second resistor R2 and the fourth resistor R4 may be coupled in series to the second switching transistor 422 and the fourth switching transistor 424, respectively, to variously change the amount by which the buffer circuit 400 is to adjust the duty cycle of the first output signal OUTP or the phase of the first output signal OUTP.

[0039] The load circuit 420 may further include a third load resistor RL3 and a fourth load resistor RL4. The third load resistor RL3 may be coupled in series to the first load resistor RL1 between the second output node ON and the first load resistor RL1. The fourth load resistor RL4 may be coupled in series to the second load resistor RL2 between the first output node OP and the second load resistor RL2. The resistance value of the fourth load resistor RL4 may be substantially the same as the resistance value of the third load resistor RL3.

[0040] Figure 5 is a diagram showing a configuration of a buffer circuit 500 according to an embodiment. The buffer circuit 500 may have Figure 1 The buffer circuit 100 is similarly configured as shown in FIG. Figure 1 and Figure 5 Like elements have like reference numerals between the embodiments. Figure 5, the buffer circuit 500 can adjust the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN by adjusting the resistance value of the load. The buffer circuit 500 can adjust the duty cycle and / or phase of the first output signal OUTP and / or the second output signal OUTN by adjusting the amount of current provided to the node that outputs the first output signal OUTP and / or the second output signal OUTN. The buffer circuit 500 may include a first input transistor 511, a second input transistor 512, a load circuit 520, and a load control circuit 530. Each of the first input signal INP and the second input signal INN may have various swing ranges according to the common mode. The first input signal INP and the second input signal INN may swing within a range of higher voltage levels or within a range of lower voltage levels. When the signal provided to the gate of the N-channel MOS transistor has a higher voltage level, the N-channel MOS transistor may respond well. When the signal provided to the gate of the P-channel MOS transistor has a lower voltage level, the P-channel MOS transistor may respond well. Because each of the first input transistor 111 and the second input transistor 112 is a P-channel MOS transistor, Figure 1 The buffer circuit 100 can be adapted to receive a first input signal INP and a second input signal INN that swing within a relatively low voltage level range. Each of the first input transistor 511 and the second input transistor 512 of the buffer circuit 500 can be an N-channel MOS transistor. Therefore, the buffer circuit 500 can be adapted to receive a first input signal INP and a second input signal INN that swing within a relatively high voltage level range. The first input transistor 511 can be coupled between the second output node ON and the second power supply voltage node 502. The first input transistor 511 can receive the first input signal INP. The second input transistor 512 can be coupled between the first output node OP and the second power supply voltage node 502. The second input transistor 512 can receive the second input signal INN.

[0041] The load circuit 520 may be coupled between the first power supply voltage node 501, the first output node OP, and the second output node ON. The load circuit 520 may include a first load resistor RL1, a second load resistor RL2, a first switching transistor 521, and a second switching transistor 522. Each of the first switching transistor 521 and the second switching transistor 522 may be an N-channel MOS transistor. The first switching transistor 521 may be coupled between one end of the first load resistor RL1 and one end of the second load resistor RL2. The first switching transistor 521 may receive a first load control signal LC11. The second switching transistor 522 may be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The second switching transistor 522 may receive a second load control signal LC12.

[0042] The load circuit 520 may further include a third load resistor RL3 and a fourth load resistor RL4. The third load resistor RL3 may be coupled in series to the first load resistor RL1 between the second output node ON and the first load resistor RL1. The fourth load resistor RL4 may be coupled in series to the second load resistor RL2 between the first output node OP and the second load resistor RL2. The resistance value of the fourth load resistor RL4 may be substantially the same as the resistance value of the third load resistor RL3.

[0043] The load control circuit 530 can generate a first load control signal LC11 and a second load control signal LC12 based on the first output signal OUTP and the second output signal OUTN. The load control circuit 530 can provide the first output signal OUTP as the first load control signal LC11 and the second output signal OUTN as the second load control signal LC12. To increase the duty cycle of the first output signal OUTP, the load control circuit 530 can provide the first output signal OUTP as the first load control signal LC11 while keeping the second load control signal LC12 disabled. The second load control signal LC12 can be disabled to a logic high level. To reduce the duty cycle of the first output signal OUTP, the load control circuit 530 can provide the second output signal OUTN as the second load control signal LC12 while keeping the first load control signal LC11 disabled. The first load control signal LC11 can be disabled to a logic high level. To advance the phase of the first output signal OUTP, the load control circuit 530 can generate the first load control signal LC11 based on the first output signal OUTP and generate the second load control signal LC12 based on the second output signal OUTN.

[0044] The buffer circuit 500 may further include an enable transistor 540. The enable transistor 540 may be coupled between the first input transistor 511, the second input transistor 512, and the second power supply voltage node 502. The enable transistor 540 may receive an enable signal ENB. The enable transistor 540 may be an N-channel MOS transistor. When the enable signal ENB is enabled to a logic high level, the enable transistor 540 may couple the first input transistor 511 and the second input transistor 512 to the second power supply voltage node 502, thereby forming a current path from the first input transistor 511 and the second input transistor 512 to the second power supply voltage node 502, respectively.

[0045] The operation of the buffer circuit 500 according to an embodiment will be described below. To increase the duty cycle of the first output signal OUTP, the load control circuit 530 may output the first output signal OUTP as the first load control signal LC11 while maintaining the second load control signal LC12 disabled. The first switching transistor 521 may be turned on during a period when the voltage level of the first load control signal LC11 is at a logic low level, i.e., during a period when the voltage level of the first output signal OUTP is at a logic low level. When the first switching transistor 521 is turned on, the first load resistor RL1 and the second load resistor RL2 may be coupled in parallel with each other, thereby reducing the resistance value between the first power supply voltage node 501, the first output node OP, and the second output node ON. When the resistance value between the first power supply voltage node 501, the first output node OP, and the second output node ON decreases, the amount of current supplied from the first power supply voltage node 501 to the first output node OP and the second output node ON may increase, and the voltage level of the first output node OP and the second output node ON may increase. When the voltage level of the first output signal OUTP transitions from a logic high level to a logic low level and the voltage level of the second output signal OUTN transitions from a logic low level to a logic high level, the first load control signal LC11 may also transition to a logic low level. When the first switching transistor 521 is turned on and couples the first load resistor RL1 and the second load resistor RL2 in parallel with each other, the voltage level of the first output signal OUTP may increase, and the swing range of the first output signal OUTP and the second output signal OUTN may decrease. When the voltage level of the first output signal OUTP increases, the time required for the first output signal OUTP to transition from a logic low level to a logic high level may decrease, and the duration of the high level portion of the first output signal OUTP may increase. Furthermore, the time required for the second output signal OUTN to transition from a logic high level to a logic low level may decrease, and the duration of the high level portion of the second output signal OUTN may decrease. Therefore, the duty cycle of the first output signal OUTP may increase, while the duty cycle of the second output signal OUTN may decrease.

[0046] To reduce the duty cycle of the first output signal OUTP, the load control circuit 530 may output the second output signal OUTN as the second load control signal LC12 while maintaining the first load control signal LC11 disabled. The second switching transistor 522 may be turned on during a period when the voltage level of the second load control signal LC12 is at a logic low level, i.e., when the voltage level of the second output signal OUTN is at a logic low level. When the second switching transistor 522 is turned on, the first load resistor RL1 and the second load resistor RL2 may be coupled in parallel with each other, thereby reducing the resistance value between the first power supply voltage node 501, the first output node OP, and the second output node ON. When the resistance value between the first power supply voltage node 501, the first output node OP, and the second output node ON decreases, the amount of current supplied from the first power supply voltage node 501 to the first output node OP and the second output node ON may increase, and the voltage level of the first output node OP and the second output node ON may increase. When the voltage level of the first output signal OUTP transitions from a logic low level to a logic high level and the voltage level of the second output signal OUTN transitions from a logic high level to a logic low level, the second load control signal LC12 may also transition to a logic low level. When the second switching transistor 522 is turned on and couples the first load resistor RL1 and the second load resistor RL2 in parallel with each other, the voltage level of the second output signal OUTN may increase, and the swing range of the second output signal OUTN and the first output signal OUTP may decrease. When the voltage level of the second output signal OUTN increases, the time required for the second output signal OUTN to transition from a logic low level to a logic high level may decrease, and the duration of the high level portion of the second output signal OUTN may increase. Furthermore, the time required for the first output signal OUTP to transition from a logic high level to a logic low level may decrease, and the duration of the high level portion of the first output signal OUTP may decrease. Therefore, the duty cycle of the first output signal OUTP may decrease, while the duty cycle of the second output signal OUTN may increase.

[0047] To advance the phase of the first output signal OUTP, the load control circuit 530 can output the first output signal OUTP as the first load control signal LC11 and can output the second output signal OUTN as the second load control signal LC12. The first switching transistor 521 can be turned on during a period when the voltage level of the first load control signal LC11 is at a logic low level, that is, during a period when the voltage level of the first output signal OUTP is at a logic low level. The second switching transistor 522 can be turned on during a period when the voltage level of the second load control signal LC12 is at a logic low level, that is, during a period when the voltage level of the second output signal OUTN is at a logic low level. Therefore, based on the first load control signal LC11 and the second load control signal LC12, the first load resistor RL1 and the second load resistor RL2 can be continuously coupled in parallel with each other. During the period when the voltage level of the first output signal OUTP is at a logic low level, the voltage level of the first output signal OUTP can increase, and the swing range of the first output signal OUTP and the second output signal OUTN can be reduced. During the time period when the voltage level of the second output signal OUTN is at a logic low level, the voltage level of the second output signal OUTN can increase and the swing range of the second output signal OUTN and the first output signal OUTP can be reduced. Therefore, the time required for the first output signal OUTP to transition from a logic low level to a logic high level and the time required for the first output signal OUTP to transition from a logic high level to a logic low level can be reduced. In a similar manner, the time required for the second output signal OUTN to transition from a logic low level to a logic high level and the time required for the second output signal OUTN to transition from a logic high level to a logic low level can be reduced. When the transition time of the first output signal OUTP and the second output signal OUTN is reduced, the time point of outputting the first output signal OUTP and the second output signal OUTN can be advanced, and the delay time required to generate the first output signal OUTP and the second output signal OUTN can be reduced.

[0048] Figure 6 is a diagram showing a configuration of a buffer circuit 600 according to an embodiment. The buffer circuit 600 may have the same configuration as Figure 5 The buffer circuit 500 has the same configuration as shown. Figure 5 and Figure 6 The same elements have the same reference numerals between the embodiments, and redundant descriptions of the same elements will be omitted. Figure 6, the buffer circuit 600 may additionally include a common-mode load circuit 650. The common-mode load circuit 650 may be coupled between the first output node OP, the second output node ON, and the load circuit 520. The common-mode load circuit 650 may operate as a load for the buffer circuit 600 based on a common-mode voltage of the buffer circuit 600. The common-mode voltage may have a voltage level corresponding to a midpoint between the first output signal OUTP and the second output signal OUTN.

[0049] The common-mode load circuit 650 may include a first transistor 651, a second transistor 652, a first resistor 653, and a second resistor 654. The first transistor 651 may be coupled to the second output node ON and one end of the first load resistor RL1. The second transistor 652 may be coupled to the first output node OP and one end of the second load resistor RL2. Each of the first transistor 651 and the second transistor 652 may be a P-channel MOS transistor. The first transistor 651 may be coupled to the second output node ON at its drain and to the one end of the first load resistor RL1 at its source. The second transistor 652 may be coupled to the first output node OP at its drain and to the one end of the second load resistor RL2 at its source. One end of the first resistor 653 may be coupled to the second output node ON, and the other end of the first resistor 653 may be commonly coupled to the gates of the first transistor 651 and the second transistor 652. One end of the second resistor 654 may be coupled to the first output node OP, and the other end of the second resistor 654 may be commonly coupled to gates of the first transistor 651 and the second transistor 652 .

[0050] Figure 7 700 according to an embodiment. Figure 5 The buffer circuit 500 is similarly configured as shown in FIG. Figure 5 and Figure 7 The same elements have the same reference numerals between the embodiments, and redundant descriptions of the same elements will be omitted. Figure 7 The load control circuit 730 may receive the first output signal OUTP and the second output signal OUTN, and may further receive the resistance control signals CON<1:2>. The load control circuit 730 may generate a first load control signal LC11 and a third load control signal LC13 based on the first output signal OUTP and the resistance control signals CON<1:2>. The load control circuit 730 may generate a second load control signal LC12 and a fourth load control signal LC14 based on the second output signal OUTN and the resistance control signals CON<1:2>.

[0051] To increase the duty cycle of the first output signal OUTP, the load control circuit 730 may provide the first output signal OUTP as the first load control signal LC11 and the third load control signal LC13 while keeping the second load control signal LC12 and the fourth load control signal LC14 disabled. Based on the resistance control signals CON<1:2>, the load control circuit 730 may selectively output each of the first load control signal LC11 and the third load control signal LC13. To decrease the duty cycle of the first output signal OUTP, the load control circuit 730 may provide the second output signal OUTN as the second load control signal LC12 and the fourth load control signal LC14 while keeping the first load control signal LC11 and the third load control signal LC13 disabled. Based on the resistance control signals CON<1:2>, the load control circuit 730 may selectively output each of the second load control signal LC12 and the fourth load control signal LC14. To advance the phase of the first output signal OUTP, the load control circuit 730 can provide the first output signal OUTP as first and third load control signals LC11 and LC13, and can provide the second output signal OUTN as second and fourth load control signals LC12 and LC14. Based on the resistance control signals CON<1:2>, the load control circuit 730 can selectively output each of the first to fourth load control signals LC11 to LC14.

[0052] The load circuit 720 can adjust the resistance values between the first output node OP, the second output node ON, and the second power supply voltage node 502 differently based on first to fourth load control signals LC11 to LC14. The load circuit 720 may include a first load resistor RL1, a second load resistor RL2, a first switching transistor 721, a second switching transistor 722, a third switching transistor 723, and a fourth switching transistor 724. The first switching transistor 721 may be coupled between one end of the first load resistor RL1 and one end of the second load resistor RL2. The first switching transistor 721 may receive the first load control signal LC11. The second switching transistor 722 may be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The second switching transistor 722 may receive the second load control signal LC12. The third switching transistor 723 may be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The third switching transistor 723 may receive the third load control signal LC13. The fourth switch transistor 724 can be coupled between the one end of the first load resistor RL1 and the one end of the second load resistor RL2. The fourth switch transistor 724 can receive a fourth load control signal LC14. The on-resistance value of the third switch transistor 723 can be the same as or different from the on-resistance value of the first switch transistor 721. The on-resistance value of the fourth switch transistor 724 can be the same as or different from the on-resistance value of the second switch transistor 722. For example, when the on-resistance value of the first switch transistor 721 is less than the on-resistance value of the third switch transistor 723, the load control circuit 730 can output both the first load control signal LC11 and the third load control signal LC13 to adjust the amount by which the resistance value of the load circuit 720 is to be reduced to a maximum value. The load control circuit 730 can output only the third load control signal LC13 to adjust the amount by which the resistance value of the load circuit 720 is to be reduced to a minimum value. The load control circuit 730 may output only the first load control signal LC11 to adjust the amount by which the resistance value of the load circuit 720 is to be reduced between the maximum value and the minimum value. Similarly, when the on-resistance value of the second switching transistor 722 is less than the on-resistance value of the fourth switching transistor 724, the load control circuit 730 may output both the second load control signal LC12 and the fourth load control signal LC14 to adjust the amount by which the resistance value of the load circuit 720 is to be reduced to the maximum value. The load control circuit 730 may output only the fourth load control signal LC14 to adjust the amount by which the resistance value of the load circuit 720 is to be reduced to the minimum value. The load control circuit 730 may output only the second load control signal LC12 to adjust the amount by which the resistance value of the load circuit 720 is to be reduced between the maximum value and the minimum value.

[0053] The load circuit 720 may further include a first resistor R11, a second resistor R12, a third resistor R13, and a fourth resistor R14. The first resistor R11 may be coupled in series to the first switching transistor 721. The second resistor R12 may be coupled in series to the second switching transistor 722. The third resistor R13 may be coupled in series to the third switching transistor 723. The fourth resistor R14 may be coupled in series to the fourth switching transistor 724. The resistance value of the third resistor R13 may be the same as or different from the resistance value of the first resistor R11. The resistance value of the fourth resistor R14 may be the same as or different from the resistance value of the second resistor R12. The first resistor R11 and the third resistor R13 may be coupled in series to the first switching transistor 721 and the third switching transistor 723, respectively, to vary the amount by which the buffer circuit 700 adjusts the duty cycle of the first output signal OUTP or the phase of the first output signal OUTP. The second resistor R12 and the fourth resistor R14 may be coupled in series to the second switching transistor 722 and the fourth switching transistor 724, respectively, to variously change the amount by which the buffer circuit 700 is to adjust the duty cycle of the first output signal OUTP or the amount by which the buffer circuit 700 is to adjust the phase of the first output signal OUTP.

[0054] The load circuit 720 may further include a third load resistor RL3 and a fourth load resistor RL4. The third load resistor RL3 may be coupled in series to the first load resistor RL1 between the second output node ON and the first load resistor RL1. The fourth load resistor RL4 may be coupled in series to the second load resistor RL2 between the first output node OP and the second load resistor RL2. The resistance value of the fourth load resistor RL4 may be substantially the same as the resistance value of the third load resistor RL3.

[0055] Although certain embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely exemplary. Therefore, the snubber circuit should not be limited based on the described embodiments. Instead, the snubber circuit described herein should be limited only in light of the following claims taken in conjunction with the above description and accompanying drawings.

Claims

1. A buffer circuit comprising: a first input transistor coupled between a first power supply voltage node and a second output node and configured to change a voltage level of the second output node based on a first input signal; a second input transistor coupled between the first power supply voltage node and a first output node and configured to change a voltage level of the first output node based on a second input signal; a first load resistor coupled between the second output node and a second power supply voltage node; a second load resistor coupled between the first output node and a second power supply voltage node; and At least one switching transistor is configured to couple the first load resistor and the second load resistor in parallel with each other based on at least one of a first output signal from the first output node and a second output signal from the second output node.

2. The buffer circuit according to claim 1, wherein The buffer circuit is configured to reduce a duty ratio of the first output signal output from the first output node by turning on the at least one switching transistor during a period in which a voltage level of the first output node is a logic high level.

3. The buffer circuit according to claim 1, wherein The buffer circuit is configured to increase a duty ratio of the first output signal output from the first output node by turning on the at least one switching transistor during a period in which a voltage level of the second output node is a logic high level.

4. The buffer circuit according to claim 1, wherein The buffer circuit is configured to advance the phase of the first output signal output from the first output node by turning on the at least one switching transistor during a period when the voltage level of the first output node is a logic high level and a period when the voltage level of the second output node is a logic high level.

5. A buffer circuit comprising: a first input transistor coupled between a first power supply voltage node and a second output node and configured to change a voltage level of the second output node based on a first input signal; a second input transistor coupled between the first power supply voltage node and a first output node and configured to change a voltage level of the first output node based on a second input signal; a load control circuit configured to generate at least one load control signal based on a first output signal output from the first output node and a second output signal output from the second output node; a first load resistor coupled between the second output node and a second power supply voltage node; a second load resistor coupled between the first output node and a second power supply voltage node; and At least one switching transistor is configured to couple the first load resistor and the second load resistor in parallel with each other based on the at least one load control signal.

6. The buffer circuit according to claim 5, in, The load control circuit is configured to provide the first output signal as a first load control signal, and The at least one switching transistor couples the first load resistor and the second load resistor in parallel with each other based on the first load control signal.

7. The buffer circuit according to claim 5, in, The load control circuit is configured to provide the second output signal as a second load control signal, and The at least one switching transistor couples the first load resistor and the second load resistor in parallel with each other based on the second load control signal.

8. The buffer circuit according to claim 5, in, The load control circuit is configured to provide the first output signal as a first load control signal and to provide the second output signal as a second load control signal, and The at least one switching transistor couples the first load resistor and the second load resistor in parallel with each other based on the first load control signal and the second load control signal.

9. The buffer circuit according to claim 5, wherein The buffer circuit further includes: a third load resistor coupled in series to the first load resistor between the first load resistor and the second output node; and A fourth load resistor is coupled in series to the second load resistor between the second load resistor and the first output node.

10. The buffer circuit according to claim 5, wherein The at least one switching transistor comprises: a first switching transistor configured to couple the first load resistor and the second load resistor in parallel with each other based on a first load control signal; and a second switching transistor configured to couple the first load resistor and the second load resistor in parallel with each other based on a second load control signal.

11. The buffer circuit according to claim 10, wherein: The buffer circuit further includes: a third load resistor coupled in series to the first load resistor between the first load resistor and the second output node; and A fourth load resistor is coupled in series to the second load resistor between the second load resistor and the first output node.

12. The buffer circuit according to claim 5, in, The load control circuit is configured to further receive a resistance control signal, is configured to generate a first load control signal and a third load control signal based on the first output signal and the resistance control signal, and is configured to generate a second load control signal and a fourth load control signal based on the second output signal and the resistance control signal. Wherein, the at least one switching transistor comprises: a first switching transistor configured to couple the first load resistor and the second load resistor in parallel with each other based on the first load control signal; a second switching transistor configured to couple the first load resistor and the second load resistor in parallel with each other based on the second load control signal; a third switching transistor configured to couple the first load resistor and the second load resistor in parallel with each other based on the third load control signal; and a fourth switching transistor configured to couple the first load resistor and the second load resistor in parallel with each other based on the fourth load control signal.

13. The buffer circuit according to claim 12, wherein: An on-resistance value of the first switch transistor is different from an on-resistance value of the third switch transistor.

14. The buffer circuit according to claim 12, wherein: An on-resistance value of the second switch transistor is different from an on-resistance value of the fourth switch transistor.

15. The buffer circuit according to claim 12, wherein The buffer circuit further includes: a first resistor coupled in series to the first switch transistor; a second resistor coupled in series to the second switch transistor; a third resistor coupled in series to the third switch transistor; and A fourth resistor is coupled in series to the fourth switch transistor.

16. The buffer circuit according to claim 12, wherein: The buffer circuit further includes: a third load resistor coupled in series to the first load resistor between the first load resistor and the second output node; and A fourth load resistor is coupled in series to the second load resistor between the second load resistor and the first output node.

17. The buffer circuit according to claim 5, further comprising: A common-mode load circuit is coupled between the first output node, the second output node, and the load circuit.

18. A buffer circuit comprising: a first input transistor coupled between a first power supply voltage node and a second output node and configured to change a voltage level of the second output node based on a first input signal; a second input transistor coupled between the first power supply voltage node and a first output node and configured to change a voltage level of the first output node based on a second input signal; a load control circuit configured to generate a first load control signal and a second load control signal based on a first output signal output from the first output node and a second output signal output from the second output node; a first load resistor including one end coupled to the second output node and another end coupled to the second power supply voltage node; a second load resistor including one end coupled to the first output node and another end coupled to the second power supply voltage node; a first switching transistor configured to couple the one end of the first load resistor and the one end of the second load resistor to each other based on the first load control signal; and a second switching transistor configured to couple the one end of the first load resistor and the one end of the second load resistor to each other based on the second load control signal.

19. The buffer circuit according to claim 18, wherein The load control circuit is configured to provide the first output signal as the first load control signal and disable the second load control signal to adjust a duty cycle of the first output signal.

20. The buffer circuit according to claim 18, wherein The load control circuit is configured to provide the second output signal as the second load control signal and disable the first load control signal to adjust a duty cycle of the first output signal.

21. The buffer circuit according to claim 18, wherein The load control circuit is configured to provide the first output signal as the first load control signal and to provide the second output signal as the second load control signal so that the phase of the first output signal is advanced.

22. The buffer circuit according to claim 18, further comprising: a third load resistor coupled in series to the first load resistor between the first load resistor and the second output node; and A fourth load resistor is coupled in series to the second load resistor between the second load resistor and the first output node.

23. The buffer circuit according to claim 18, wherein The load control circuit is configured to further receive a resistance control signal, is configured to generate the first load control signal and a third load control signal based on the first output signal and the resistance control signal, and is configured to generate the second load control signal and a fourth load control signal based on the second output signal and the resistance control signal.

24. The buffer circuit according to claim 23, further comprising: a third switching transistor configured to couple the one end of the first load resistor and the one end of the second load resistor to each other based on the third load control signal; and a fourth switching transistor configured to couple the one end of the first load resistor and the one end of the second load resistor to each other based on the fourth load control signal.

25. The buffer circuit according to claim 24, wherein An on-resistance value of the third switch transistor is different from an on-resistance value of the first switch transistor.

26. The buffer circuit according to claim 24, wherein An on-resistance value of the fourth switch transistor is different from an on-resistance value of the second switch transistor.

27. The buffer circuit according to claim 24, further comprising: a first resistor coupled in series to the first switch transistor; a second resistor coupled in series to the second switch transistor; a third resistor coupled in series to the third switch transistor; and A fourth resistor is coupled in series to the fourth switch transistor.

28. The buffer circuit according to claim 18, further comprising: A common-mode load circuit is coupled between the first output node, the second output node, the one end of the first load resistor, and the one end of the second load resistor.

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