Method and apparatus for self-aligned MRAM top contact with package topography assistance

Abstract

A method for forming an MRAM device, comprising: forming an MTJ (202) on an interconnect (106) embedded in a first dielectric (102); depositing an encapsulation layer (204) over the MTJ (202); burying the MTJ (202) in a second dielectric (206); patterning a trench (302') in the second dielectric (206) over the MTJ, thereby exposing the encapsulation layer (204) over the top of the MTJ (202), This forms a topography at the bottom of the trench (302'); forms a metal line (904) in the trench (302') above the topography; recesses the metal line (904) which separates the metal line (904) into segments (904a, 904b) separated by exposed peaks of the encapsulation layer; recesses the exposed peaks of the encapsulation layer (204) to form a recess at the top of the MTJ (202); and forms a self-aligned contact (1202) in the recess. An MRAM device is also provided.

Description

Technical Field

[0001] The present invention relates to magnetic random access memory (MRAM) devices, and more particularly to package topography-assisted techniques for forming self-aligned top contacts in MRAM devices. Background Art

[0002] Magnetic random access memory (MRAM) is a type of non-volatile memory that stores data in a magnetic storage element called a magnetic tunnel junction (MTJ). Each MTJ includes at least one 'free' magnetic layer separated from at least one 'fixed' magnetic layer by a tunnel barrier. The resistance of the MTJ changes depending on the magnetization orientation of the free layer to the fixed layer. The magnetization of the free layer can be switched (relative to the fixed layer) in order to write data to the device.

[0003] During the manufacture of MRAM devices, a top contact is formed to access the MTJ. However, there may be some significant manufacturing challenges in forming the top contact in advanced technology nodes. For example, metal line pullback (also known as line end shortening) may undesirably cause misalignment at the end of the line. For a general discussion of line pullback / line end shortening, see, for example, Stewart et al., "Mechanistic Conference of Line End Shortening" (August 2001) (9 pages) in SPIE 4345, Advances in Resist Technology and Processing XVIII. In some instances, line pullback may cause the MTJ to not contact the metal line above. As such, conventional processes avoid placing contacts too close to the ends of metal lines in order to avoid any misalignment caused by pullback. However, doing so imposes strict restrictions on the design.

[0004] Therefore, techniques for contact formation that eliminate reliance on wire pullback would be desirable. Summary of the invention

[0005] The present invention provides packaging morphology-assisted technology for forming self-aligned top contacts in magnetic random access memory (MRAM) devices. In one aspect of the present invention, a method for forming an MRAM device is provided. The method includes: forming a magnetic tunnel junction (MTJ) on an interconnect embedded in a first dielectric; depositing a packaging layer above the MTJ; burying the MTJ in a second dielectric; patterning a groove in the second dielectric above the MTJ, thereby exposing the packaging layer above the top of the MTJ, which creates a topography at the bottom of the groove; forming a metal line in the groove above the topography at the bottom of the groove; recessing the metal line down to the packaging layer and exposing the packaging layer, wherein the recess separates the metal line into segments separated by exposed peaks of the packaging layer above the MTJ; recessing the exposed peaks of the packaging layer to form a recess between the segments of the metal line at the top of the MTJ; and forming a contact self-aligned with the top of the MTJ in the recess.

[0006] In another aspect of the present invention, an MRAM device is provided. The MRAM device includes: an MTJ, the MTJ is arranged on an interconnect embedded in a first dielectric; an encapsulation layer, the encapsulation layer is arranged above the MTJ; a second dielectric, the second dielectric surrounds the MTJ; a recess in the encapsulation layer between segments of a metal line at the top of the MTJ, wherein the segment of the metal line is separated from the second dielectric by a barrier layer; and a contact formed in the recess, the contact being self-aligned with the top of the MTJ, wherein the contact is in direct contact with the MTJ, and wherein the contact is connected to the segment of the metal line through the barrier layer.

[0007] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by referring to the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view showing that an interconnect with a capping layer has been formed in a dielectric on an underlying substrate in accordance with an embodiment of the present invention;

[0009] Figure 2 is a cross-sectional view showing that a magnetic tunnel junction (MTJ) has been formed on an interconnect over a capping layer, a conformal encapsulation layer has been deposited over the MTJ, and a second dielectric (e.g., an interlayer dielectric (ILD)) has been deposited over / around the MTJ in accordance with an embodiment of the present invention;

[0010] Figure 3is a cross-sectional view showing that a trench has been patterned in a second dielectric over the MTJ to expose the (encapsulated) MTJ within the trench, which creates a topography at the bottom of the trench, in accordance with an embodiment of the present invention;

[0011] Figure 4 is a cross-sectional view showing that a conformal barrier layer has been deposited into and lined the trench and the trench has been filled with metal to form a metal line over the barrier layer in the trench over the MTJ in accordance with an embodiment of the present invention;

[0012] Figure 5 is a cross-sectional view showing that a metal line has been recessed down into the encapsulation layer, which separates the metal line into segments separated by exposed peaks of the encapsulation layer at the top of the MTJ, in accordance with an embodiment of the present invention;

[0013] Figure 6 is a cross-sectional view showing that the exposed peak of the encapsulation layer has been etched to form a recess at the top of the MTJ according to an embodiment of the present invention;

[0014] Figure 7 is a cross-sectional view showing that contacts have been formed in recesses on each top portion of the MTJ according to one embodiment of the present invention;

[0015] Figure 8 yes Figure 2 a cross-sectional view thereafter showing that an offset trench according to an alternative embodiment has been patterned in the second dielectric above the MTJ, thereby exposing the (encapsulated) MTJ within the trench, which produces a topography at the bottom of the trench according to an embodiment of the present invention;

[0016] Fig. 9 is a cross-sectional view showing that a conformal barrier layer has been deposited into and lined the trench and the trench has been filled with metal to form a metal line over the barrier layer in the trench over the MTJ in accordance with an embodiment of the present invention;

[0017] Fig.10 is a cross-sectional view showing that a metal line has been recessed down to the encapsulation layer, which separates the metal line into segments separated by exposed peaks of the encapsulation layer at the top of the MTJ in accordance with an embodiment of the present invention;

[0018] Fig.11 is a cross-sectional view showing that the exposed peak of the encapsulation layer has been etched to form a recess at the top of the MTJ according to an embodiment of the present invention;

[0019] Fig.12 is a cross-sectional view showing that contacts have been formed in recesses on each top of the MTJ in accordance with one embodiment of the present invention; and

[0020] Fig.13is a cross-sectional view illustrating an exemplary MTJ according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] As highlighted above, in advanced technology nodes, line end pullback and overlay can result in a magnetic tunnel junction (MTJ) of a magnetic random access memory (MRAM) device not making contact with an overlying metal line. Advantageously, techniques are provided herein for forming self-aligned line end contacts that eliminate the reliance on overlying line pullback and overlay, thereby enabling metallized contact between the top of the MTJ and an overlying metal level.

[0022] As will be described in detail below, the MTJs are packaged in an insulator. The topography of those packaged MTJs is then used to self-align contacts to the top of the MTJs without requiring direct interaction between the MTJs and metal lines.

[0023] See now Figure 1-Figure 7 An exemplary method for forming an MRAM device is described below. Figure 1 As shown, interconnect 106 is formed in dielectric 102. According to an exemplary embodiment, interconnect 106 includes a metal line, a conductive via, or a combination thereof. It should be noted that interconnect 106 represents the metal level MX in the design, and other device elements (not shown) may already exist below dielectric 102, other device elements such as transistors, resistors, capacitors, etc. formed on the underlying substrate 101.

[0024] According to an exemplary embodiment, substrate 101 is a bulk semiconductor wafer, such as bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe), and / or bulk III-V semiconductor wafer. Alternatively, substrate 102 may be a semiconductor on insulator (SOI) wafer. The SOI wafer includes an SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide, it is referred to herein as a buried oxide or BOX. The SOI layer may include any suitable semiconductor, such as Si, Ge, SiGe, and / or a III-V semiconductor.

[0025] Suitable dielectrics 102 include, but are not limited to, oxide materials, such as silicon oxide (SiOx) and / or organosilicate glass (SiCOH) and / or ultra-low-κ interlayer dielectric (ULK-ILD) materials, for example, having a dielectric constant κ of less than 2.7. By comparison, silicon dioxide (SiO2) has a dielectric constant κ value of 3.9. Suitable ultra-low-κ dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH).

[0026] Standard metallization techniques are used to form interconnects 106 embedded in dielectric 102. For example, features such as vias and / or trenches (for metal lines) are first patterned in dielectric 102. These features are then filled with a metal or metals to form interconnects 106. Suitable metals include, but are not limited to, copper (Cu) and / or cobalt (Co). Prior to placing the metal in the feature, a conformal barrier layer 104 is deposited into the feature and lines the feature. See Figure 1 By way of example only, suitable barrier materials include, but are not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), and / or tantalum nitride (TaN). Barrier layer 104 separates interconnect 106 from dielectric 102. When the metal is Cu, embodiments are also contemplated herein in which a thin (e.g., from about 1 nanometer (nm) to about 3 nm) Cu seed layer (not shown) is deposited onto barrier layer 104 using, for example, evaporation, sputtering, etc. Cu is then plated onto the seed layer to form interconnect 106.

[0027] A planarization process such as chemical mechanical polishing (CMP) is used to remove the capping layer (if any) from the metal fill. Thus, interconnect 106 is coplanar with the top surface of dielectric 102. Figure 1 Then, a capping layer 108 is formed on the interconnect 106. Suitable materials for the capping layer 108 include, but are not limited to, ruthenium (Ru), Ta, TaN, Ti, TiN, and / or tungsten (W).

[0028] Then, MTJ 202 is formed on interconnect 106 (above capping layer 108). Figure 2 Each MTJ 202 generally includes a stack of magnetic metal layers separated by tunnel barriers. The specific configuration of the stack may vary depending on the application at hand. According to an exemplary embodiment, the layers of the MTJ 202 are sequentially deposited as a stack on the dielectric 102 and the interconnect 106 using a process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The stack of layers is then patterned into Figure 2 , each (eg, pillar-shaped) MTJ 202 is shown in FIG. 1 , and the MTJ 202 is disposed on the interconnect 106 .

[0029] The specific composition and configuration of the MTJ stack may vary depending on the application at hand. For example, by way of example only, suitable materials for the magnetic metal layer include, but are not limited to, cobalt (Co), iron (Fe), nickel (Ni), Co alloys, Fe alloys, and / or Ni alloys. Suitable materials for the tunnel barrier include, but are not limited to, aluminum (Al) and / or magnesium (Mg) oxides. According to an exemplary embodiment, the tunnel barrier has a thickness from about 1 nanometer (nm) to about 3 nm and ranges therebetween. Fig.13 An exemplary MTJ element is described with reference to the description of FIG.

[0030] In one exemplary embodiment, the direction of the magnetization of the magnetic metal layer on one side of the tunnel barrier is fixed, while the direction of the magnetization of the magnetic metal layer on the other side of the tunnel barrier is free and can be switched by an applied current tunneling through the tunnel barrier. Based on the orientation of the magnetization of the free magnetic metal layer relative to the magnetization of the fixed magnetic metal layer, data is stored in the MTJ 202. The resistance state of the MTJ 202 changes based on the relative orientation of the magnetization of the fixed layer and the free layer.

[0031] A conformal encapsulation layer 204 is deposited over the MTJs 202 (and portions of the dielectric 102 / metal lines 106 between the MTJs 202). Figure 2 . Suitable materials for encapsulation layer 204 include, but are not limited to, electrical insulators such as silicon nitride (SiN). Encapsulation layer 204 may be deposited using processes such as ALD, CVD, or PVD. According to an exemplary embodiment, encapsulation layer 204 has a thickness from about 5 nm to about 15 nm and ranges therebetween. The material selected for encapsulation layer 204 should provide etch selectivity to an interlayer dielectric (ILD) 206 fill subsequently deposited over MTJ 202. In this way, the topography of the encapsulated MTJ may be used to self-align contacts to the top of the MTJ (see below).

[0032] That is, the MTJ 202 is then buried in the ILD 206. The terms "first dielectric" and "second dielectric" may be used herein when referring to the dielectric 102 and the ILD 206. Suitable ILD 206 include, but are not limited to, oxide materials such as SiOx and / or SiCOH and / or ULK-ILD materials such as pSiCOH, each of which can be selectively etched relative to the encapsulation layer 204 (e.g., SiN). The ILD 206 can be deposited over / surrounding the MTJ 202 using processes such as ALD, CVD, PVD, a casting process such as spin coating, and the like. A trench 302 is then patterned in the ILD 206 over the MTJ 202, thereby exposing the (encapsulated) MTJ 202 within the trench 302, which creates a topography at the bottom of the trench 302. See Figure 3 Specifically, Figure 3As shown, the trench 302, when patterned, extends partially through the ILD 206, wherein the bottom of the trench 302 is below the encapsulation layer 204 above the MTJ 202. Standard lithography and etching techniques may be used to pattern the trench 302 using, for example, a directional (i.e., anisotropic) etching process such as reactive ion etching (RIE) for trench etching. By way of example only, when the ILD 206 is an oxide material (see above), an oxide-selective RIE may be used to pattern the trench 302 in the ILD 206 that is selective to the (e.g., nitride) encapsulation layer 204. The topography at the bottom of the trench 302 includes a 'peak' formed by the encapsulation layer 204 above the MTJ 202 and a 'valley' formed by the bottom of the trench 302.

[0033] The trench 302 is then filled with one or more metals to form a metal line 404 above the MTJ 202. Figure 4 . If the interconnect 106 includes a metal line, the terms "first" and "second" may be used herein when referring to the interconnect 106 / metal line and the metal line 404, respectively. Suitable metals include, but are not limited to, Cu and / or Co. Prior to metal filling, a conformal barrier layer 402 is deposited into the trench 302 and lines the trench 302. The metal line 404 is formed on the barrier layer 402 so that the barrier layer 402 separates the metal line 404 from the ILD 206. As described above, suitable barrier materials include, but are not limited to, Ti, TiN, Ta, and / or TaN. According to an exemplary embodiment, the metal line 404 is Cu, and a thin (e.g., from about 1 nm to about 3 nm) Cu seed layer (not shown) is first deposited onto the barrier layer 402 using, for example, evaporation, sputtering, etc. Cu is then plated onto the seed layer to form the metal line 404.

[0034] It is noteworthy that metal line 404 is now formed over the topography created by (packaged) MTJ 202 at the bottom of trench 302. Advantageously, this topography enables the encapsulation layer 204 at the top of MTJ 202 to be selectively exposed along metal line 404. That is, as shown in FIG. Figure 5 As shown in , a polishing process such as CMP is used to recess the metal line 404 / ILD 206 down to the encapsulation layer 204. As a result of this polishing, the metal line 404 is now separated into segments 404a, 404b, etc. separated by the (now exposed) peaks of the encapsulation layer 204 at the top of the MTJ 202.

[0035] Then, a selective etch is performed to recess the exposed peak of the encapsulation layer 204, thereby forming a recess at the top of the MTJ 202. Figure 6 .like Figure 6As shown, such recessing of the encapsulation layer 204 exposes the top of the MTJ 202 between the metal line segments 404a, 404b, etc. Figure 6 By way of example only, nitride selective RIE or wet etch chemistry may be used to selectively etch (eg, SiN) encapsulation layer 204. Through this selective recessed etch process, contacts (see below) formed over recessed encapsulation layer 204 are self-aligned to the top of MTJ 202.

[0036] Then, a conductive material is deposited into / filled in the grooves on top of the MTJs 202, followed by a polishing process such as CMP to form contacts 702 in the grooves on top of each of the MTJs 202. Figure 7 Suitable conductive materials include, but are not limited to, metals such as Ru, Ta, TaN, Ti, TiN, W, Cu and / or Co. Figure 7 As shown, in the present device structure, there is no direct contact between the MTJ 202 and the metal line segments 404a, 404b, 404c, etc. Instead, the electrical connection between the MTJ 202 and the metal line segments 404a, 404b, 404c, etc. is formed via the contact 702. That is, the contact 702 is in direct physical / electrical contact with the MTJ 202. The contact 702 is electrically connected to the metal line segments 404a, 404b, 404c, etc. through the barrier layer 402. Therefore, the MTJ 202 can be accessed through the contact 702 and / or the metal line segments 404a, 404b, 404c, etc.

[0037] As emphasized above, the present technique advantageously eliminates the reliance on pullback and overlap of the lines described above. To illustrate this, reference is now made to Figure 8-Figure 12 An exemplary method of forming an MRAM device is described in which there is some misalignment of the trench patterned over the MTJ 202, such as may occur due to, for example, line pullback. For example, briefly returning to reference Figure 3 (As described above), trench 302 is substantially centered over MTJ 202. In practice, however, some degree of misalignment of the trench over the MTJ can be expected, especially near the end of the line.

[0038] The process begins in the same general manner as the above examples by forming interconnects 106 (eg, vias and / or metal lines) in dielectric 102 over barrier layer 104 and forming capping layer 108 on interconnects 106 (see above). Figure 1 ), forming MTJ 202 on interconnect 106, depositing conformal encapsulation layer 204 and ILD 206 over MTJ 202 (see above Figure 2 Therefore, Figure 8 Describes Figure 2In addition, similar structures are numbered similarly in the accompanying drawings.

[0039] As described above, trenches 302' are then patterned in ILD 206 over MTJ 202 (eg, using RIE). Figure 8 However, in this case, trench 302' is not directly centered over MTJ 202, but is slightly offset (i.e., off-center) over MTJ 202. This misalignment may occur due to process variations such as pull-back (see above). As a result, encapsulation layer 204 (on top of one of MTJs 202) may be located on top of the MTJ 202. Figure 8 arbitrarily shown on the right in FIG. 3 ) is fully exposed in the trench 302′, while the encapsulation layer 204 on top of the other MTJ 202 (shown on the right in FIG. 3 ) is fully exposed in the trench 302′. Figure 8 Only a portion of the MTJ 202 (arbitrarily shown on the left in FIG. 1 ) is exposed. Nevertheless, it is important to note that the fully / partially exposed (encapsulated) MTJ 202 produces a topography at the bottom of the trench 302'. Figure 8 As shown, the topography of the bottom of the trench 302' includes a peak formed by the encapsulation layer 204 above the MTJ 202 and a valley formed by the bottom of the trench 302'.

[0040] The trench 302' is then filled with one or more metals to form a metal line 904 above the MTJ 202. Fig. 9 . If the interconnect 106 includes a metal line, the terms "first" and "second" may be used herein when referring to the interconnect 106 / metal line and the metal line 904, respectively. As described above, suitable metals include, but are not limited to, Cu and / or Co. Prior to metal filling, a conformal barrier layer 902 (e.g., Ti, TiN, Ta, and / or TaN) is deposited into and lines the trench 302'. The metal line 904 is formed on the barrier layer 902 such that the barrier layer 902 separates the metal line 904 from the ILD 206. According to an exemplary embodiment, the metal line 904 is Cu, and a thin (e.g., from about 1 nm to about 3 nm) Cu seed layer (not shown) is first deposited onto the barrier layer 902 using, for example, evaporation, sputtering, etc. Cu is then plated onto the seed layer to form the metal line 904.

[0041] Metal line 904 is now formed over the topography created by the (encapsulated) MTJ 202 at the bottom of trench 302'. Advantageously, this topography enables the encapsulation layer 204 at the top of the MTJ 202 to be selectively exposed along the metal line 904. That is, in the same manner as above, a polishing process such as CMP is used to recess the metal line 904 / ILD 206 down to the encapsulation layer 204. See Fig.10As a result of this polishing, the metal line 904 is now separated into segments 904 a , 904 b , etc. separated by the (now exposed) peaks of the encapsulation layer 204 at the top of the MTJ 202 .

[0042] A selective etch is then performed to recess the exposed peaks of the encapsulation layer 204 to form a recess at the top of the MTJ 202, which exposes the top of the MTJ 202 between the metal line segments 904a, 904b, etc. Fig.11 By way of example only, nitride selective RIE or wet etch chemistry may be used to selectively etch (eg, SiN) encapsulation layer 204. Through this selective recessed etch process, contacts (see below) formed over recessed encapsulation layer 204 are self-aligned to the top of MTJ 202.

[0043] Then, a conductive material is deposited into / filled in the grooves on top of the MTJs 202, followed by a polishing process such as CMP to form contacts 1202 in the grooves on top of each of the MTJs 202. Fig.12 As provided above, suitable conductive materials include, but are not limited to, metals such as Ru, Ta, TaN, Ti, TiN, W, Cu, and / or Co. Fig.12 As shown, in the present device structure, there is no direct contact between the MTJ 202 and the metal line segments 904a, 904b, etc. Instead, the electrical connection between the MTJ 202 and the metal line segments 904a, 904b, etc. is formed via the contact 1202. That is, the contact 1202 is in direct physical / electrical contact with the MTJ 202. The contact 1202 is electrically connected to the metal line segments 904a, 904b, etc. through the barrier layer 902. Thus, the MTJ 202 can be accessed through the contact 1202 and / or the metal line segments 904a, 904b, etc.

[0044] Fig.13 1 is a diagram showing an exemplary MTJ 1300. MTJ 1300 represents MTJ 202 implemented in the above embodiment. Fig.13 As shown, MTJ 1300 includes a magnetic metal layer 1302 separated from a magnetic metal layer 1306 by a tunnel barrier 1304. As provided above, suitable materials for magnetic metal layers 1302 and 1306 include, but are not limited to, Co, Fe, Ni, Co alloys, Fe alloys, and / or Ni alloys.

[0045] Tunnel barrier 1304 isolates magnetic metal layer 1302 from magnetic metal layer 1306. However, since tunnel barrier 1304 is ultra-thin, electrons can tunnel from one magnetic metal layer to another magnetic metal layer through tunnel barrier 1304. For example, according to an exemplary embodiment, the tunnel barrier has a thickness from about 2 nm to about 3 nm and varies therebetween. As provided above, suitable materials for tunnel barrier 1304 include, but are not limited to, aluminum and / or magnesium oxide.

[0046] Although illustrative embodiments of the present invention have been described herein, it should be understood that the invention is not limited to those precise embodiments and that various other changes and modifications may be made by those skilled in the art without departing from the scope of the present invention.

Claims

1. A method for forming a magnetic random access memory (MRAM) device, the method comprising the steps of: forming a magnetic tunnel junction on an interconnect embedded in the first dielectric; depositing an encapsulation layer over the magnetic tunnel junction; burying the magnetic tunnel junction in a second dielectric; patterning a trench in the second dielectric above the magnetic tunnel junction, thereby exposing the encapsulation layer above a top of the magnetic tunnel junction, forming a topography at a bottom of the trench; forming a metal line in the trench over the topography at the bottom of the trench; recessing the metal line down to the encapsulation layer and exposing the encapsulation layer, wherein the recessing separates the metal line into segments separated by exposed peaks of the encapsulation layer over the magnetic tunnel junction; recessing the exposed peaks of the encapsulation layer to form recesses between the segments of the metal line at the tops of the magnetic tunnel junctions; as well as A contact is formed in the recess between the segments of the metal line that is self-aligned with a top of the magnetic tunnel junction.

2. The method according to claim 1, further comprising the steps of: depositing a barrier layer into the trench and lining the trench; as well as The metal line is formed on the barrier layer in the trench. 3 . The method of claim 2 , wherein the contact is in direct contact with the magnetic tunnel junction, and wherein the contact is connected to the segment of the metal line through the barrier layer.

4. The method of any one of the preceding claims, wherein a capping layer is provided on the interconnect, and wherein the magnetic tunnel junction is formed on the interconnect above the capping layer. 5 . The method of claim 4 , wherein the capping layer comprises a material selected from the group consisting of ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and combinations thereof.

6. The method of any one of the preceding claims, wherein each of the magnetic tunnel junctions comprises: at least one free magnetic metal layer; at least one fixed magnetic metal layer; as well as A tunnel barrier is provided between the at least one free magnetic metal layer and the at least one fixed magnetic metal layer.

7. A method according to any preceding claim, wherein the encapsulation layer comprises an insulator. The method of claim 7 , wherein the insulator is silicon nitride (SiN).

9. A method according to any one of the preceding claims, wherein the patterned trench is centred over the magnetic tunnel junction.

10. The method of any one of claims 1 to 8, wherein the patterned trenches are offset over the magnetic tunnel junctions such that the trenches expose only a portion of the encapsulation layer over a top portion of at least one of the magnetic tunnel junctions.

11. The method of claim 2, wherein the barrier layer comprises a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and combinations thereof.

12. The method of any of the preceding claims, wherein the contact comprises a material selected from the group consisting of ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), copper (Cu), cobalt (Co), and combinations thereof.

13. An MRAM device comprising: a magnetic tunnel junction disposed on an interconnect embedded in the first dielectric; an encapsulation layer, the encapsulation layer being disposed above the magnetic tunnel junction; a second dielectric surrounding the magnetic tunnel junction; a recess in the encapsulation layer, the recess being located at a top of the magnetic tunnel junction between segments of a metal line, wherein the segments of the metal line are separated from the second dielectric by a barrier layer; as well as A contact is formed in the recess, the contact being self-aligned with a top portion of the magnetic tunnel junction, wherein the contact is in direct contact with the magnetic tunnel junction, and wherein the contact is connected to the segment of the metal line through the barrier layer.

14. The MRAM device of claim 13, further comprising: A capping layer is disposed on the interconnect, wherein the magnetic tunnel junction is disposed on the interconnect above the capping layer, and wherein the capping layer includes a material selected from the group consisting of ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and combinations thereof.

15. The MRAM device of claim 13 or claim 14, wherein each of the magnetic tunnel junctions comprises: at least one free magnetic metal layer; at least one fixed magnetic metal layer; as well as A tunnel barrier is provided between the at least one free magnetic metal layer and the at least one fixed magnetic metal layer.

16. The MRAM device of any one of claims 13 to 15, wherein the barrier layer comprises a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and combinations thereof.

17. The MRAM device of any one of claims 13 to 16, wherein the contact comprises a material selected from the group consisting of ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), copper (Cu), cobalt (Co), and combinations thereof.

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