Power amplifier, chip and terminal device

Abstract

The application provides a power amplifier, a chip and a terminal device, and relates to the technical field of electronics. The power amplifier comprises a first output pin, a first power amplification circuit and a second power amplification circuit; the first power amplification circuit and the second power amplification circuit are connected with the first output pin respectively; the control ends of the first power amplification circuit and the second power amplification circuit are connected with a logic control module respectively; the first voltage output by the first power amplification circuit is smaller than the second voltage output by the second power amplification circuit; the first power amplification circuit and the second power amplification circuit alternately output the first voltage and the second voltage to the first output pin under the control of the logic control module, so that the first output pin outputs a first staircase wave used for driving an antenna, and the first staircase wave comprises two-stage voltages with amplitudes of the first voltage and the second voltage. The scheme can save an electromagnetic compatibility filter in an NFC radio frequency circuit, thereby reducing the cost of the NFC radio frequency circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a power amplifier, chip, and terminal device. Background Technology

[0002] Near Field Communication (NFC) is a short-range, high-frequency wireless communication technology. The Near Field Communication Controller (NFCC) is a chip that provides NFC active communication functionality. The NFCC controller includes a baseband processing unit, logic control circuitry, and a power amplifier. The baseband processing unit generates the low-frequency digital signal required for communication (i.e., the low-frequency digital signal carries the communication signal to be transmitted to the receiver). This digital signal is processed by the logic control circuitry and converted into a high-frequency logic control signal for the power amplifier. The power amplifier amplifies this logic control signal to generate the transmission signal that drives the antenna.

[0003] Most current NFCC design architectures use simple Class D power amplifiers. The output signal of a Class D power amplifier is a rectangular wave, while the actual transmit signal required to drive the antenna is a sine wave. Therefore, an electromagnetic compatibility (EMC) filter needs to be set between the near-field communication controller and the communication antenna. The EMC filter suppresses the high-order harmonics in the transmit signal output by the power amplifier to prevent high-order harmonics from radiating outward through the antenna and affecting other functional modules in the NFC device.

[0004] The high cost of NFC radio frequency circuits is due to the need for an electromagnetic compatibility filter between the near-field communication controller and the antenna, which is expensive. Summary of the Invention

[0005] This application provides a power amplifier, chip, and terminal device that can save on electromagnetic compatibility filters in NFC radio frequency circuits, thereby reducing the cost of NFC radio frequency circuits.

[0006] In a first aspect, embodiments of this application provide a power amplifier applied to a chip, the power amplifier including: a first output pin, a first power amplification circuit, and a second power amplification circuit;

[0007] The first output terminal of the first power amplifier circuit and the first output terminal of the second power amplifier circuit are respectively connected to the first output pin;

[0008] The control terminals of the first power amplifier circuit and the second power amplifier circuit are respectively connected to the logic control module in the chip;

[0009] The first voltage output by the first power amplifier circuit is less than the second voltage output by the second power amplifier circuit;

[0010] Under the control of the logic control module, the first power amplifier circuit and the second power amplifier circuit alternately output the first voltage and the second voltage to the first output pin, so that the first output pin outputs a first stepped wave for driving the antenna, wherein the first stepped wave includes two voltage levels with amplitudes of the first voltage and the second voltage.

[0011] In one possible implementation, the first power amplifier circuit and the second power amplifier circuit, under the control of the logic control module, alternately or simultaneously output the first voltage and the second voltage to the first output pin, so that the first output pin outputs a second stepped wave for driving the antenna, wherein the second stepped wave includes three voltage levels with amplitudes of the first voltage, the difference between the second voltage and the first voltage, and the second voltage.

[0012] In one possible implementation, the power amplifier further includes: at least one third power amplifier circuit;

[0013] The first output terminal of each of the third power amplifier circuits is connected to the first output pin;

[0014] The control terminal of each of the third power amplifier circuits is connected to the logic control module;

[0015] Different third power amplifier circuits output different third voltages, and these third voltages are different from the first voltage and the second voltage.

[0016] Under the control of the logic control module, the first power amplifier circuit, the second power amplifier circuit, and the at least one third power amplifier circuit sequentially output voltages to the first output pin in the order of output voltage from low to high and then from high to low, so that the first output pin outputs a third-step wave for driving the antenna, wherein the third-step wave includes at least three voltage levels with amplitudes of the first voltage, the second voltage, and at least one of the third voltages.

[0017] In one possible implementation, the power amplifier further includes: a second output pin;

[0018] The second output terminal of each power amplifier circuit in the power amplifier circuit group is connected to the second output pin respectively. The power amplifier circuit group includes the first power amplifier circuit and the second power amplifier circuit, or the first power amplifier circuit, the second power amplifier circuit and at least one third power amplifier circuit.

[0019] Under the control of the logic control module, each power amplifier circuit in the power amplifier circuit group outputs a voltage to the second output pin, so that the second output pin outputs a fourth step wave for driving the antenna. The fourth step wave has the same frequency and amplitude as the step wave output by the first output pin, and the phase difference is half a cycle.

[0020] In one possible implementation, each power amplifier circuit in the power amplifier circuit group includes: a first switching circuit, a second switching circuit, and a driving power supply, wherein the output voltage of the driving power supply in the first power amplifier circuit, the second power amplifier circuit, and the third power amplifier circuit is different.

[0021] The first switching circuit and the second switching circuit are respectively connected to the driving power supply;

[0022] The first switching circuit is connected to the first output pin, and the second switching circuit is connected to the second output pin;

[0023] When the first switching circuit is turned on under the control of the logic control module, the second switching circuit is turned off under the control of the logic control module. The first switching circuit connects the driving power supply to the first output pin so that the first output pin outputs a voltage equal to the output voltage of the driving power supply.

[0024] When the second switching circuit is turned on under the control of the logic control module, the first switching circuit is turned off under the control of the logic control module. The second switching circuit connects the driving power supply to the second output pin so that the second output pin outputs a voltage equal to the output voltage of the driving power supply.

[0025] In one possible implementation, the first switching circuit includes: a first P-channel metal-oxide-semiconductor (PMOS) transistor, a first N-channel metal-oxide-semiconductor (NMOS) transistor, and a first inverter; the second switching circuit includes: a second PMOS transistor, a second NMOS transistor, and a second inverter.

[0026] The input terminal of the first inverter is connected to the first signal output terminal of the logic control module, the output terminal of the first inverter is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to the driving power supply, and the drain of the first PMOS transistor is connected to the first output pin.

[0027] The gate of the first NMOS transistor is connected to the first signal output terminal, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the second output pin.

[0028] The input terminal of the second inverter is connected to the second signal output terminal of the logic control module, the output terminal of the second inverter is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the driving power supply, and the drain of the second PMOS transistor is connected to the second output pin.

[0029] The gate of the second NMOS transistor is connected to the second signal output terminal, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the first output pin.

[0030] In one possible implementation, the power amplifier further includes: a ground pin;

[0031] The grounding pin is connected to the source of the first NMOS transistor and the source of the second NMOS transistor in each power amplifier circuit of the power amplifier circuit group.

[0032] The grounding pin is used to provide a reference ground voltage.

[0033] In one possible implementation, the power amplifier includes one of the third power amplifier circuits;

[0034] The ratio of the first voltage, the second voltage, and the third voltage is 0.2679:0.7321:1.

[0035] In one possible implementation, within one logic control cycle of the logic control module, the ratio of the time lengths during which the first power amplifier circuit, the second power amplifier circuit, and the third power amplifier circuit output voltage to the first output pin in the order of first power amplifier circuit, second power amplifier circuit, third power amplifier circuit, second power amplifier circuit, and first power amplifier circuit under the control of the logic control module is equal to 1:1:2:1:1.

[0036] Secondly, embodiments of this application also provide a chip, including the power amplifier described in the first aspect and any possible implementation thereof.

[0037] In one possible implementation, the chip is a near-field communication (NFC) controller chip, which is used to transmit and receive NFC signals through a connected antenna.

[0038] Thirdly, embodiments of this application also provide a terminal device, including the chip described in the second aspect and any possible implementation thereof.

[0039] Based on the above technical solution, the control terminals of the first and second power amplifier circuits are respectively connected to a logic control module. The logic control module controls the first and second power amplifier circuits through the control terminals. Under the control of the logic control module, the first and second power amplifier circuits alternately output a first voltage and a second voltage to the first output pin, so that the first output pin outputs a two-stage stepped wave with amplitudes equal to the first and second voltages. This two-stage stepped wave drives the antenna. Because the first and second voltages are different, the first stepped wave with amplitudes equal to the first and second voltages is closer to a sine wave. Therefore, the first stepped wave contains fewer higher-order harmonics, so the antenna can be directly driven by the first stepped wave output from the first output pin without the need for a costly EMC filter between the power amplifier and the antenna, thus reducing the cost of the NFC radio frequency circuit. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of an NFC communication process provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of an ideal rectangular wave spectrum distribution provided in an embodiment of this application;

[0043] Figure 3 This is a schematic block diagram of a power amplifier provided in an embodiment of this application;

[0044] Figure 4 This is a waveform diagram of a first-step wave provided in an embodiment of this application;

[0045] Figure 5 This is a waveform diagram of a second-step wave provided in an embodiment of this application;

[0046] Figure 6 This is a schematic block diagram of another power amplifier provided in an embodiment of this application;

[0047] Figure 7 This is a waveform diagram of a third-step wave provided in an embodiment of this application;

[0048] Figure 8 This is a waveform diagram of another third-step wave provided in an embodiment of this application;

[0049] Figure 9 This is a schematic block diagram of yet another power amplifier provided in the embodiments of this application;

[0050] Figure 10 This is a schematic diagram of a stepped wave output by two output pins provided in an embodiment of this application;

[0051] Figure 11 This is a schematic block diagram of another power amplifier provided in the embodiments of this application;

[0052] Figure 12 This is a schematic diagram of the switching timing of a switching circuit provided in an embodiment of this application;

[0053] Figure 13 This is a schematic diagram of the stepped wave output by two output pins according to another embodiment of this application;

[0054] Figure 14 This is a schematic diagram of the circuit structure of a power amplifier provided in an embodiment of this application;

[0055] Figure 15 This is a schematic diagram of a logic control signal provided in an embodiment of this application;

[0056] Figure 16 This is a schematic diagram of an antenna signal spectrum distribution provided in an embodiment of this application;

[0057] Figure 17 This is a schematic diagram of a terminal device provided in an embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0059] Near Field Communication (NFC) technology is widely used in mobile devices, access control systems, electronic payments, and other fields. The basic principle of NFC technology is to use inductive coupling technology between two NFC devices to achieve bidirectional interactive communication. NFC technology defines two types of devices: NFC initiators (sometimes called PollingDevice) and NFC targets (sometimes called ListeningDevice).

[0060] Figure 1 This is a schematic diagram of an NFC communication process provided in an embodiment of this application. See also... Figure 1 The NFC initiator's signal is processed by the internal circuitry of the Near Field Communication Controller (NFCC) chip. The signal is then output by the NFCC chip's internal power amplifier. This output signal is conditioned by external transmitting circuitry and transmitted to the antenna, which generates a magnetic field nearby. This magnetic field becomes the NFC operating area. The NFC initiator's antenna transmits signals externally using this magnetic field. The signals transmitted by the NFC initiator conform to the NFC communication protocol and are known as NFC polling signals.

[0061] When an NFC target enters the magnetic field generated by the NFC initiator, the initiator detects the change in the magnetic field and analyzes whether communication is appropriate. If the NFC initiator and the NFC target meet the conditions required for communication, they begin NFC communication. The NFC target communicates with the NFC initiator using load modulation.

[0062] Any real-world periodic signal can be reconstructed from a series of sine waves of different frequencies; this is essentially using Fourier series expansion to represent a periodic signal. During NFC communication, the carrier wave used in the air interface is a sine wave; however, the transmit signal output by the NFCC chip is a rectangular wave with a 50% duty cycle and a frequency of 13.56MHz, which cannot be directly used on the antenna. Figure 2 This is a schematic diagram of an ideal rectangular wave spectrum distribution provided in an embodiment of this application. When the amplitude of the rectangular wave is 5V, the amplitude distribution of the first 20 harmonics of the rectangular wave, calculated theoretically, is as follows: Figure 2 As shown, apart from the required first harmonic (i.e., the harmonic with a frequency of 13.56 MHz), the rectangular wave includes a rich array of harmonic components.

[0063] Due to the radiation characteristics of antennas, harmonics at the antenna can cause serious EMC problems. Because the motherboards of mobile phones, smartwatches, and other terminal devices are limited by the overall size of the device, various functional modules are tightly packed together. During NFC signal transmission, if large harmonics are radiated outwards through the antenna, they could potentially affect other functional modules on the motherboard, such as Bluetooth Low Energy (BLE) modules, 4G modules, 5G modules, WiFi modules, or display controllers. Therefore, while ensuring NFC communication, it is necessary to suppress the signal amplitude of harmonics transmitted to the antenna as much as possible.

[0064] The existing method for suppressing the amplitude of harmonic signals on the antenna is to set an EMC filter between the NFCC chip and the antenna. The rectangular wave signal output by the NFCC chip first passes through the EMC filter. While ensuring the amplitude of the NFC communication signal, the higher-order harmonics are suppressed by the EMC filter. Then, the signal after being filtered by the EMC filter is transmitted to the antenna, thereby suppressing the amplitude of the harmonic signals transmitted to the antenna and preventing the antenna from radiating large harmonics that would affect the normal operation of other functional modules.

[0065] It is evident that existing methods for suppressing harmonic signal amplitude on the antenna require the addition of an EMC filter. EMC filters consist of expensive high-power inductors and capacitors, thus increasing the cost of the NFC RF circuitry. Furthermore, the EMC filter also occupies space on the motherboard of the terminal device, resulting in the NFC RF circuitry occupying a significant portion of the motherboard area, which is detrimental to motherboard design and the miniaturization of the terminal device.

[0066] Figure 3 This is a schematic block diagram of a power amplifier provided in an embodiment of this application. The power amplifier provided in this embodiment is applied to a chip; see [link to relevant documentation]. Figure 3 The power amplifier 300 includes: a first output pin 301, a first power amplifier circuit 302, and a second power amplifier circuit 303;

[0067] The first output terminal 3021 of the first power amplifier circuit 302 and the first output terminal 3031 of the second power amplifier circuit 303 are respectively connected to the first output pin 301.

[0068] The control terminal 3022 of the first power amplifier circuit 302 and the control terminal 3032 of the second power amplifier circuit 303 are respectively connected to the logic control module 200 in the chip;

[0069] The first voltage V1 output by the first power amplifier circuit 302 is less than the second voltage V2 output by the second power amplifier circuit;

[0070] Under the control of the logic control module 200, the first power amplifier circuit 302 and the second power amplifier circuit 303 alternately output a first voltage V1 and a second voltage V2 to the first output pin 301, so that the first output pin 301 outputs a first stepped wave for driving the antenna 100, wherein the first stepped wave includes two voltage levels with amplitudes of the first voltage V1 and the second voltage V2.

[0071] In this embodiment, the control terminal 3022 of the first power amplifier circuit 302 and the control terminal 3032 of the second power amplifier circuit 303 are respectively connected to the logic control module 200. The logic control module 200 controls the first power amplifier circuit 302 and the second power amplifier circuit 303 through the control terminal 3022 and the control terminal 3032. Under the control of the logic control module 200, the first power amplifier circuit 302 and the second power amplifier circuit 303 alternately output the first voltage V1 and the second voltage V2 to the first output pin 301, so that the first output pin 301 outputs two-stage stepped waves including the amplitude of the first voltage V1 and the second voltage V2, and drives the antenna 100 through the two-stage stepped waves. Because the first voltage V1 and the second voltage V2 are different, the first stepped wave, which includes two voltage levels with amplitudes of the first voltage V1 and the second voltage V2, is closer to a sine wave. Therefore, the first stepped wave includes fewer high-order harmonics, so the antenna 100 can be driven directly through the first stepped wave output by the first output pin 301 without the need to set a costly EMC filter between the power amplifier 300 and the antenna 100. This reduces the cost of the NFC radio frequency circuit.

[0072] In addition, since there is no need to set an EMC filter between the power amplifier 300 and the antenna 100, there is no need to reserve space for the EMC filter on the motherboard of the terminal device, thereby reducing the area occupied by the NFC radio frequency circuit on the motherboard, improving the convenience of motherboard design, and facilitating the miniaturization design of the terminal device.

[0073] It should be understood that, such as Figure 3As shown, the power amplifier 300 also includes a ground pin 304. The ground terminal 3023 of the first power amplifier circuit 302 and the ground terminal 3033 of the second power amplifier circuit 303 are both connected to the ground pin 304. When the first power amplifier circuit 302 outputs a first voltage V1 to the first output pin 301, or the second power amplifier circuit 303 outputs a second voltage V2 to the first output pin 301, the output voltage of the first output pin 301 is either the first voltage V1 or the second voltage V2. At this time, the output voltage of the first output pin 301 relative to the voltage of the ground pin 304 is not zero. When neither the first power amplifier circuit 302 nor the second power amplifier circuit 303 outputs voltage to the first output pin 301, the output voltage of the first output pin 301 relative to the voltage of the ground pin 304 is equal to zero. Therefore, the antenna 100 is connected to the first output pin 301 and the ground pin 304. The first output pin 301 supplies a changing voltage to the antenna 100 relative to the ground pin 304 to drive the antenna 100 to transmit signals carrying communication information.

[0074] It should also be understood that the power amplifier 300 is located in the chip, and the first output pin 301 and the ground pin 304 are different pins on the chip. After the chip is mounted on the printed circuit board (PCB), the first output pin 301 is connected to the antenna through the connecting wires in the PCB and other parts of the NFC radio frequency circuit.

[0075] It should be noted that, as Figure 3 As shown, the chip includes a baseband control unit 400, a logic control module 200, and a power amplifier 300, wherein the logic control module 200 includes logic control circuitry within the chip. The baseband control unit 400 generates the required low-frequency digital signal for communication. After signal processing by the logic control module 200, the digital signal is converted into a logic control signal input to the power amplifier 300. The power amplifier 300 amplifies the logic control signal to obtain a transmission signal used to drive the antenna 100.

[0076] Optionally, in one implementation, the first power amplifier circuit 302 and the second power amplifier circuit 303, under the control of the logic control module 200, alternately or simultaneously output a first voltage V1 and a second voltage V2 to the first output pin 301, so that the first output pin 301 outputs a second stepped wave for driving the antenna 100, wherein the second stepped wave includes three voltage levels with amplitudes of V1, V2-V1 and V2.

[0077] Figure 4 This is a waveform diagram of a first-step wave provided in an embodiment of this application. Figure 5This is a waveform diagram of a second stepped wave provided in an embodiment of this application. When the first power amplifier circuit 302 and the second power amplifier circuit 303 alternately output the first voltage V1 and the second voltage V2 to the first output pin 301, the first output pin 301 outputs a first stepped wave including two voltage levels with amplitudes of the first voltage V1 and the second voltage V2. The waveform of the first stepped wave output by the first output pin 301 at this time is as follows: Figure 4 As shown. When the first power amplifier circuit 302 and the second power amplifier circuit 303 output voltages to the first output pin 301 in the following order: the first power amplifier circuit 302 outputs voltage, the first power amplifier circuit 302 and the second power amplifier circuit 303 simultaneously output voltages, and the second power amplifier circuit 303 outputs voltage, the first output pin 301 outputs a second stepped wave with amplitudes including three levels of voltages: V1, V2-V1, and V2, where V1 < V2-V1 < V2. The waveform of the second stepped wave output by the first output pin 301 at this time is as follows: Figure 5 As shown. By Figure 4 and Figure 5 It is evident that, compared to the first step wave which includes two levels, the second step wave, which includes three levels of amplitude, is closer to a sine wave. Therefore, the second step wave contains fewer higher-order harmonics than the first step wave.

[0078] In this embodiment, under the control of the logic control module 200, the first power amplifier circuit 302 and the second power amplifier circuit 303 can alternately output voltage to the first output pin 301. The first power amplifier circuit 302 and the second power amplifier circuit 303 can also output voltage to the first output pin 301 simultaneously. When only the first power amplifier circuit 302 outputs voltage to the first output pin 301, the voltage output by the first output pin 301 is the first voltage V1. When only the second power amplifier circuit 303 outputs voltage to the first output pin 301, the voltage output by the first output pin 301 is the second voltage V2. When the first power amplifier circuit 302 and the second power amplifier circuit 303 output voltage to the first output pin 301 simultaneously, the output voltage of the first output pin 301 is V2-V1. Therefore, the first power amplifier circuit 302 and the second power amplifier circuit 303 simultaneously output voltage to the first output pin 301. The first voltage V1 and the second voltage V2 are superimposed on the first output pin 301, so that the first output pin 301 outputs a voltage V2-V1 that is different from the first voltage V1 and the second voltage V2. This results in the first output pin 301 outputting a second stepped wave including three voltage levels. The second stepped wave is closer to a sine wave, which can further reduce the signal amplitude of high-order harmonics transmitted to the antenna 100. While ensuring the normal operation of NFC communication function, it also ensures the normal operation of other functional modules in the terminal device.

[0079] Optionally, in one implementation, in addition to the first power amplifier circuit 302 and the second power amplifier circuit 303, the power amplifier 300 may include more power amplifier circuits, so that the first output pin 301 outputs a stepped wave including more voltage levels, making the stepped wave output by the first output pin 301 closer to a sine wave, and further reducing the signal amplitude of higher-order harmonics transmitted to the antenna 100.

[0080] Figure 6 This is a schematic block diagram of another power amplifier 300 provided in an embodiment of this application. See also... Figure 6 ,exist Figure 3 Based on the power amplifier 300 shown, the power amplifier 300 also includes at least one third power amplifier circuit 305;

[0081] The first output terminal 3051 of each third power amplifier circuit 305 is connected to the first output pin 301;

[0082] The control terminal 3052 of each third power amplifier circuit 305 is connected to the logic control module 200;

[0083] Different third power amplifier circuits 305 output different third voltages V3, and the third voltage V3 is different from the first voltage V1 and the second voltage V2;

[0084] Under the control of the logic control module 200, the first power amplifier circuit 302, the second power amplifier circuit 303, and each of the third power amplifier circuits 305 output voltages to the first output pin 301 in the order of output voltage from low to high and then from high to low, so that the first output pin 301 outputs a third stepped wave for driving the antenna 100, wherein the third stepped wave includes at least three voltage levels with amplitudes of a first voltage V1, a second voltage V2, and at least one third voltage V3.

[0085] It should be understood that the number of third power amplifier circuits 305 included in the power amplifier 300 varies, and the number of stages of the third step wave output by the first output pin 301 also varies. Figure 7 This is a waveform diagram of a third-step wave provided in an embodiment of this application. Figure 8 This is a waveform diagram of another third-step wave provided in an embodiment of this application. When the power amplifier 300 includes a third power amplifier circuit 305, and the third voltage V3 output by the third power amplifier circuit 305 to the first output pin 301 is greater than the second voltage V2, the third-step wave output by the first output pin 301 includes three voltage levels with amplitudes of the first voltage V1, the second voltage V2, and the third voltage V3. The waveform of the third-step wave at this time is as follows: Figure 7As shown. When the power amplifier 300 includes N-2 third power amplifier circuits 305, and the third voltage V3 output by each third power amplifier circuit 305 to the first output pin 301 is greater than the second voltage V2, and N is a positive integer greater than 3, the third stepped wave output by the first output pin 301 includes N levels of voltages with amplitudes of the first voltage V1, the second voltage V2, and at least two third voltages V3. The waveform of the third stepped wave at this time is as follows: Figure 8 As shown.

[0086] In this embodiment, different third power amplifier circuits 305 can output different magnitudes of third voltage V3 to the first output pin 301. Moreover, the third voltage V3 output by each third power amplifier circuit 305 to the first output pin 301 is different from the first voltage V1 and the second voltage V2. Thus, under the control of the logic control module 200, the first power amplifier circuit 302, the second power amplifier circuit 303, and each third power amplifier circuit 305 can sequentially output voltages to the first output pin 301 in the order of low to high and then high to low, so that the first output pin 301 outputs a third stepped wave including at least three levels of voltage. Since the third stepped wave includes more voltages with different amplitudes than the first stepped wave, the third stepped wave can be closer to a sine wave. When the first output pin 301 outputs the third stepped wave to the antenna 100, it can further reduce the signal amplitude of the higher-order harmonics output to the antenna 100 and reduce the impact on other functional modules.

[0087] It should also be understood that, such as Figure 6 As shown, the ground terminal 3053 of the third power amplifier circuit 305 is connected to the ground pin 304. When the first power amplifier circuit 302 outputs a first voltage V1 to the first output pin 301, or the second power amplifier circuit 303 outputs a second voltage V2 to the first output pin 301, or the third power amplifier circuit 305 outputs a third voltage V3 to the first output pin 301, the output voltage of the first output pin 301 is the first voltage V1, the second voltage V2, or the third voltage V3. At this time, the output voltage of the first output pin 301 is not zero relative to the voltage of the ground pin 304.

[0088] When none of the first power amplifier circuit 302, the second power amplifier circuit 303, or the third power amplifier circuit 305 outputs voltage to the first output pin 301, the output voltage of the first output pin 301 relative to the voltage of the ground pin 304 is zero. Therefore, the antenna 100 is connected to the first output pin 301 and the ground pin 304, and the first output pin 301 supplies a changing voltage to the antenna 100 relative to the ground pin 304 to drive the antenna 100 to transmit signals carrying communication information.

[0089] Optionally, in one implementation, the power amplifier 300 may further include a second output pin. Under the control of the logic control module 200, each power amplifier circuit included in the power amplifier 300 outputs a voltage to the first output pin 301 and the second output pin, so that the stepped wave output by the first output pin 301 and the second output pin has the same frequency and amplitude, and the phase difference is half a cycle.

[0090] Figure 9 This is a schematic block diagram of another power amplifier 300 according to an embodiment of this application, and... Figure 3 Compared to the power amplifier 300 shown, Figure 9 The power amplifier 300 shown can be considered as being in Figure 3 The power amplifier 300 shown is based on which a second output pin 306 is added.

[0091] For ease of description, the power amplifier circuit group is defined as including each power amplifier circuit included in power amplifier 300. When power amplifier 300 as... Figure 9 When the power amplifier 300 includes a first power amplifier circuit 302 and a second power amplifier circuit 303, the power amplifier circuit group includes the first power amplifier circuit 302 and the second power amplifier circuit 303. The first power amplifier circuit 302 includes a second output terminal 3024, and the second power amplifier circuit 303 includes a second output terminal 3034. When the power amplifier 300 includes a first power amplifier circuit 302, a second power amplifier circuit 303, and at least one third power amplifier circuit 305, the power amplifier circuit group includes the first power amplifier circuit 302, the second power amplifier circuit 303, and each third power amplifier circuit 305.

[0092] The first output terminal of each power amplifier circuit in the power amplifier circuit group is connected to the first output pin 301, and the second output terminal of each power amplifier circuit in the power amplifier circuit group is connected to the second output pin 306. Under the control of the logic control module 200, each power amplifier circuit in the power amplifier circuit group outputs a voltage to the second output pin 306, so that the second output pin 306 outputs a fourth stepped wave for driving the antenna 100. The fourth stepped wave has the same frequency and amplitude as the stepped wave output by the first output pin 301, and the phase difference is half a cycle.

[0093] In this embodiment, under the control of the logic control module 200, each power amplifier circuit in the power amplifier group can output voltage to both the first output pin 301 and the second output pin 306. This allows the first output pin 301 and the second output pin 306 to output stepped waves with the same frequency and amplitude but a phase difference of half a cycle. This differential driving method drives the antenna 100, ensuring that the power amplifier 300 has sufficient driving capability, enabling the antenna to send NFC signals to NFC devices within a set distance range. Furthermore, driving the antenna 100 differentially reduces the chip area occupied by the power amplifier 300, lowering the design complexity of the chip.

[0094] Figure 10 This is a schematic diagram of a stepped wave output from two output pins according to an embodiment of this application. See also... Figure 10 Tc is the period of the driving signal used to drive antenna 100. During the first Tc / 2 period, the first output pin 301 outputs a stepped wave, and the voltage on the second output pin 306 is zero. During the second Tc / 2 period, the voltage on the first output pin 301 is zero, and the second output pin 306 outputs a stepped wave. The stepped wave on the first output pin 301 during the first Tc / 2 period and the stepped wave on the second output pin 306 during the second Tc / 2 period have the same frequency and amplitude, but are phase-differentiated by Tc / 2.

[0095] Optionally, in one implementation, each power amplifier circuit in the power amplifier circuit group includes a first switching circuit, a second switching circuit, and a drive power supply. The following description uses the first power amplifier circuit 302 and the second power amplifier circuit 303 as examples to illustrate the process of outputting a stepped wave at the first output pin 301 and the second output pin 306. Figure 11 This is a schematic block diagram of yet another power amplifier provided in an embodiment of this application. See also... Figure 11 The first power amplifier circuit 302 includes a first switching circuit 3025, a second switching circuit 3026 and a driving power supply V1, and the second power amplifier circuit 303 includes a first switching circuit 3035, a second switching circuit 3036 and a driving power supply V2.

[0096] The first switch circuit 3025 and the second switch circuit 3026 are respectively connected to the drive power supply V1. The first switch circuit 3025 is connected to the first output pin 301, and the second switch circuit 3026 is connected to the second output pin 306.

[0097] The first switch circuit 3035 and the second switch circuit 3036 are respectively connected to the drive power supply V2. The first switch circuit 3035 is connected to the first output pin 301, and the second switch circuit 3026 is connected to the second output pin 306.

[0098] When the first switching circuit 3025 is turned on under the control of the logic control module 200, the second switching circuit 3026 is turned off under the control of the logic control module 200. The first switching circuit 3025 connects the driving power supply V1 to the first output pin 301 so that the first output pin 301 outputs a voltage equal to the output voltage of the driving power supply V1. When the second switching circuit 3026 is turned on under the control of the logic control module 200, the first switching circuit 3025 is turned off under the control of the logic control module 200. The second switching circuit 3026 connects the driving power supply V1 to the second output pin 306 so that the second output pin 306 outputs a voltage equal to the output voltage of the driving power supply V1.

[0099] When the first switching circuit 3035 is turned on under the control of the logic control module 200, the second switching circuit 3036 is turned off under the control of the logic control module 200. The first switching circuit 3035 connects the driving power supply V2 to the first output pin 301 so that the first output pin 301 outputs a voltage equal to the output voltage of the driving power supply V2. When the second switching circuit 3036 is turned on under the control of the logic control module 200, the first switching circuit 3035 is turned off under the control of the logic control module 200. The second switching circuit 3036 connects the driving power supply V2 to the second output pin 306 so that the second output pin 306 outputs a voltage equal to the output voltage of the driving power supply V2.

[0100] Figure 12 This is a schematic diagram of the switching timing of a switching circuit provided in an embodiment of this application, wherein... Figure 12 High and medium values ​​represent the on and off states of the switching circuit, respectively. Figure 13 This is a schematic diagram of a stepped wave output from two output pins according to another embodiment of this application. For example... Figure 12Within one logic control cycle Tc of the logic control module 200, four switching circuits are sequentially turned on in the order of first switching circuit 3025, first switching circuit 3035, first switching circuit 3025, second switching circuit 3026, second switching circuit 3036, and second switching circuit 3026. When any one of the four switching circuits is turned on, the other three switching circuits are turned off. When the first switching circuit 3025 is turned on, the output voltage of the first output pin 301 is V1, and the output voltage of the second output pin 306 is zero. When the first switching circuit 3035 is turned on, the output voltage of the first output pin 301 is V2, and the output voltage of the second output pin 306 is zero. When the second switching circuit 3026 is turned on, the output voltage of the second output pin 306 is V1, and the output voltage of the first output pin 301 is zero. When the second switching circuit 3036 is turned on, the output voltage of the second output pin 306 is V2, and the output voltage of the first output pin 301 is zero. After one logic control cycle of the logic control module 200 ends, the stepped wave output by the first output pin 301 and the stepped wave output by the second output pin 306 are as follows: Figure 13 As shown, the stepped wave output by the first output pin 301 and the stepped wave output by the second output pin 306 have the same frequency and amplitude, but are half a cycle out of phase.

[0101] In this embodiment, each power amplifier circuit in the power amplifier circuit group includes a first switching circuit and a second switching circuit. The first switching circuit is connected to the first output pin 301, and the second switching circuit is connected to the second output pin 306. When the first switching circuit is on, the second switching circuit is off; when the first switching circuit is off, the second switching circuit is on. When the first switching circuit is on, the driving power supply in the corresponding power amplifier circuit is connected to the first output pin 301, and the output voltage of the driving power supply is applied to the first output pin 301. When the second switching circuit is on, the driving power supply in the corresponding power amplifier circuit is connected to the second output pin 306, and the output voltage of the driving power supply is applied to the second output pin 306. Therefore, the on / off states of the first and second switching circuits in the same power amplifier circuit are opposite, so that the first output pin 301 and the second output pin 306 output stepped waves with the same frequency and amplitude but a phase difference of half a cycle, thereby realizing the driving of the antenna 100 through differential driving and ensuring that the power amplifier 300 has sufficient driving capability. In addition, differential driving is achieved through the first and second switching circuits, which simplifies the logic and reduces the space occupied by the power amplifier 300 on the chip, thus helping to reduce the design difficulty of the chip.

[0102] The following is combined Figures 14 to 16 The circuit structure of the power amplifier in the embodiments of this application is described in detail.

[0103] Figure 14 Based on Figure 6 This illustrates one possible implementation of the power amplifier 300. Since the different power amplifier circuits in the power amplifier circuit group have similar circuit structures, only the circuit structure of the first power amplifier circuit 302 will be described below. The circuit structures of the second power amplifier circuit 303 and the third power amplifier circuit 305 can be referenced from the circuit structure of the first power amplifier circuit 302, and will not be repeated here. See also... Figure 14 The first switching circuit 3025 includes a first P-channel metal-oxide-semiconductor (PMOS) transistor Q1, a first N-channel metal-oxide-semiconductor (NMOS) transistor Q4, and a first inverter C1. The second switching circuit 3026 includes a second PMOS transistor Q3, a second NMOS transistor Q2, and a second inverter C2.

[0104] The input terminal of the first inverter C1 is connected to the first signal output terminal Switch1 of the logic control section, the output terminal of the first inverter C1 is connected to the gate of the first PMOS transistor Q1, the source of the first PMOS transistor Q1 is connected to the driving power supply V1, and the drain of the first PMOS transistor Q1 is connected to the first output pin 301.

[0105] The gate of the first NMOS transistor Q4 is connected to the first signal output terminal Switch1, the source of the first NMOS transistor Q4 is grounded, and the drain of the first NMOS transistor Q4 is connected to the second output pin 306.

[0106] The input terminal of the second inverter C2 is connected to the second signal output terminal Switch2 of the logic control section, the output terminal of the second inverter C2 is connected to the gate of the second PMOS transistor Q3, the source of the second PMOS transistor Q3 is connected to the driving power supply V1, and the drain of the second PMOS transistor Q3 is connected to the second output pin 306.

[0107] The gate of the second NMOS transistor Q2 is connected to the second signal output terminal Switch2, the source of the second NMOS transistor Q2 is grounded, and the drain of the second NMOS transistor Q2 is connected to the first output pin 301.

[0108] In this embodiment, when the first signal output terminal Switch1 is high and the second signal output terminal Switch2 is zero, the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned on, while the second PMOS transistor Q3 and the second NMOS transistor Q2 are turned off. At this time, the output voltage of the first output pin 301 is V1, and the output voltage of the second output pin 306 is zero. When the first signal output terminal Switch1 is zero and the second signal output terminal Switch2 is high, the second PMOS transistor Q3 and the second NMOS transistor Q2 are turned on, while the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned off. At this time, the output voltage of the first output pin 301 is 0, and the output voltage of the second output pin 306 is V1.

[0109] Therefore, a half-bridge circuit is formed by the first PMOS transistor Q1 and the first NMOS transistor Q4, and another half-bridge circuit is formed by the second PMOS transistor Q3 and the second NMOS transistor Q2. The two half-bridge circuits together form a full-bridge circuit. Under the control of the logic control module 200, when one half-bridge circuit is turned on, the other half-bridge circuit is turned off, thereby driving the antenna through differential drive and ensuring that the power amplifier 300 has sufficient driving capability.

[0110] Optionally, in one implementation, the inputs of the first and second inverters in each power amplifier circuit of the power amplifier circuit group are connected to different signal outputs of the logic control module 200. See also Figure 14 In the first power amplifier circuit 302, the input terminal of the first inverter C1 is connected to the first signal output terminal Switch1 of the logic control module 200, and the input terminal of the second inverter C2 is connected to the second signal output terminal Switch2 of the logic control module 200. In the second power amplifier circuit 303, the input terminal of the first inverter C3 is connected to the first signal output terminal Switch3 of the logic control module 200, and the input terminal of the second inverter C4 is connected to the second signal output terminal Switch4 of the logic control module 200. In the third power amplifier circuit 305, the input terminal of the first inverter C5 is connected to the first signal output terminal Switch5 of the logic control module 200, and the input terminal of the second inverter C6 is connected to the second signal output terminal Switch6 of the logic control module 200. The first signal output terminals Switch1, Switch3, and Switch5, the second signal output terminals Switch2, Switch4, and Switch6 are different signal output terminals in the logic control module 200.

[0111] In this embodiment, the power amplifier 300 includes at least two power amplifier circuits, each power amplifier circuit including two inverters. The two inverters in the same power amplifier circuit are connected to different signal output terminals in the logic control module 200, and the inverters in different power amplifier circuits are also connected to different signal output terminals in the logic control module 200, so that each power amplifier circuit can be independently turned on and off under the control of the logic control module 200, so as to facilitate the formation of a stepped wave on the first output pin 301 and the second output pin 306, thereby reducing the amplitude of high-order harmonics in the transmitted signal output by the power amplifier 300.

[0112] It should be understood that the logic control module 200 has one or more logic control signals with outputs. When the logic control signal of the logic control section has multiple outputs, and the number of outputs of the logic control signal is greater than or equal to the total number of inverters included in each power amplifier circuit in the power amplifier 300, the input terminals of each inverter in each power amplifier circuit in the power amplifier 300 are respectively connected to different outputs of the logic control signal to transmit different logic control signals to each inverter in each power amplifier circuit, thereby independently controlling the on / off state of the first and second switching circuits in each power amplifier circuit. When the number of outputs of the logic control signal of the logic control module 200 is less than the total number of inverters included in each power amplifier circuit in the power amplifier 300, the logic control module 200 generates one or more new logic control signals based on the original logic control signals through a signal separation circuit, so that the input terminals of each inverter in each power amplifier circuit can be connected to different outputs of the logic control signal to transmit different logic control signals to each inverter in each power amplifier circuit, thereby independently controlling the on / off state of the first and second switching circuits in each power amplifier circuit.

[0113] Alternatively, in one implementation, see [link to implementation details]. Figure 14 The power amplifier 300 also includes a ground pin 304. The ground pin 304 is connected to the source of the first NMOS transistor and the source of the second NMOS transistor in each power amplifier circuit of the power amplifier 300, respectively. The ground pin 304 is used to provide a reference ground voltage.

[0114] In this embodiment, the sources of the first NMOS transistor and the second NMOS transistor in each power amplifier circuit of the power amplifier 300 are connected to the ground pin 304. When the first NMOS transistor or the second NMOS transistor is turned on, the first output pin 301 or the second output pin 306 has the same ground voltage as the ground pin 304. The power amplifier 300 transmits the transmission signal to the antenna 100 through the first output pin 301, the second output pin 306, and the ground pin 304. The ground pin 304 provides a reference ground voltage to ensure that the transmission signal can excite the antenna 100 to generate a magnetic field and transmit the NFC signal.

[0115] Alternatively, in one implementation, see [link to implementation details]. Figure 14 The power amplifier 300 includes a third power amplifier circuit 305, meaning the power amplifier 300 includes a first power amplifier circuit 302, a second power amplifier circuit 303, and a third power amplifier circuit 305. Under the control of the logic control module 200, the three power amplifier circuits in the power amplifier 300 output voltages to the first output pin 301 and the second output pin 306 in the following order: first power amplifier circuit 302, second power amplifier circuit 303, third power amplifier circuit 305, second power amplifier circuit 303, and first power amplifier circuit 302. The first voltage V1 output by the first power amplifier circuit 302 to the first output pin 301 or the second output pin 306 is less than the second voltage V2 output by the second power amplifier circuit 303 to the first output pin 301 or the second output pin 306. The second voltage V2 output by the second power amplifier circuit 303 to the first output pin 301 or the second output pin 306 is less than the third voltage V3 output by the third power amplifier circuit 305 to the first output pin 301 or the second output pin 306.

[0116] In this embodiment, under the control of the logic control module 200, the three power amplifier circuits included in the power amplifier 300 output voltages to the first output pin 301 and the second output pin 306 in the order of first power amplifier circuit 302, second power amplifier circuit 303, third power amplifier circuit 305, second power amplifier circuit 303, and first power amplifier circuit 302. The first power amplifier circuit 302 outputs a first voltage V1, the second power amplifier circuit 303 outputs a second voltage V2, and the third power amplifier circuit 305 outputs a third voltage V3, where V1 < V2 < V3, thereby forming a voltage distribution on the first output pin 301 and the second output pin 306. Figure 10 The stepped wave shown. It can be seen that... Figure 10The stepped waves on the first output pin 301 and the second output pin 306 are closer to sine waves than rectangular waves. Therefore, the stepped waves output by the first output pin 301 and the second output pin 306 include smaller higher-order harmonics and can be sent to the antenna without the need for an EMC filter, thereby reducing the cost of NFC radio frequency circuits.

[0117] Optionally, in one implementation, when the power amplifier 300 includes a first power amplifier circuit 302, a second power amplifier circuit 303, and a third power amplifier circuit 305, the first power amplifier circuit 302 outputs a first voltage V1, the second power amplifier circuit 303 outputs a second voltage V2, and the third power amplifier circuit 305 outputs a third voltage V3, and the ratio of the first voltage V1, the second voltage V2, and the third voltage V3 is equal to 0.2679:0.7321:1.

[0118] In this embodiment, under the control of the logic control module 200, the three power amplifier circuits included in the power amplifier 300 output voltages sequentially to the first output pin 301 and the second output pin 306 in the order of first power amplifier circuit 302, second power amplifier circuit 303, third power amplifier circuit 305, second power amplifier circuit 303, and first power amplifier circuit 302, so that the waveform of the stepped wave output from the first output pin 301 and the second output pin 306 is as follows: Figure 10 The diagram shows a stepped wave consisting of three voltage levels: V1, V2, and V3. When V1:V2:V3 = 0.2679:0.7321:1, the waveform of the stepped wave output from the first output pin 301 or the second output pin 306 is closer to a sine wave, ensuring that the transmitted signal output by the power amplifier 300 includes fewer higher-order harmonics.

[0119] Optionally, in one implementation, within one logic control cycle of the logic control module 200, the ratio of the time lengths during which the first power amplifier circuit 302, the second power amplifier circuit 303, and the third power amplifier circuit 305 output voltage to the first output pin 301 in the order of first power amplifier circuit 302, second power amplifier circuit 303, third power amplifier circuit 305, second power amplifier circuit 303, and first power amplifier circuit 302 is equal to 1:1:2:1:1.

[0120] In this embodiment, under the control of the logic control module, the three power amplifier circuits included in the power amplifier 300 output voltage to the first output pin 301 in the order of first power amplifier circuit 302, second power amplifier circuit 303, third power amplifier circuit 305, second power amplifier circuit 303, and first power amplifier circuit 302, so that the waveform of the stepped wave output from the first output pin 301 is as follows: Figure 10As shown, this is a stepped wave including three voltage levels. Since the stepped wave output from the second output pin 306 has the same frequency and amplitude as the stepped wave output from the first output pin 301, but differs in phase by half a cycle, the stepped wave output from the second output pin 306 is also a stepped wave including three voltage levels. When the voltage is output to the first output pin 301 or the second output pin 306 in the order of the first power amplifier circuit 302, the second power amplifier circuit 303, the third power amplifier circuit 305, the second power amplifier circuit 303, and the first power amplifier circuit 302, the ratio of the time length of the output voltage of each power amplifier circuit is equal to 1:1:2:1:1, making the waveform of the stepped wave output from the first output pin 301 and the second output pin 306 closer to a sine wave, ensuring that the transmitted signal output by the power amplifier 300 includes fewer high-order harmonics.

[0121] See Figure 14 In the second power amplifier circuit 303, the input terminal of the first inverter C3 is connected to the first signal output terminal Switch3 of the logic control module 200, the output terminal of the first inverter C3 is connected to the gate of the first PMOS transistor Q5, the source of the first PMOS transistor Q5 is connected to the driving power supply V2, and the drain of the first PMOS transistor Q5 is connected to the first output pin 301; the gate of the first NMOS transistor Q8 is connected to the first signal output terminal Switch3, the source of the first NMOS transistor Q8 is grounded, and the drain of the first NMOS transistor Q8 is connected to the second output pin 301. Pin 306 is connected; the input of the second inverter C4 is connected to the second signal output terminal Switch4 of the logic control section, the output of the second inverter C2 is connected to the gate of the second PMOS transistor Q7, the source of the second PMOS transistor Q7 is connected to the drive power supply V2, and the drain of the second PMOS transistor Q7 is connected to the second output pin 306; the gate of the second NMOS transistor Q6 is connected to the second signal output terminal Switch4, the source of the second NMOS transistor Q6 is grounded, and the drain of the second NMOS transistor Q6 is connected to the first output pin 301.

[0122] See Figure 14In the third power amplifier circuit 305, the input terminal of the first inverter C5 is connected to the first signal output terminal Switch5 of the logic control module 200, the output terminal of the first inverter C5 is connected to the gate of the first PMOS transistor Q9, the source of the first PMOS transistor Q9 is connected to the driving power supply V3, and the drain of the first PMOS transistor Q9 is connected to the first output pin 301; the gate of the first NMOS transistor Q12 is connected to the first signal output terminal Switch5, the source of the first NMOS transistor Q12 is grounded, and the drain of the first NMOS transistor Q12 is connected to the second output pin. Pin 306 is connected; the input of the second inverter C6 is connected to the second signal output terminal Switch6 of the logic control section, the output of the second inverter C6 is connected to the gate of the second PMOS transistor Q11, the source of the second PMOS transistor Q11 is connected to the drive power supply V3, and the drain of the second PMOS transistor Q11 is connected to the second output pin 306; the gate of the second NMOS transistor Q10 is connected to the second signal output terminal Switch6, the source of the second NMOS transistor Q10 is grounded, and the drain of the second NMOS transistor Q10 is connected to the first output pin 301.

[0123] Figure 15 This is a schematic diagram of the logic control signals output by the logic control module 200 provided in this embodiment. The logic control module 200 outputs rectangular waves at signal output terminals Switch1 to Switch6, and the signal timing at each signal output terminal is as follows: Figure 15 As shown in the diagram. The phase difference between the rectangular waves output by Switch1 and Switch4 is Tc / 2; the phase difference between the rectangular waves output by Switch2 and Switch5 is Tc / 2; and the phase difference between the rectangular waves output by Switch3 and Switch6 is Tc / 2. Tc is the period of the logic control signal, for example, Tc = 1 / 13.56MHz.

[0124] The following is combined Figure 14 The power amplifier 300 shown Figure 10 The stepped wave shown and Figure 15 The logic control signals shown provide a further detailed description of the power amplifier 300 in this embodiment. See also Figure 15 The logic control signals shown indicate that within one cycle of the carrier wave output by the power amplifier 300, the transistors in the power amplifier 300 respond to the logic control signals output by the logic control module 200 by switching on and off in the following order:

[0125] (1) With Switch1 set high and all other signal outputs set to 0, the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned on, while all other PMOS and NMOS transistors are turned off. At this time, the first output pin 301 outputs V1, and the second output pin 306 outputs 0. This process lasts for Tc / 12, where Tc is the period of one carrier wave output by the power amplifier 300. Second.

[0126] (2) When the signal output terminal Switch3 is set high, all other signal output terminals are set to 0, making the first PMOS transistor Q5 and the first NMOS transistor Q8 turn on, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs V2, and the second output pin 306 outputs 0. This process lasts for Tc / 12.

[0127] (3) When the signal output terminal Switch5 is set high, all other signal output terminals are set to 0, making the first PMOS transistor Q9 and the first NMOS transistor Q12 conduct, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs V3, and the second output pin 306 outputs 0. This process is maintained for a duration of Tc / 6.

[0128] (4) When the signal output terminal Switch3 is set high, all other signal output terminals are set to 0, making the first PMOS transistor Q5 and the first NMOS transistor Q8 turn on, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs V2, and the second output pin 306 outputs 0. This process lasts for Tc / 12.

[0129] (5) When the signal output terminal Switch1 is set high, all other signal output terminals are set to 0, making the first PMOS transistor Q1 and the first NMOS transistor Q4 turn on, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs V1, and the second output pin 306 outputs 0. This process lasts for Tc / 12.

[0130] (6) When the signal output terminal Switch2 is set high, all other signal output terminals are set to 0, making the second PMOS transistor Q3 and the second NMOS transistor Q2 conduct, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs 0, and the second output pin 306 outputs V1. This process lasts for Tc / 12.

[0131] (7) When the signal output terminal Switch4 is set high, all other signal output terminals are set to 0, making the second PMOS transistor Q7 and the second NMOS transistor Q6 conduct, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs 0, and the second output pin 306 outputs V2. This process lasts for Tc / 12.

[0132] (8) When the signal output terminal Switch6 is set high, all other signal output terminals are set to 0, making the second PMOS transistor Q11 and the second NMOS transistor Q10 conduct, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs 0, and the second output pin 306 outputs V3. This process lasts for Tc / 6.

[0133] (9) When the signal output terminal Switch4 is set high, all other signal output terminals are set to 0, making the second PMOS transistor Q7 and the second NMOS transistor Q6 conduct, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs 0, and the second output pin 306 outputs V2. This process lasts for Tc / 12.

[0134] (10) When the signal output terminal Switch2 is set high, all other signal output terminals are set to 0, making the second PMOS transistor Q3 and the second NMOS transistor Q2 conduct, while all other PMOS transistors and NMOS transistors are turned off. At this time, the first output pin 301 outputs 0, and the second output pin 306 outputs V1. This process lasts for Tc / 12.

[0135] In power amplifier 300, each transistor responds to a logic control signal and switches on and off according to steps (1) to (10) above, causing the first output pin 301 and the second output pin 306 to output as shown in the figure. Figure 7 The stepped wave shown.

[0136] Figure 16 This is a schematic diagram of an antenna signal spectrum distribution provided in an embodiment of this application. Under the conditions of the same antenna, the same maximum output voltage, and the same matching impedance, when using an existing scheme to suppress higher-order harmonics through an EMC filter, the signal spectrum distribution at the antenna is as follows: Figure 16 Curve 161 in the middle, using Figure 13 When the power amplifier is used to suppress higher-order harmonics, the signal spectrum distribution at the antenna is as shown. Figure 16 Curve 162 in the text. (The rest of the text appears to be a list of characters and symbols, possibly related to curve Figure 16 As can be seen, the carrier transmission frequency amplitude of NFCC (i.e., the highest points of curves 161 and 162) basically overlap, indicating that the NFC transmission power of the two schemes mentioned above is basically suppressed, and the basic functions of NFC are not affected.

[0137] use Figure 14When the power amplifier is used to suppress higher harmonics, the amplitudes at the 7th harmonic (149.16MHz) and 13th harmonic (176.28MHz) are larger than those of the existing scheme. However, the amplitudes of these two harmonics are 40dB smaller than the amplitude of the 13.56MHz carrier wave, which is less than 1 / 100 of the carrier wave amplitude. This indicates that the amplitudes of these two harmonic components are small and will not cause serious EMC problems at the antenna. Apart from these two harmonics, the other harmonics are basically similar between the two schemes. Figure 14 The power amplifier scheme shown meets the requirements for suppressing higher-order harmonics.

[0138] This application also provides a chip that includes the power amplifier 300 in any of the above embodiments.

[0139] Optionally, in one implementation, the chip provided in this application embodiment is a Near Field Communication controller (NFCC) chip, which is used to transmit and receive NFC signals through a connected antenna. That is, the power amplifier 300 in the above embodiment can be applied to the NFCC chip.

[0140] This application also provides a terminal device, which includes the chip described in the above embodiments. Figure 7 This is a schematic diagram of a terminal device provided in an embodiment of this application. See also... Figure 17 The terminal device 170 includes a chip 171, a matching circuit 172, and an antenna 100. The chip 171 includes a power amplifier 300. The power amplifier 300 is connected to the matching circuit 172, and the matching circuit 172 is connected to the antenna 100. The power amplifier 300 transmits a transmission signal to the matching circuit 172 through a first output pin 301, a second output pin 306, and a ground pin 304. After passing through the matching circuit 172, the amplitude of the transmission signal increases, thereby increasing the communication distance of the antenna 100. Based on the transmission signal transmitted by the matching circuit 172, the antenna 100 transmits an NFC signal.

[0141] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0142] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0143] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power amplifier applied to a chip, the power amplifier comprising: First output pin, first power amplifier circuit, and second power amplifier circuit; The first output terminal of the first power amplifier circuit and the first output terminal of the second power amplifier circuit are respectively connected to the first output pin; The control terminals of the first power amplifier circuit and the second power amplifier circuit are respectively connected to the logic control module in the chip; The first voltage output by the first power amplifier circuit is less than the second voltage output by the second power amplifier circuit; Under the control of the logic control module, the first power amplifier circuit and the second power amplifier circuit alternately output the first voltage and the second voltage to the first output pin, so that the first output pin outputs a first stepped wave for driving the antenna, wherein the first stepped wave includes two voltage levels with amplitudes of the first voltage and the second voltage; Under the control of the logic control module, the first power amplifier circuit and the second power amplifier circuit alternately or simultaneously output the first voltage and the second voltage to the first output pin, so that the first output pin outputs a second stepped wave for driving the antenna, wherein the second stepped wave includes three voltage levels with amplitudes of the first voltage, the difference between the second voltage and the first voltage, and the second voltage.

2. The power amplifier according to claim 1, wherein, The power amplifier further includes: at least one third power amplifier circuit; The first output terminal of each of the third power amplifier circuits is connected to the first output pin; The control terminal of each of the third power amplifier circuits is connected to the logic control module; Different third power amplifier circuits output different third voltages, and these third voltages are different from the first voltage and the second voltage. Under the control of the logic control module, the first power amplifier circuit, the second power amplifier circuit, and the at least one third power amplifier circuit sequentially output voltages to the first output pin in the order of output voltage from low to high and then from high to low, so that the first output pin outputs a third-step wave for driving the antenna, wherein the third-step wave includes at least three voltage levels with amplitudes of the first voltage, the second voltage, and at least one of the third voltages.

3. The power amplifier according to any one of claims 1 to 2, wherein, The power amplifier further includes: a second output pin; The second output terminal of each power amplifier circuit in the power amplifier circuit group is connected to the second output pin respectively. The power amplifier circuit group includes the first power amplifier circuit and the second power amplifier circuit, or the first power amplifier circuit, the second power amplifier circuit and at least one third power amplifier circuit. Under the control of the logic control module, each power amplifier circuit in the power amplifier circuit group outputs a voltage to the second output pin, so that the second output pin outputs a fourth step wave for driving the antenna. The fourth step wave has the same frequency and amplitude as the step wave output by the first output pin, and the phase difference is half a cycle.

4. The power amplifier according to claim 3, wherein, Each power amplifier circuit in the power amplifier circuit group includes: a first switching circuit, a second switching circuit, and a driving power supply, wherein the output voltage of the driving power supply in the first power amplifier circuit, the second power amplifier circuit, and the third power amplifier circuit is different. The first switching circuit and the second switching circuit are respectively connected to the driving power supply; The first switching circuit is connected to the first output pin, and the second switching circuit is connected to the second output pin; When the first switching circuit is turned on under the control of the logic control module, the second switching circuit is turned off under the control of the logic control module. The first switching circuit connects the driving power supply to the first output pin so that the first output pin outputs a voltage equal to the output voltage of the driving power supply. When the second switching circuit is turned on under the control of the logic control module, the first switching circuit is turned off under the control of the logic control module. The second switching circuit connects the driving power supply to the second output pin so that the second output pin outputs a voltage equal to the output voltage of the driving power supply.

5. The power amplifier according to claim 4, wherein, The first switching circuit includes: a first P-channel metal-oxide-semiconductor PMOS transistor, a first N-channel metal-oxide-semiconductor NMOS transistor, and a first inverter; The second switching circuit includes: a second PMOS transistor, a second NMOS transistor, and a second inverter; The input terminal of the first inverter is connected to the first signal output terminal of the logic control module, the output terminal of the first inverter is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to the driving power supply, and the drain of the first PMOS transistor is connected to the first output pin. The gate of the first NMOS transistor is connected to the first signal output terminal, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the second output pin. The input terminal of the second inverter is connected to the second signal output terminal of the logic control module, the output terminal of the second inverter is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the driving power supply, and the drain of the second PMOS transistor is connected to the second output pin. The gate of the second NMOS transistor is connected to the second signal output terminal, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the first output pin.

6. The power amplifier according to claim 5, wherein, The power amplifier further includes: a ground pin; The grounding pin is connected to the source of the first NMOS transistor and the source of the second NMOS transistor in each power amplifier circuit of the power amplifier circuit group. The grounding pin is used to provide a reference ground voltage.

7. The power amplifier according to claim 2, wherein, The power amplifier includes one of the third power amplifier circuits; The ratio of the first voltage, the second voltage, and the third voltage is 0.2679:0.7321:

1.

8. The power amplifier according to claim 7, wherein, Within one logic control cycle of the logic control module, the ratio of the time lengths during which the first power amplifier circuit, the second power amplifier circuit, and the third power amplifier circuit output voltage to the first output pin in the order of first power amplifier circuit, second power amplifier circuit, third power amplifier circuit, second power amplifier circuit, and first power amplifier circuit, under the control of the logic control module, is equal to 1:1:2:1:

1.

9. A chip, wherein, Includes the power amplifier as described in any one of claims 1 to 8 above.

10. The chip according to claim 9, wherein, The chip is a near-field communication (NFC) controller chip, which is used to transmit and receive NFC signals through a connected antenna.

11. A terminal device, wherein, The terminal device includes the chip as described in claim 9 or 10 above.

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