NAND Gate Tree Structure

Abstract

The present disclosure provides a NAND gate tree structure, the NAND gate tree structure includes: a plurality of NAND gates; wherein the first input end of the first NAND gate is connected to the first input signal, the output end of the first NAND gate is used as the output of the entire NAND gate tree structure, and the second input end of the first NAND gate is connected to the output end of the second NAND gate. The advantage of the present disclosure is that in order to achieve the area increase without the ring oscillator, the present disclosure divides the input signal into two types: for NAND gate tree measurement and for the ring oscillator. In both cases, the NAND gate circuit contained in the input and output terminals is used. The output results in both cases can be obtained. Therefore, the present disclosure does not need to enlarge the size of the product, which is conducive to the miniaturization and cost control of semiconductor devices.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a NAND gate tree structure and a testing method using the same. Background Art

[0002] In ultra-fine semiconductor processes, since AC performance is important, it is often necessary to use a ring oscillator circuit for measurement and management, because the DC parameter values ​​and AC performance of ultra-fine processes and semiconductor components are not equal. However, in order to test AC performance, it is sometimes necessary to leave extra space for the measurement circuit in the product, and at the same time, there must be extra pads. Therefore, the size of the product is enlarged, which is not conducive to the miniaturization and cost control of semiconductor devices. Summary of the invention

[0003] The purpose of the present disclosure is to propose a NAND gate tree structure to address the deficiencies of the above-mentioned prior art, and the purpose is achieved through the following technical solutions.

[0004] The first aspect of the present disclosure proposes a NAND gate tree structure, comprising:

[0005] Multiple NAND gates; among them,

[0006] The first input end of the first NAND gate is connected to the first input signal, the output end of the first NAND gate serves as the output of the entire NAND gate tree structure, and the second input end of the first NAND gate is connected to the output end of the second NAND gate.

[0007] A second aspect of the present disclosure provides a NAND gate tree structure, comprising:

[0008] Multiple NAND gates;

[0009] The first input end of the first NAND gate is connected to the first input signal, the output end of the first NAND gate serves as the output of the entire NAND gate tree structure, the second input end of the first NAND gate is connected to the output end of the first delay unit, and the input end of the delay unit is connected to the output end of the second NAND gate.

[0010] A third aspect of the present disclosure provides a semiconductor device group, which includes the NAND gate tree structure according to the first aspect or the second aspect.

[0011] The advantage of the present disclosure is that, in order to achieve the area increase without the ring oscillator, the present disclosure divides the input signal into two types: for NAND tree measurement and for the ring oscillator. In both cases, the NAND circuit included in the input and output terminals is used. The output results in both cases can be obtained. Therefore, the present disclosure does not need to increase the size of the product, which is conducive to the miniaturization and cost reduction of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0013] Figure 1 A schematic diagram of a NAND gate tree structure for verifying the connection status of an input signal terminal in the first embodiment of the present disclosure;

[0014] Figure 2 A schematic diagram showing output changes caused by input signals during the measurement process;

[0015] Figure 3 This is a schematic diagram of a logic circuit inside a product using a standard NAND gate tree structure in the second embodiment of the present disclosure;

[0016] Figure 4 is an enlarged schematic diagram of a delay unit structure used in a second embodiment of the present disclosure;

[0017] Figure 5 Schematic diagram of NAND tree verification. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0019] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0020] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0021] In the prior art, a ring oscillator is used to measure the AC performance of a semiconductor element. This type of ring oscillator is formed inside a product or in a gap around a product. The AC performance measured by the ring oscillator formed in this way is used as an indicator for managing the process after performing work consistent with the product performance. Also, in order to measure these ring oscillators, additional space is required, and additional pads are also required.

[0022] As the process becomes more sophisticated, the AC performance of transistors measured by the scribe lane cannot represent product performance problems. Therefore, it is common to add special test circuits inside the product for evaluation. In this case, space needs to be reserved according to the addition inside the product. In particular, the test circuit implemented in this way can be measured at the wafer-level evaluation stage, and the feedback time will be delayed.

[0023] The ring oscillators of the management process are formed on the additional area and electrically connected on the input and output pads. The same input and output pads are additional pads required to connect the ring oscillators formed in the additional area, or additional areas required to connect the existing input and output ports. The formation of such additional areas and additional pads has the problem of increasing the product area. For all semiconductor memory products, there is a NAND circuit inside the input and output pads.

[0024] Figure 1 This is the first embodiment of the present disclosure. In order to verify the NAND tree structure of the input signal terminal connection status, the present disclosure connects the NAND circuit (NAND gate circuit) built into the product pad with the NAND circuit, and uses the NAND tree structure to verify the input and output pad design. Figure 1 In the embodiment, there are 20 NAND gates in total. However, those skilled in the art will appreciate that the inventive concept of the present disclosure is not limited to 20 NAND gates, and a structure with a greater or lesser number of NAND gates can implement the present disclosure. Figure 1 In the figure, the first input of the top NAND gate is connected to the input signal INPUT_00, and its output is used as the output of the entire NAND gate tree structure. The second input of the first NAND gate is connected to the output of the second NAND gate below. The first input of the second NAND gate is connected to the input signal INPUT_01, and its output is connected to the second input of the first NAND gate. The second input of the second NAND gate is connected to the output of the third NAND gate. By analogy, the connection methods of the 2nd to 19th NAND gates are the same, and the first inputs are connected to the input signals INPUT_01 to INPUT_18 respectively. The first and second inputs of the 20th NAND gate are both connected to the input signal INPUT_19, and its output is connected to the second input of the 19th NAND gate.

[0025] Thus, in the first embodiment, the NAND circuit confirms the connection status of the input / output pads (I / O Pads), connects the NAND circuits to form a NAND tree, and measures the output signal according to the change of the input signal. Therefore, when the present disclosure connects the NAND circuits inside the input / output pads and uses them as a ring oscillator for process management, the process can be directly monitored inside the product. In particular, this measurement circuit does not require an additional area and an additional pad, and can be implemented without increasing the area.

[0026] Figure 2 In the first embodiment, the output changes caused by the input signal are displayed during the measurement process. Among them, the first column on the left represents the pad input and output signals, OUT represents the output signal, INPUT_00 to INPUT_19 represent the input signal, the letter L represents the low level, the letter H represents the high level, and 1 and 0 represent the value of the input signal. In this way, the NAND tree loop can verify the performance of the product. The NAND tree loop constructed in this way is not completed by the input and output pad connection verification in a simple wafer-level test, but in the DC test stage before the wafer-level test, so it is necessary to verify the AC characteristics in advance.

[0027] Figure 3 It is a logic circuit inside the product using the standard NAND Tree structure. Figure 3 In the embodiment, there are 20 NAND gates in total. However, those skilled in the art will appreciate that the inventive concept of the present disclosure is not limited to 20 NAND gates, and a structure with a greater or lesser number of NAND gates can implement the present disclosure. Figure 3 In the figure, the first input of the top NAND gate is connected to the input signal INPUT_00, and its output is used as the output of the entire NAND gate tree structure. The second input of the first NAND gate is connected to the output of the first delay unit, and the input of the first delay unit is connected to the output of the second NAND gate. The first input of the second NAND gate is connected to the input signal INPUT_01, and its output is used as the input of the first delay unit. The second input of the second NAND gate is connected to the output of the second delay unit, and the input of the second delay unit is connected to the output of the third NAND gate. By analogy, the connection methods of the 2nd to 19th NAND gates are the same, and the first inputs are connected to the input signals INPUT_01 to INPUT_18 respectively. The first input and second input of the 20th NAND gate are both connected to the input signal INPUT_19, and its output is connected to the 19th delay unit.

[0028] In the second embodiment, the formula result of the connected ring oscillator appears. Like this, when the NAND inside the input terminal and the logic circuit inside the product are woven into a NAND tree structure, NAND tree verification can be performed. At the same time, when the input signal at all input terminals is 1, the ring oscillator can be used to start and test the AC performance.

[0029] like Figure 4 FIG. 1 is an enlarged schematic diagram of the delay unit structure used in the second embodiment of the present disclosure. Figure 4 As shown, the delay unit used in the present disclosure includes two NOT gates / NAND gates / NOR gates connected in series. A resistor and a capacitor are connected between the first NOT gate / NAND gate / NOR gate and the second NOT gate / NAND gate / NOR gate. One end of the resistor is connected to the output end of the first NOT gate / NAND gate / NOR gate, and the other end is connected to the input end of the second NOT gate / NAND gate / NOR gate; one end of the first capacitor is connected to the output end of the first NOT gate / NAND gate / NOR gate, and the other end is grounded, VDD or other signal nodes; one end of the second capacitor is connected to the input end of the second NOT gate / NAND gate / NOR gate, and the other end is grounded, VDD or other signal nodes. τ d1 and τ d2 Represent the delay time of the NAND gate and the delay unit respectively.

[0030] like Figure 5 As shown, in NAND tree verification, if the input signals at the input and output terminals are switched in sequence as 1 and 0, the switched values ​​are detected in sequence according to the signals at the output terminals. In addition, in order to measure the AC performance, the ring oscillator is used. If all input signals are set to 1, the NAND circuit will measure the frequency of the output signal at the output terminal according to the inverter circuit operation. When the output frequency of the output terminal is high, the AC performance of the management process can be evaluated by measuring it using the period method. Figure 5 In the figure, OUTPUT is the output signal of the NAND gate tree structure, and INPUT_x-1, INPUT_x, and INPUT_x+1 are all input signals.

[0031] In order to achieve the area increase without the ring oscillator, the present disclosure divides the input signal into two types: NAND tree measurement and ring oscillator. In both cases, the NAND circuit included in the existing input and output terminals is used. The output results in both cases can be obtained. Therefore, the present disclosure does not need to increase the size of the product, which is conducive to the miniaturization and cost reduction of semiconductor devices.

[0032] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0033] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A NAND gate tree structure for ultra-micro semiconductor testing, characterized in that: include: Multiple NAND gates; The first input end of the first NAND gate is connected to the first input signal, the output end of the first NAND gate serves as the output of the entire NAND gate tree structure, the second input end of the first NAND gate is connected to the output end of the second NAND gate, the first input end of the second NAND gate is connected to the second input signal, and the second input end is connected to the output end of the third NAND gate, the multiple NAND gates are N NAND gates, the second NAND gate is connected to the N-1th NAND gate in the same manner, the first input end and the second input end of the N-1th NAND gate are both connected to the input signal, and the output end is connected to the second input end of the N-1th NAND gate; The second input terminal of the first NAND gate is connected to the output terminal of the first delay unit, and the input terminal of the delay unit is connected to the output terminal of the second NAND gate; The input terminals of all NAND gates are set to a high level state to activate the internal logic circuit of the NAND gate tree structure, and the frequency of the output signal at the output terminal is measured to evaluate the AC performance.

2. The NAND gate tree structure for ultra-micro semiconductor testing according to claim 1, characterized in that: The first input terminal of the second NAND gate is connected to the second input signal, the second input terminal is connected to the output terminal of the second delay unit, and the input terminal of the second delay unit is connected to the output terminal of the third NAND gate.

3. The NAND gate tree structure for ultra-micro semiconductor testing according to claim 1 or 2, characterized in that: The plurality of NAND gates are N NAND gates, and the connection mode from the second NAND gate to the N-1th NAND gate is the same.

4. The NAND gate tree structure for ultra-micro semiconductor testing according to claim 3, characterized in that: The first input terminal and the second input terminal of the Nth NAND gate are both connected to the input signal, and the output terminal thereof is connected to the N-1th delay unit.

5. The NAND gate tree structure for ultra-micro semiconductor testing according to claim 4, characterized in that: The delay unit comprises two NOT gates / NAND gates / NOR gates connected in series, and a resistor and a capacitor are connected between the first NOT gate / NAND gate / NOR gate and the second NOT gate / NAND gate / NOR gate; one end of the resistor is connected to the output end of the first NOT gate / NAND gate / NOR gate, and the other end is connected to the input end of the second NOT gate / NAND gate / NOR gate; one end of the first capacitor is connected to the output end of the first NOT gate / NAND gate / NOR gate, and the other end is grounded, VDD or other signal nodes; one end of the second capacitor is connected to the input end of the second NOT gate / NAND gate / NOR gate, and the other end is grounded, VDD or other signal nodes.

6. A semiconductor device assembly, characterized in that: It comprises a NAND gate tree structure for ultra-micro semiconductor testing according to any one of claims 1-5.

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