A leadless, solderless surface mount electronic component

Abstract

The application provides a pinless and solderless patch electronic component, relates to the technical field of electronic components, and solves the problems of small current flow, poor anti-combined wave capability, poor voltage resistance, high cost and complex production of the patch electronic component, and comprises a base body; the upper electrode surface is composed of an upper electrode layer, an auxiliary electrode layer and an upper adhering electrode; the bottom of the base body is provided with a lower electrode surface; the lower electrode surface is composed of a lower electrode layer and a lower adhering electrode; the top of the upper electrode surface is covered with an upper insulating layer; the bottom of the lower electrode surface is covered with a lower insulating layer; and a separation gap is arranged between the upper adhering electrode and the lower electrode layer. The device can increase the effective area of the electrode, improve the current flow and the anti-combined wave capability, and adopts the pinless or pinless and solderless process technology, so that the production environment meets the environmental protection requirements, the production process is simpler, and the cost is obviously reduced.

Description

Technical Field

[0001] This invention belongs to the field of electronic component technology, and more specifically, relates to a leadless, solderless surface-mount electronic component. Background Technology

[0002] Currently, there are four manufacturing methods for surface mount electronic components: solder-encapsulated two-lead surface mount components, single-lead circular surface mount components, plastic-encapsulated surface mount components, and multilayer surface mount components. Among them, solder-encapsulated two-lead surface mount components are manufactured using traditional soldering and encapsulation methods, with the two leads arranged in a stepped shape, and can be produced using traditional equipment and processes. Single-lead circular surface mount components have electrodes on both sides of the substrate, with insulating material on the edges of the electrodes. The upper electrode is soldered with a flat lead support, and the lower electrode and the lead form two bonding surfaces. Plastic-encapsulated surface mount components are manufactured using the same process as diode plastic-encapsulated surface mount components, using upper and lower support frames soldered together and then plastic-encapsulated. Multilayer surface mount components use a multilayer electrode process, enabling product miniaturization.

[0003] For example, patent application number 201721689007.4 discloses a surface-mount zinc oxide varistor, including a substrate, electrodes, an auxiliary electrode, and an insulating layer. The substrate is high-purity zinc oxide ceramic. Two electrodes are printed on both sides of the lower surface of the substrate. One auxiliary electrode is printed on the upper surface of the substrate. A gap is left between the edge of the electrode and the edge of the substrate. A gap is left between the two electrodes. The insulating layer is printed on the outer annular edge of the lower surface of the substrate, extending inward to the edge of the electrode and upward to the side surface of the substrate. This invention is small in size, lightweight, highly reliable, and has low manufacturing cost. At the same time, this invention completely subverts the structure of traditional varistors in terms of structural distribution, changing the original two electrodes sandwiched between two substrates to two electrodes distributed on both sides of the same surface, solving the need for automated surface mounting and making semi-automation and full automation of the product easier to achieve.

[0004] For example, patent application number 201822145675.1 discloses a multi-electrode surface-mount varistor assembly, including a varistor substrate and electrodes. One bottom surface of the cuboid varistor substrate has an isolation groove. A first electrode and a second electrode are respectively located on the bottom surface divided into two parts by the isolation groove. A third electrode is located on the opposite bottom surface. The vertical projection of the third electrode onto the plane containing the first and second electrodes overlaps with the first and second electrodes. Through the design of the isolation groove and multiple electrodes, the entire varistor assembly is equivalent to two varistors connected in parallel. This transforms the commonly used two-electrode facing design of varistors into a structure where the conductive electrodes are on the same plane, ensuring a perfect match between the varistor's input electrodes and the circuit board plane. This makes it more suitable for soldering surface-mount varistors, facilitating the application of surface-mount varistor assemblies and providing greater adjustability in the corresponding circuit design. Both of the above solutions use the same-surface electrode design. The varistor voltage of this type of product is determined by the gap between the two electrodes. The current density is uneven and inconsistent, resulting in low current flow and poor reliability.

[0005] Based on the above, the inventors have discovered the following problems: the effective electrode area of ​​current wireless and solderless surface-mount electronic components is small, and the current density is uneven and inconsistent, resulting in low product current and poor reliability; moreover, due to miniaturization, the creepage distance between the two electrodes of multilayer surface-mount electronic components is short, so the anti-combination wave capability is poor, and the use of precious metals for the inner electrodes is costly, requires large investment, and the production process is relatively complex.

[0006] Therefore, in view of this, we have studied and improved the structure and shortcomings of existing products to provide a leadless, solderless surface-mount electronic component in order to achieve greater practical value. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides a leadless, solderless surface-mount electronic component, which solves the problems of low current carrying capacity, poor resistance to combined waves, low voltage withstand, high cost, and complex manufacturing of current surface-mount electronic components.

[0008] The purpose and effect of this invention—a leadless, solderless surface-mount electronic component—are achieved through the following specific technical means:

[0009] A leadless, solderless surface-mount electronic component includes a substrate; a top electrode surface is provided on the top of the substrate; the top electrode surface is composed of an upper electrode layer, an auxiliary electrode layer, and an upper bonding electrode; a bottom electrode surface is provided on the bottom of the substrate; the bottom electrode surface is composed of a lower electrode layer and a lower bonding electrode; an upper insulating layer covers the top of the upper electrode surface; a lower insulating layer covers the bottom of the lower electrode surface; and an isolation gap is provided between the upper bonding electrode and the lower electrode layer.

[0010] Furthermore, the substrate is one of a varistor, a thermistor, or a ceramic capacitor, and the upper electrode surface and the lower electrode surface are one or more layers of electrodes made by screen printing, spraying, dipping, rolling, sputtering, or electroplating.

[0011] Furthermore, the upper electrode layer, the auxiliary electrode layer, and the upper bonding electrode together form a J-shape.

[0012] Furthermore, both the upper and lower insulating layers are made of inorganic glass or organic resin, and are manufactured by screen printing or spraying processes.

[0013] Furthermore, the width of the isolation gap is greater than the thickness of the substrate.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] This invention consists of a substrate, electrodes, and insulating materials. By using an auxiliary electrode to extend one electrode to the other side of the substrate, two bonding surfaces are formed on the same side, which serve as the two electrodes of the component and are soldered to the PCB board. This enables automated surface mount installation, increases the effective electrode area, improves current carrying capacity, and enhances the resistance to combined waves. Furthermore, the use of leadless or pinless and solderless processes makes the production environment meet environmental protection requirements, simplifies the production process, and significantly reduces costs. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the top-side structure after assembly in Embodiment 1 of the present invention.

[0017] Figure 2 This is a schematic diagram of the split-up tilt axis structure in Embodiment 1 of the present invention.

[0018] Figure 3 This is a bottom view schematic diagram of the assembled structure in Embodiment 1 of the present invention.

[0019] Figure 4 This is a schematic diagram of the assembled tilt axis side structure in Embodiment 2 of the present invention.

[0020] Figure 5 This is a schematic diagram of the split-up tilt axis structure in Embodiment 2 of the present invention.

[0021] Figure 6 This is a schematic diagram of the assembled tilt axis side structure in Embodiment 3 of the present invention.

[0022] Figure 7 This is a schematic diagram of the assembled tilt axis side structure in Embodiment 4 of the present invention.

[0023] In the diagram, the correspondence between component names and drawing numbers is as follows:

[0024] 1. Substrate; 2. Upper electrode surface; 201. Upper electrode layer; 202. Auxiliary electrode layer; 203. Upper bonding electrode; 3. Lower electrode surface; 301. Lower electrode layer; 302. Lower bonding electrode; 4. Upper insulating layer; 5. Lower insulating layer; 6. Isolation gap. Detailed Implementation

[0025] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0026] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] Example 1:

[0029] As attached Figure 1 To be continued Figure 3 As shown:

[0030] This invention provides a leadless, solderless surface-mount electronic component, comprising a substrate 1; an upper electrode surface 2 is disposed on the top of the substrate 1; the upper electrode surface 2 is composed of an upper electrode layer 201, an auxiliary electrode layer 202 and an upper bonding electrode 203; a lower electrode surface 3 is disposed on the bottom of the substrate 1; the lower electrode surface 3 is composed of a lower electrode layer 301 and a lower bonding electrode 302; an upper insulating layer 4 is covered on the top of the upper electrode surface 2; a lower insulating layer 5 is covered on the bottom of the lower electrode surface 3; and an isolation gap 6 is disposed between the upper bonding electrode 203 and the lower electrode layer 301.

[0031] The substrate 1 is a varistor, and the upper electrode surface 201, the upper bonding electrode, and the lower electrode surface 3 are electrodes made by screen printing.

[0032] The auxiliary electrode layer 202 is a multilayer electrode fabricated by sputtering and electroplating.

[0033] The upper electrode layer 201, the auxiliary electrode layer 202, and the upper bonding electrode 203 together form a J-shape.

[0034] The upper insulating layer 4 and the lower insulating layer 5 are both inorganic glass layers, and the upper insulating layer 4 and the lower insulating layer 5 are made by screen printing.

[0035] The width of the isolation gap 6 is greater than the thickness of the substrate 1.

[0036] The lower insulating layer 5 also has a window on its right side that corresponds to the bottom right side of the lower bonding electrode 302.

[0037] The specific usage and function of this embodiment are as follows:

[0038] When fabricating surface-mount electronic components using this method, an upper electrode layer 201, an upper bonding electrode 203, and a lower electrode surface 3 are first fabricated on the top and bottom of a substrate 1 using a screen printing process. The upper electrode layer 201 and the lower electrode layer 301 are positioned on the top and bottom surfaces of the substrate 1, respectively. The upper bonding electrode 203 covers the bottom left side of the substrate 1, and the lower bonding electrode 302 covers the bottom right side of the substrate 1. At this time, an isolation gap 6 appears between the upper bonding electrode 203 and the lower electrode layer 301 to separate the two electrodes. Then, an insulating layer is fabricated using a screen printing process. The left side of the upper insulating layer 4 covers the left side of the upper electrode layer 201, and the upper electrode layer... The left side of the upper electrode layer 201 is exposed by 0.1-5mm. The edges of the other sides of the upper insulating layer 4 cover the edges of the other sides of the upper electrode layer 201. The left side of the lower insulating layer 5 covers the right side of the upper bonding electrode 203, and the upper bonding electrode 203 is exposed by 0.1-5mm. The edges of the other sides of the lower insulating layer 5 cover the edges of the other sides of the lower electrode layer 301. Then, a welding window is opened on the lower bonding electrode 302. The auxiliary electrode layer 202 is then covered on the left side of the substrate 1 by sputtering and electroplating. The two bonding electrodes are used as surface mount components and are welded to the PCB board respectively. The surface mount varistor made by the above method has a strong anti-combination wave capability.

[0039] Example 2:

[0040] As attached Figure 4 To be continued Figure 5 As shown:

[0041] This invention provides a leadless, solderless surface-mount electronic component, comprising a substrate 1; an upper electrode surface 2 is disposed on the top of the substrate 1; the upper electrode surface 2 is composed of an upper electrode layer 201, an auxiliary electrode layer 202 and an upper bonding electrode 203; a lower electrode surface 3 is disposed on the bottom of the substrate 1; the lower electrode surface 3 is composed of a lower electrode layer 301 and a lower bonding electrode 302; an upper insulating layer 4 is covered on the top of the upper electrode surface 2; a lower insulating layer 5 is covered on the bottom of the lower electrode surface 3; and an isolation gap 6 is disposed between the upper bonding electrode 203 and the lower electrode layer 301.

[0042] The substrate 1 is a positive temperature coefficient thermistor, and the upper electrode surfaces 201 and 203 and the lower electrode surface 3 are two layers of electrodes fabricated by screen printing.

[0043] The auxiliary electrode layer 202 is a multilayer electrode fabricated by sputtering.

[0044] The upper electrode layer 201, the auxiliary electrode layer 202, and the upper bonding electrode 203 together form a J-shape.

[0045] Both the upper insulating layer 4 and the lower insulating layer 5 are organic resin layers.

[0046] The width of the isolation gap 6 is greater than the thickness of the substrate 1.

[0047] The specific usage and function of this embodiment are as follows:

[0048] When fabricating surface-mount electronic components using this method, an upper electrode surface 2 and a lower electrode surface 3 are first formed on the top and bottom of a substrate 1 using electroplating. The upper electrode layer 201 and the lower electrode layer 301 are positioned on the top and bottom surfaces of the substrate 1, respectively. The upper bonding electrode 203 covers the bottom left side of the substrate 1, and the lower bonding electrode 302 covers the bottom right side of the substrate 1. An isolation gap 6 forms between the upper bonding electrode 203 and the lower electrode layer 301 to separate the two electrodes. Then, an insulating layer is fabricated using screen printing. The left side of the upper insulating layer 4 covers the left side of the upper electrode layer 201. The electrode is then... The left side of electrode layer 201 is exposed by 0.1-5mm. The edges of the other sides of the upper insulating layer 4 cover the edges of the other sides of the upper electrode layer 201. The left side of the lower insulating layer 5 covers the right side of the upper bonding electrode 203, and the upper bonding electrode 203 is exposed by 0.1-5mm. The edges of the other sides of the lower insulating layer 5 cover the edges of the other sides of the lower electrode layer 301. Then, the auxiliary electrode layer 202 is sputtered onto the left side of the substrate 1. The two bonding electrodes are used as surface mount components and are soldered to the PCB board respectively. The surface mount positive temperature coefficient thermistor made by the above method does not need to have a high anti-combination wave capability.

[0049] Example 3:

[0050] As attached Figure 6 As shown:

[0051] This invention provides a leadless, solderless surface-mount electronic component, comprising a substrate 1; an upper electrode surface 2 is disposed on the top of the substrate 1; the upper electrode surface 2 is composed of an upper electrode layer 201, an auxiliary electrode layer 202 and an upper bonding electrode 203; a lower electrode surface 3 is disposed on the bottom of the substrate 1; the lower electrode surface 3 is composed of a lower electrode layer 301 and a lower bonding electrode 302; an upper insulating layer 4 is covered on the top of the upper electrode surface 2; a lower insulating layer 5 is covered on the bottom of the lower electrode surface 3; and an isolation gap 6 is disposed between the upper bonding electrode 203 and the lower electrode layer 301.

[0052] The substrate 1 is a varistor, and the upper electrode surfaces 201 and 203 and the lower electrode surface 3 are electrodes fabricated by sputtering.

[0053] The auxiliary electrode layer 202 is a multilayer electrode fabricated by sputtering.

[0054] The upper electrode layer 201, the auxiliary electrode layer 202, and the upper bonding electrode 203 together form a J-shape.

[0055] The upper insulating layer 4 and the lower insulating layer 5 are both organic resin layers, and the upper insulating layer 4 and the lower insulating layer 5 are made by screen printing.

[0056] The width of the isolation gap 6 is greater than the thickness of the substrate 1.

[0057] The upper bonding electrode 203 is located on the left end surface of the lower insulating layer 5.

[0058] The specific usage and function of this embodiment are as follows:

[0059] When manufacturing surface mount electronic components using this method, the lower insulating layer 5 can be covered before covering the upper bonding electrode 203. Therefore, the right side of the upper bonding electrode 203 will be located on the left side surface of the lower insulating layer 5, which can effectively improve product safety (compared to Example 1).

[0060] Example 4:

[0061] As attached Figure 7 As shown:

[0062] This invention provides a leadless, solderless surface-mount electronic component, comprising a substrate 1; an upper electrode surface 2 is disposed on the top of the substrate 1; the upper electrode surface 2 is composed of an upper electrode layer 201, an auxiliary electrode layer 202 and an upper bonding electrode 203; a lower electrode surface 3 is disposed on the bottom of the substrate 1; the lower electrode surface 3 is composed of a lower electrode layer 301 and a lower bonding electrode 302; an upper insulating layer 4 is covered on the top of the upper electrode surface 2; a lower insulating layer 5 is covered on the bottom of the lower electrode surface 3; and an isolation gap 6 is disposed between the upper bonding electrode 203 and the lower electrode layer 301.

[0063] The substrate 1 is a varistor, and the upper electrode surfaces 201 and 203 and the lower electrode surface 3 are electrodes fabricated by sputtering.

[0064] The auxiliary electrode layer 202 is a multilayer electrode made by dip coating and electroplating processes.

[0065] The upper electrode layer 201, the auxiliary electrode layer 202, and the upper bonding electrode 203 together form a J-shape.

[0066] The upper insulating layer 4 and the lower insulating layer 5 are both organic resin layers, and the upper insulating layer 4 and the lower insulating layer 5 are made by screen printing.

[0067] The width of the isolation gap 6 is greater than the thickness of the substrate 1.

[0068] Among them, a strip groove is provided above the isolation gap 6 on one side of the bottom of the substrate 1.

[0069] The specific usage and function of this embodiment are as follows:

[0070] In this invention, when fabricating surface-mount electronic components using this method, the lower insulating layer 5 can be covered before the upper bonding electrode 203. Furthermore, a strip-shaped groove is provided above the isolation gap 6 before covering. In this way, the actual distance between the upper bonding electrode 203 and the lower electrode layer 301 is equal to the direct distance 6 between the two electrodes plus the depth of two grooves. This widens the distance between the upper bonding electrode 203 and the lower electrode layer 301, and the right side of the upper bonding electrode 203 will be located on the left surface of the lower insulating layer 5. This can increase the effective electrode area (compared to embodiment 3) and further improve the safety of the product.

[0071] The above four embodiments only illustrate some methods described in the patent application. In actual production, the following principles can be used to optimize and replace the manufacturing process:

[0072] 1. For substrates that are insulators, such as varistors and ceramic capacitors, the following combination processes can be used:

[0073] 1) The upper electrode layer 201, the upper bonding electrode 203 and the lower electrode 3 are made of silver electrodes by screen printing. The insulating layer can be made of inorganic glass or organic resin.

[0074] 2) The upper electrode layer 201, the upper bonding electrode 203 and the lower electrode 3 are fabricated by sputtering to form a multilayer alloy electrode, and the insulating layer can be made of organic resin;

[0075] 3) The auxiliary electrode layer 202 is a multilayer electrode made by dip coating and electroplating process, or a multilayer electrode made by sputtering and electroplating process, or a multilayer electrode made by sputtering process.

[0076] 2. For substrates that are semiconductors, such as thermistors (divided into positive temperature coefficient thermistors (PTC) and negative temperature coefficient thermistors (NTC)), the following combination processes can be used:

[0077] 1) The upper electrode layer 201, the upper bonding electrode 203 and the lower electrode 3 are made by screen printing. The insulating layer can be made of inorganic glass or organic resin.

[0078] 2) The upper electrode layer 201, the upper bonding electrode 203 and the lower electrode 3 are fabricated by sputtering to form a multilayer alloy electrode, and the insulating layer can be made of organic resin;

[0079] 3) The auxiliary electrode layer 202 is a multilayer electrode fabricated by a through sputtering process.

[0080] The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A leadless, solderless surface-mount electronic component, characterized in that: The surface mount electronic component includes: a substrate (1); an upper electrode surface (2) is disposed on the top of the substrate (1); the upper electrode surface (2) is composed of an upper electrode layer (201), an auxiliary electrode layer (202) and an upper bonding electrode (203); a lower electrode surface (3) is disposed on the bottom of the substrate (1); the lower electrode surface (3) is composed of a lower electrode layer (301) and a lower bonding electrode (302); the top of the upper electrode surface (2) is covered with an upper insulating layer (4); the bottom of the lower electrode surface (3) is covered with a lower insulating layer (5). Insulating layer (5); an isolation gap (6) is provided between the upper bonding electrode (203) and the lower electrode layer (301); the upper electrode layer (201), the auxiliary electrode layer (202), and the upper bonding electrode (203) together form a J-shape; the width of the isolation gap (6) is greater than the thickness of the substrate (1); the upper electrode layer (201), the upper bonding electrode (203), and the lower electrode surface (3) are first fabricated on the top and bottom of the substrate (1) by screen printing process, and the upper electrode layer (201) and the lower electrode layer (301) are respectively... Located on the top and bottom surfaces of the substrate (1), the upper bonding electrode (203) covers the bottom left side of the substrate (1), and the lower bonding electrode (302) covers the bottom right side of the substrate (1). At this time, an isolation gap (6) appears between the upper bonding electrode (203) and the lower electrode layer (301) to separate the two electrodes. Then, an insulating layer is made by screen printing. The left side of the upper insulating layer (4) covers the left side of the upper electrode layer (201), and the left side of the upper electrode layer (201) is exposed by 0.1-5mm. The other parts of the upper insulating layer (4) are not visible. The edge of the upper electrode layer (201) is covered by the edge of the other edge of the upper electrode layer (201). The left side of the lower insulating layer (5) covers the right side of the upper bonding electrode (203), and the upper bonding electrode (203) is exposed by 0.1-5mm. The edges of the other edges of the lower insulating layer (5) are covered by the edges of the other edges of the lower electrode layer (301). Then a welding window is opened on the lower bonding electrode (302). The auxiliary electrode layer (202) is then covered on the left side of the substrate (1) by sputtering and electroplating. The two bonding electrodes are used as surface mount components and are welded to the PCB board respectively.

2. The leadless, solderless surface-mount electronic component as described in claim 1, characterized in that: The substrate (1) is a varistor, thermistor, or ceramic capacitor, and the upper electrode surface (2) and lower electrode surface (3) are one or more electrodes made by screen printing, spraying, dipping, sputtering or electroplating.

3. The leadless, solderless surface-mount electronic component as described in claim 1, characterized in that: The upper electrode surface (2) and the lower electrode surface (3) are one or more alloys of silver, nickel, copper, zinc, aluminum, chromium or titanium.

4. The leadless, solderless surface-mount electronic component as described in claim 1, characterized in that: Both the upper insulating layer (4) and the lower insulating layer (5) are inorganic glass or organic resin.

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