MOS device and manufacturing method thereof

Abstract

The present invention provides a MOS device and a manufacturing method thereof, the method comprising the following steps: providing a substrate, wherein the substrate is provided with a source region and a drain region spaced apart in a horizontal direction; forming a sandwich structure on the substrate, wherein the sandwich structure comprises a first SiO 2 layer, high-K dielectric layer and second SiO 2 forming a groove, the groove being formed from the second SiO 2 The upper surface of the layer is opened and extends downward into the high-K dielectric layer, the groove is located between the source region and the drain region in the horizontal direction, and in the direction from the source region to the drain region, the depth of the two ends of the groove is less than the depth in the middle; a gate conductive layer is formed, and the gate conductive layer is located in the second SiO 2 The gate conductive layer is formed on the sidewall of the gate conductive layer and filled into the groove, the width of the gate conductive layer is greater than the width of the groove; and a sidewall structure is formed on the sidewall of the gate conductive layer. The present invention can improve the withstand voltage performance of the device without affecting the turn-on voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to a MOS device and a manufacturing method thereof. Background Art

[0002] The gate oxide structures commonly used in current semiconductor manufacturing technology are as follows: Figure 1 As shown, the structure includes a substrate 101 , a source 102 , a drain 103 , a gate oxide layer 104 , a polysilicon gate 105 and a spacer 106 .

[0003] The threshold voltage and withstand voltage of MOS devices are important criteria for measuring device performance. Finding a suitable threshold voltage and improving the withstand voltage of devices are also an important development direction of current devices.

[0004] Basic characteristics such as threshold voltage and withstand voltage are closely related to conditions such as device channel length and gate silicon oxide thickness. Generally, it is hoped that the device has a higher withstand voltage while maintaining the current driving capability.

[0005] Therefore, how to improve the structural design of MOS devices to enhance the voltage withstand capability of the devices while having minimal impact on the threshold voltage has become an important technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a MOS device and a manufacturing method thereof, so as to solve the problem in the prior art that the turn-on voltage is affected while the voltage resistance of the MOS device is improved.

[0007] To achieve the above object and other related objects, the present invention provides a method for manufacturing a MOS device, comprising the following steps:

[0008] Providing a substrate, wherein a source region and a drain region are provided in the substrate and are spaced apart in a horizontal direction;

[0009] forming a sandwich structure on the substrate, wherein the sandwich structure comprises a first SiO2 layer, a high-K dielectric layer and a second SiO2 layer stacked sequentially from bottom to top;

[0010] A groove is formed in the sandwich structure, the groove opens from the upper surface of the second SiO2 layer and extends downward, but does not penetrate the sandwich structure, the groove is located between the source region and the drain region in the horizontal direction, and in the direction from the source region to the drain region, the depth of the two ends of the groove is less than the depth of the middle of the groove;

[0011] forming a gate conductive layer, wherein the gate conductive layer fills the groove, and a top surface of the gate conductive layer is higher than a top surface of the second SiO2 layer;

[0012] A sidewall structure is formed on the sidewall of the gate conductive layer.

[0013] Optionally, forming the groove comprises:

[0014] forming a first photoresist layer on the second SiO2 layer;

[0015] Forming a photoresist layer opening in the first photoresist layer, wherein the photoresist layer opening is located between the source region and the drain region in a horizontal direction, and the bottom of the photoresist layer opening exposes the second SiO2 layer;

[0016] The second SiO2 layer and the high-K dielectric layer are etched using the first photoresist layer as a mask to obtain the groove.

[0017] Optionally, the bottom of the groove is a concave arc surface.

[0018] Optionally, a bottom surface of the groove is not lower than a top surface of the first SiO2 layer.

[0019] Optionally, forming a gate conductive layer includes:

[0020] forming a conductive material layer on the second SiO2 layer and in the groove;

[0021] forming a second photoresist layer on the conductive material layer;

[0022] Patterning the second photoresist layer to expose the portion of the conductive material layer facing the source region and the drain region, and the portion of the conductive material layer facing the groove is still blocked by the photoresist layer;

[0023] The second photoresist layer is used as a mask to etch the conductive material layer until the second SiO2 layer is exposed, and the area of ​​the conductive material layer blocked by the second photoresist layer is not etched to serve as the gate conductive layer.

[0024] Optionally, the width of the gate conductive layer is greater than the width of the groove, and in the direction from the source region to the drain region, the bottoms of both ends of the gate conductive layer are in contact with the upper surface of the second SiO2 layer.

[0025] Optionally, the area of ​​the sandwich structure that is not blocked by the spacer structure and the gate conductive layer is removed.

[0026] Optionally, the method of forming the first SiO2 layer includes a thermal oxidation method.

[0027] The present invention also provides a MOS device, comprising:

[0028] A substrate, wherein a source region and a drain region are provided in the substrate and are spaced apart in a horizontal direction;

[0029] A sandwich structure, located on the substrate and comprising a first SiO2 layer, a high-K dielectric layer and a second SiO2 layer stacked in sequence from bottom to top;

[0030] A groove is located in the sandwich structure, the groove opens from the upper surface of the second SiO2 layer and extends downward, but does not penetrate the sandwich structure, the groove is located between the source region and the drain region in the horizontal direction, and in the direction from the source region to the drain region, the depth of the two ends of the groove is less than the depth of the middle of the groove;

[0031] A gate conductive layer is filled in the groove, and a top surface of the gate conductive layer is higher than a top surface of the second SiO2 layer;

[0032] The sidewall structure is located on the sidewall of the gate conductive layer.

[0033] Optionally, the bottom of the groove is a concave arc surface.

[0034] Optionally, a bottom surface of the groove is higher than a top surface of the second SiO2 layer.

[0035] Optionally, the width of the gate conductive layer is greater than the width of the groove, and in the direction from the source region to the drain region, the bottoms of both ends of the gate conductive layer are in contact with the upper surface of the second SiO2 layer.

[0036] As described above, in the MOS device structure of the present invention, the gate dielectric layer adopts a SiO2 / high-K dielectric layer / SiO2 sandwich structure, wherein the high-K dielectric layer in the middle layer is conducive to reducing the breakdown probability and enhancing the voltage resistance of the device. The presence of the upper and lower SiO2 layers can reduce the interface strain and maintain the matching degree between the gate oxide and the substrate, and the gate oxide and the gate conductive layer. In the MOS device structure of the present invention, the gate dielectric layer also adopts a design of being thin in the middle and thick at both ends, wherein the thicker parts at both ends of the gate dielectric layer are conducive to reducing the source-drain voltage influence of the source-drain edge region and improving the voltage resistance, while the thinner part in the middle can ensure that the conductive channel can still be normally turned on at low voltage, so that the turn-on voltage is not significantly different from that of the ordinary structure, thereby reducing the influence of thickness on the turn-on voltage, that is, the present invention can improve the voltage resistance of the device without affecting the turn-on voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a MOS device.

[0038] Figure 2 Shown is a process flow chart of a method for manufacturing a MOS device of the present invention.

[0039] Figure 3 The cross-sectional structure diagram of the substrate provided for the method for manufacturing the MOS device of the present invention is shown.

[0040] Figure 4 It is a schematic diagram showing the method for manufacturing the MOS device of the present invention to form a sandwich structure on the substrate.

[0041] Figure 5 It is a schematic diagram showing the method for manufacturing a MOS device of the present invention, wherein a first photoresist layer is formed on the second SiO2 layer and then patterned.

[0042] Figure 6 The schematic diagram shows the method for manufacturing the MOS device of the present invention, which uses the first photoresist layer as a mask to etch the second SiO2 layer and the high-K dielectric layer to obtain the groove.

[0043] Figure 7 It is a schematic diagram showing the method for manufacturing a MOS device of the present invention, wherein a conductive material layer is formed on the second SiO2 layer and in the groove.

[0044] Figure 8 It is a schematic diagram showing the method for manufacturing a MOS device of the present invention, wherein a second photoresist layer is formed on the conductive material layer and then patterned.

[0045] Fig. 9 It is a schematic diagram showing the method for manufacturing a MOS device of the present invention, in which the conductive material layer is etched until the second SiO2 layer is exposed.

[0046] Fig.10 It is a schematic diagram showing the method for manufacturing a MOS device of the present invention, in which a spacer structure is formed on the side wall of the gate conductive layer.

[0047] Fig.11 It is a schematic diagram showing the method for manufacturing a MOS device of the present invention, wherein the area of ​​the sandwich structure that is not blocked by the spacer structure and the gate conductive layer is removed.

[0048] Component number

[0049] 101 substrate

[0050] 102 Source

[0051] 103 Drain

[0052] 104 gate oxide layer

[0053] 105 polysilicon gate

[0054] 106 side wall

[0055] Steps S1 to S5

[0056] 201 substrate

[0057] 202 Source Area

[0058] 203 Leakage Area

[0059] 204 first SiO2 layer

[0060] 205 High K dielectric layer

[0061] 206 Second SiO2 layer

[0062] 207 grooves

[0063] 208 first photoresist layer

[0064] 209 photoresist layer opening

[0065] 210 gate conductive layer

[0066] 210' conductive material layer

[0067] 211 second photoresist layer

[0068] 212 Oxide layer

[0069] 213 Silicon Nitride Layer DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] See also Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0072] Embodiment 1

[0073] This embodiment provides a method for manufacturing a MOS device. Figure 2 , shown as a process flow chart of the method, comprising the following steps:

[0074] S1: providing a substrate, wherein a source region and a drain region are provided in the substrate and are spaced apart in a horizontal direction;

[0075] S2: forming a sandwich structure on the substrate, wherein the sandwich structure includes a first SiO2 layer, a high-K dielectric layer, and a second SiO2 layer stacked sequentially from bottom to top;

[0076] S3: forming a groove in the sandwich structure, wherein the groove opens from the upper surface of the second SiO2 layer and extends downward, but does not penetrate the sandwich structure, and the groove is located between the source region and the drain region in the horizontal direction, and in the direction from the source region to the drain region, the depth of the two ends of the groove is less than the depth of the middle of the groove;

[0077] S4: forming a gate conductive layer, wherein the gate conductive layer fills the groove, and a top surface of the gate conductive layer is higher than a top surface of the second SiO2 layer;

[0078] S5: forming a sidewall structure on the sidewall of the gate conductive layer.

[0079] First see Figure 3 , perform the step S1: provide a substrate 201, wherein the substrate 201 is provided with a source region 202 and a drain region 203 spaced apart in a horizontal direction.

[0080] As an example, the material of the substrate 201 includes, but is not limited to, semiconductor materials such as silicon, germanium, silicon-germanium, silicon-on-insulator, and III-V compounds. The source region 202 and the drain region 203 can be obtained by ion implantation in a preset region of the substrate 201. The source region 202 and the drain region 203 have the same conductivity type, for example, the substrate 201 adopts a P-type silicon substrate, and the source region 202 and the drain region 203 are both N-type.

[0081] Please see again Figure 4 , performing the step S2: forming a sandwich structure on the substrate 201, the sandwich structure comprising a first SiO2 layer 204, a high-K dielectric layer 205 and a second SiO2 layer 206 stacked in sequence from bottom to top.

[0082] As an example, an ultra-thin SiO2 layer may be grown on the surface of the substrate 201 by thermal oxidation as the first SiO2 layer 204. In this embodiment, the thickness of the first SiO2 layer 204 is in the range of 10-50 angstroms.

[0083] As an example, the high-K dielectric layer 205 and the second SiO2 layer 206 can be formed by chemical vapor deposition, physical vapor deposition or other suitable methods. The dielectric constant of the high-K dielectric layer 205 is greater than 3.9, and its material includes but is not limited to at least one of nitrogen-doped silicon oxide, silicon nitride, hafnium oxide, aluminum oxide and zirconium oxide. In this embodiment, the thickness of the high-K dielectric layer 205 ranges from 50 to 200 angstroms.

[0084] Please see again Figure 5 and Figure 6 , perform the step S3: form a groove 207 in the sandwich structure, the groove 207 opens from the upper surface of the second SiO2 layer 206 and extends downward, but does not penetrate the sandwich structure, the groove 207 is located between the source region 202 and the drain region 203 in the horizontal direction, and in the direction from the source region 202 to the drain region 203, the depth of the two ends of the groove 207 is less than the depth of the middle of the groove 207.

[0085] As an example, forming the groove 207 includes:

[0086] Step S3-1: Figure 5 As shown, a first photoresist layer 208 is formed on the second SiO2 layer 206 by spin coating or other suitable methods;

[0087] Step S3-2: Continue as Figure 5 As shown, a photoresist layer opening 209 is formed in the first photoresist layer 208 by using photolithography, development and other photolithography processes, and the photoresist layer opening 209 is located between the source region 202 and the drain region 203 in the horizontal direction, and the bottom of the photoresist layer opening 209 exposes the second SiO2 layer 206;

[0088] Step S3-3: Figure 6 As shown, the first photoresist layer 208 is used as a mask to etch the second SiO 2 layer 206 and the high-K dielectric layer 205 to obtain the groove 207 .

[0089] As an example, in one implementation, the groove 207 may be formed by wet etching, wherein the wet etching is isotropic etching, and the bottom of the obtained groove is a concave arc surface with shallow depths at both ends and deep depths in the middle.

[0090] As an example, in another implementation, wet etching combined with dry etching may be used to obtain the groove 207 .

[0091] As an example, the bottom surface of the groove 207 is not lower than the top surface of the first SiO 2 layer, so as to ensure the integrity of the first SiO 2 layer 204 .

[0092] As an example, the bottom surface of the groove 207 extends into the high-K dielectric layer 205 .

[0093] Please see again Figures 7 to 9, perform the step S4: remove the first photoresist layer 208 and form a gate conductive layer 210, the gate conductive layer 210 fills the groove, and the top surface of the gate conductive layer 210 is higher than the top surface of the second SiO2 layer 206.

[0094] As an example, the width of the gate conductive layer 210 may be less than or equal to the width of the groove 207, or may be greater than the width of the groove 207. In this embodiment, the width of the gate conductive layer 210 is preferably greater than the width of the groove 207, and in the direction from the source region 202 to the drain region 203, the bottoms of both ends of the gate conductive layer 210 are in contact with the upper surface of the second SiO2 layer 206, which is beneficial to reducing the curve of the contact area between the two ends of the gate conductive layer 210 and the gate dielectric layer.

[0095] As an example, the forming of the gate conductive layer 210 includes:

[0096] Step S4-1: Figure 7 As shown, a conductive material layer 210' is formed on the second SiO2 layer 206 and in the groove 207 by chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the conductive material layer 210' includes but is not limited to polysilicon;

[0097] Step S4-2: Figure 8 As shown, a second photoresist layer 211 is formed on the conductive material layer 210' by spin coating or other suitable methods;

[0098] Step S4-3: Continue as Figure 8 As shown, the second photoresist layer 211 is patterned by photolithography processes such as exposure and development to expose the portion of the conductive material layer 210' facing the source region 202 and the drain region 203, and the portion of the conductive material layer 210' facing the groove 207 is still blocked by the photoresist layer;

[0099] Step S4-4: Fig. 9 As shown, the second photoresist layer 211 is used as a mask to etch the conductive material layer 210 ′ until the second SiO 2 layer 206 is exposed, and the area of ​​the conductive material layer 210 ′ blocked by the second photoresist layer 211 is not etched to serve as the gate conductive layer 210 .

[0100] Please see again Fig.10 and Fig.11 , executing the step S5: forming a sidewall structure on the sidewall of the gate conductive layer 210 .

[0101] As an example, Fig.10As shown, the exposed surface of the gate conductive layer 210 may be oxidized to obtain an oxide layer 212, and a silicon nitride layer 213 may be deposited on the surface of the oxide layer 212 to obtain the sidewall structure, and then Fig.11 As shown, wet etching and / or dry etching is used to remove the area of ​​the sandwich structure that is not blocked by the sidewall structure and the gate conductive layer 210, wherein the area of ​​the sandwich structure that is blocked by the sidewall structure and the gate conductive layer 210 is retained as a gate dielectric layer.

[0102] At this point, a MOS device is manufactured. The manufacturing method of the MOS device of this embodiment first manufactures a relatively thick multi-material stacked sandwich structure, and then etches the sandwich structure to obtain a gate dielectric layer structure that is thin in the middle and thick on both sides. The voltage resistance performance of the device can be improved without affecting the turn-on voltage. Among them, by adding a high-K dielectric layer, the anti-breakdown, voltage resistance and other aspects are improved, the voltage resistance performance is improved by the relatively thick gate dielectric layers on both sides, and the influence of the thickness on the turn-on voltage is reduced by the thinner gate dielectric layer in the middle.

[0103] Embodiment 2

[0104] This embodiment provides a MOS device, which can be manufactured by the method in the first embodiment or other suitable methods.

[0105] See also Fig.11 The MOS device comprises a substrate 201, a sandwich structure, a groove 207, a gate conductive layer 210 and a sidewall structure, wherein the substrate 201 is provided with a source region 202 and a drain region 203 spaced apart in a horizontal direction; the sandwich structure is located on the substrate 201 and comprises a first SiO2 layer 204, a high-K dielectric layer 205 and a second SiO2 layer 206 stacked in sequence from bottom to top; the groove 207 is located in the sandwich structure, the groove 207 opens from the upper surface of the second SiO2 layer 206 and extends downward, but does not penetrate the sandwich structure, the groove 207 is located between the source region 202 and the drain region 203 in the horizontal direction, and in the direction from the source region 202 to the drain region 203, the depths of the two ends of the groove 207 are less than the depth of the middle of the groove; the gate conductive layer 210 is filled in the groove 207, and the top surface thereof is higher than the top surface of the second SiO2 layer; the sidewall structure is located on the sidewall of the gate conductive layer 210.

[0106] As an example, the sidewall structure includes an oxide layer 212 and a silicon nitride layer 213 which are sequentially arranged from the inside to the outside.

[0107] As an example, the bottom of the groove 207 is a concave arc surface.

[0108] As an example, the bottom surface of the groove 207 is not lower than the top surface of the first SiO 2 layer 204 .

[0109] As an example, the width of the gate conductive layer 210 may be less than or equal to the width of the groove 207, or may be greater than the width of the groove 207. In this embodiment, the width of the gate conductive layer 210 is preferably greater than the width of the groove 207, and in the direction from the source region 202 to the drain region 203, the bottoms of both ends of the gate conductive layer 210 are in contact with the upper surface of the second SiO2 layer 206, which is beneficial to reducing defects in the contact area between the two ends of the gate conductive layer 210 and the gate dielectric layer.

[0110] In summary, in the MOS device structure of the present invention, the gate dielectric layer adopts a SiO2 / high-K dielectric layer / SiO2 sandwich structure, wherein the high-K dielectric layer in the middle layer is conducive to reducing the breakdown probability and enhancing the voltage resistance of the device. The presence of the upper and lower SiO2 layers can reduce the interface strain and maintain the matching degree between the gate oxide and the substrate, and the gate oxide and the gate conductive layer. In the MOS device structure of the present invention, the gate dielectric layer also adopts a design of being thin in the middle and thick at both ends, wherein the thicker parts at both ends of the gate dielectric layer are conducive to reducing the source-drain voltage influence of the source-drain edge region and improving the voltage resistance, while the thinner part in the middle can ensure that the conductive channel can still be normally formed and turned on at low voltage, so that the turn-on voltage is not significantly different from that of the ordinary structure, thereby reducing the influence of thickness on the turn-on voltage, that is, the present invention can improve the voltage resistance of the device without affecting the turn-on voltage. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a MOS device, characterized in that: The following steps are involved: Providing a substrate, wherein a source region and a drain region are provided in the substrate and are spaced apart in a horizontal direction; forming a sandwich structure on the substrate, wherein the sandwich structure comprises a first SiO2 layer, a high-K dielectric layer and a second SiO2 layer stacked sequentially from bottom to top; A groove is formed in the sandwich structure, the groove opens from the upper surface of the second SiO2 layer and extends downward, but does not penetrate the sandwich structure, the groove is located between the source region and the drain region in the horizontal direction, and in the direction from the source region to the drain region, the depth of the two ends of the groove is less than the depth of the middle of the groove; forming a gate conductive layer, wherein the gate conductive layer fills the groove, and a top surface of the gate conductive layer is higher than a top surface of the second SiO2 layer; A sidewall structure is formed on the sidewall of the gate conductive layer.

2. The method for manufacturing a MOS device according to claim 1, characterized in that: The forming of the groove comprises: forming a first photoresist layer on the second SiO2 layer; Forming a photoresist layer opening in the first photoresist layer, wherein the photoresist layer opening is located between the source region and the drain region in a horizontal direction, and the bottom of the photoresist layer opening exposes the second SiO2 layer; The second SiO2 layer and the high-K dielectric layer are etched using the first photoresist layer as a mask to obtain the groove.

3. The method for manufacturing a MOS device according to claim 1, characterized in that: The bottom of the groove is a concave arc surface.

4. The method for manufacturing a MOS device according to claim 1, wherein: The bottom surface of the groove is not lower than the top surface of the first SiO2 layer.

5. The method for manufacturing a MOS device according to claim 1, characterized in that: The forming of the gate conductive layer comprises: forming a conductive material layer on the second SiO2 layer and in the groove; forming a second photoresist layer on the conductive material layer; Patterning the second photoresist layer to expose the portion of the conductive material layer facing the source region and the drain region, and the portion of the conductive material layer facing the groove is still blocked by the photoresist layer; The second photoresist layer is used as a mask to etch the conductive material layer until the second SiO2 layer is exposed, and the area of ​​the conductive material layer blocked by the second photoresist layer is not etched to serve as the gate conductive layer.

6. The method for manufacturing a MOS device according to claim 1, characterized in that: The width of the gate conductive layer is greater than the width of the groove, and in the direction from the source region to the drain region, the bottoms of both ends of the gate conductive layer are in contact with the upper surface of the second SiO2 layer.

7. The method for manufacturing a MOS device according to claim 1, characterized in that: Also includes: The area of ​​the sandwich structure that is not blocked by the sidewall structure and the gate conductive layer is removed.

8. The method for manufacturing a MOS device according to claim 1, characterized in that: The method of forming the first SiO2 layer includes a thermal oxidation method.

9. A MOS device, characterized in that: include: A substrate, wherein a source region and a drain region are provided in the substrate and are spaced apart in a horizontal direction; A sandwich structure, located on the substrate and comprising a first SiO2 layer, a high-K dielectric layer and a second SiO2 layer stacked in sequence from bottom to top; A groove is located in the sandwich structure, the groove opens from the upper surface of the second SiO2 layer and extends downward, but does not penetrate the sandwich structure, the groove is located between the source region and the drain region in the horizontal direction, and in the direction from the source region to the drain region, the depth of the two ends of the groove is less than the depth of the middle of the groove; A gate conductive layer is filled in the groove, and a top surface of the gate conductive layer is higher than a top surface of the second SiO2 layer; The sidewall structure is located on the sidewall of the gate conductive layer.

10. The MOS device according to claim 9, characterized in that: The bottom of the groove is a concave arc surface.

11. The MOS device according to claim 9, characterized in that: The bottom surface of the groove is not lower than the top surface of the first SiO2 layer.

12. The MOS device according to claim 9, characterized in that: The width of the gate conductive layer is greater than the width of the groove, and in the direction from the source region to the drain region, the bottoms of both ends of the gate conductive layer are in contact with the upper surface of the second SiO2 layer.

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