Adaptive drive circuit, IO interface circuit and chip, electronic equipment

Abstract

The present application relates to an adaptive driving circuit, an IO interface circuit and a chip, and an electronic device, and belongs to the field of electronic circuit technology. The adaptive driving circuit includes: a driving main circuit, a voltage divider circuit; the driving main circuit is used to output a driving signal; the first end of the voltage divider circuit is used to connect to a first power supply, the second end of the voltage divider circuit is grounded, the output end of the voltage divider circuit is connected to the driving main circuit, and the voltage divider circuit is used to output a control power supply as an output transistor in the driving main circuit, so that the pull-up capability and pull-down capability of the driving main circuit are consistent under different PVT conditions. The pull-up capability and pull-down capability of the driving main circuit are consistent under different PVT conditions, and compared with the traditional driving circuit, the maximum on-resistance of the PMOS tube can be reduced, thereby reducing the layout area of ​​the entire driving circuit.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and specifically relates to an adaptive driving circuit, an IO interface circuit and chip, and an electronic device. Background Art

[0002] IO (Input Output) interface circuits are widely used in various IO interface chips (such as processors, memories, etc.). The normal operation of the IO interface circuit directly determines the availability of the entire chip. As an important part of the IO interface circuit, the quality of the output signal of the driver circuit directly determines the quality of the output signal of the IO interface circuit.

[0003] The voltage resistance of MOS (Metal Oxide Semiconductor) tubes decreases with the improvement of semiconductor process, so cascode MOS tube structure is usually used to solve the voltage resistance problem of devices. Figure 1 As shown, it includes two independent power supplies, VDDH and VDDL. The maximum voltage difference that all MOS devices can withstand is VDDL. In the figure, the control signal pre_pgate is a square wave control signal of VDDL~VDDH, and the control signal pre_ngate is a square wave control signal of 0~VDDL. Resistor R1 and PMOS tubes P1 and P2 form a driving pull-up branch, and resistor R2 and NMOS tubes N1 and N2 form a driving pull-down branch.

[0004] When the PAD signal is switching (from low level to high level or from high level to low level), due to the existence of resistors R1 and R2, the MOS tube works in the deep linear region as a switch tube. The final pull-up resistance at PAD is the sum of R1 and the on-resistance of MOS tubes P1 and P2 working in the deep linear region. The pull-down resistance at PAD is the sum of R2 and the on-resistance of MOS tubes N1 and N2 working in the deep linear region. The |VGS| voltage when the P1 tube is turned on is VDDH-VDDL, the |VGS| voltage of the P2 tube is vp1-VDDL, the |VGS| voltage of the N1 tube is VDDL-vn1, and the |VGS| voltage of the N2 tube is VDDL, where vp1 is the voltage at the source end of the P2 tube, vp1 is approximately equal to VDDH, and vn1 is the voltage at the source end of the N1 tube, vn1 is approximately equal to 0.

[0005] Since VDDH and VDDL are different power supplies, under different PVT (Process Voltage Temperature, a combination of process, voltage, and temperature) conditions, the gate-source voltage of the PMOS tube is (VDDHmin-VDDLmax) to (VDDHmax-VDDLmin), while the gate-source voltage of the NMOS tube is VDDLmin to VDDLmax. Therefore, the gate-source voltage range of the NMOS tube is (VDDLmax-VDDLmin), and the gate-source voltage range of the PMOS tube is (VDDHmax–VDDHmin+VDDLmax-VDDLmin). This makes the pull-up capability of the pull-up branch in the driving circuit and the pull-down capability of the pull-down branch in the driving circuit mismatch under different PVT conditions, which will greatly deteriorate the output signal quality of the driving circuit. In addition, due to the greater influence of the gate-source voltage of the PMOS tube under different PVT conditions, the output on-resistance of the driving pull-up branch has a large deviation under different PVT conditions, especially when the gate-source voltage difference of the PMOS tube is small. If the maximum on-resistance of the PMOS tube is to meet the design requirements, the area of ​​the PMOS tube needs to be increased, which increases the layout area of ​​the entire driving circuit. Summary of the invention

[0006] In view of this, the purpose of the present application is to provide an adaptive driving circuit, an IO interface circuit and chip, and an electronic device to improve the problem that the pull-up capability and pull-down capability of the existing driving circuit do not match under different PVT conditions, and the output on-resistance of the driving pull-up branch has large deviation under different PVT conditions.

[0007] The embodiment of the present application is implemented as follows:

[0008] In the first aspect, the embodiment of the present application provides an adaptive driving circuit, including: a driving main circuit, a voltage divider circuit; the driving main circuit is used to output a driving signal; the first end of the voltage divider circuit is used to connect a first power supply, the second end of the voltage divider circuit is grounded, the output end of the voltage divider circuit is connected to the driving main circuit, and the voltage divider circuit is used to output a control power supply as an output transistor in the driving main circuit, so that the pull-up capability and the pull-down capability of the driving main circuit are consistent under different PVT conditions. In the embodiment of the present application, an adaptive adjustment technology is adopted, and a voltage divider circuit is used to divide the first power supply (such as VDDH) by a voltage divider circuit, and the voltage obtained by the voltage division is used as the control power supply of the output transistor in the driving main circuit, so as to realize the dynamic adjustment function of the control power supply of the output transistor in the driving main circuit with the power supply VDDH, so that the control power supply can change dynamically with the power supply VDDH, and be consistent with the influence of different PVT conditions, so that not only can the pull-up capability and the pull-down capability of the driving main circuit be consistent under different PVT conditions, but also can reduce the maximum on-resistance of the PMOS tube, thereby reducing the layout area of ​​the entire driving circuit.

[0009] In combination with a possible implementation of the embodiment of the first aspect, the voltage divider circuit includes: a voltage divider basic circuit and an operational amplifier; the first end of the voltage divider basic circuit is used to connect to the first power supply, the second end of the voltage divider basic circuit is grounded, and the voltage divider basic circuit is used to output an internal power supply; the first input end of the operational amplifier is connected to the output end of the voltage divider basic circuit, the second input end of the operational amplifier is connected to its output end, and the output end of the operational amplifier outputs a control power supply for an output transistor in the driving main circuit. In the embodiment of the present application, the operational amplifier is equivalent to a unit gain buffer, and by adding a unit gain, sufficient driving capability can be provided to enhance the driving capability of the voltage divider basic circuit.

[0010] In combination with a possible implementation of the embodiment of the first aspect, the voltage-dividing basic circuit includes: a first current-limiting device and a second current-limiting device; the first end of the first current-limiting device is connected to the first power supply, the second end of the first current-limiting device is grounded through the second current-limiting device, the second end of the first current-limiting device is also connected to the first input end of the operational amplifier, and the second end of the first current-limiting device is the output end of the voltage-dividing basic circuit. In the embodiment of the present application, the purpose of voltage division can be achieved by using common components such as the first current-limiting device and the second current-limiting device, which can save costs while achieving its purpose.

[0011] In a possible implementation manner of the embodiment of the first aspect, the resistance value of the first current limiting device is consistent with the resistance value of the second current limiting device. In the embodiment of the present application, the resistance value of the first current limiting device is consistent with the resistance value of the second current limiting device, so that the voltage after voltage division is equal to 0.5*VDDH, and VDDH is the first power supply.

[0012] In combination with a possible implementation of the first aspect of the embodiment, the voltage-dividing basic circuit includes a first output terminal and a second output terminal, the first output terminal is used to output a first internal power supply, and the second output terminal is used to output a second internal power supply; accordingly, the op amp includes a first op amp and a second op amp, the first input terminal of the first op amp is connected to the first output terminal, the second input terminal of the first op amp is connected to its output terminal, and the output terminal of the first op amp is output as a control power supply for the output transistor in the driving pull-up branch in the driving main circuit; the first input terminal of the second op amp is connected to the second output terminal, the second input terminal of the second op amp is connected to its output terminal, and the output terminal of the second op amp is output as a control power supply for the output transistor in the driving pull-down branch in the driving main circuit. In the embodiment of the present application, by outputting two internal power supplies, one of the internal power supplies is used as the control power supply for the output transistor in the driving pull-up branch, and the other internal power supply is used as the control power supply for the output transistor in the driving pull-down branch, so as to eliminate the influence of the body effect of the output transistor.

[0013] In combination with a possible implementation of the embodiment of the first aspect, the voltage division basic circuit includes: a first current limiting device, a second current limiting device, and a third current limiting device; the first end of the first current limiting device is connected to the first power supply, the second end of the first current limiting device is connected to the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is also connected to the first input end of the second op amp, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is also connected to the first input end of the first op amp, and the second end of the second current limiting device is the first output end. In the embodiment of the present application, the purpose of voltage division can be achieved by adopting the first current limiting device, the second current limiting device, and the third current limiting device, which has the advantages of simple structure and easy implementation.

[0014] In combination with a possible implementation of the embodiment of the first aspect, the voltage-dividing basic circuit includes: a first current-limiting device, a second current-limiting device, a third current-limiting device, and a fourth current-limiting device; the first end of the first current-limiting device is connected to the first power supply, the second end of the first current-limiting device is grounded through the second current-limiting device, the second end of the first current-limiting device is also connected to the first input end of the first op amp, and the second end of the first current-limiting device is the first output end; the first end of the third current-limiting device is connected to the first power supply, the second end of the third current-limiting device is grounded through the fourth current-limiting device, the second end of the third current-limiting device is also connected to the first input end of the second op amp, and the second end of the third current-limiting device is the second output end. In the embodiment of the present application, four current-limiting devices are used to form two voltage-dividing branches to obtain two internal power supplies, so that the adjustment of each internal power supply is more flexible.

[0015] In combination with a possible implementation of the embodiment of the first aspect, the current limiting device in the voltage-dividing basic circuit includes a current limiting resistor or a MOS tube. If the current limiting device is a MOS tube, the drain and the gate of the MOS tube serve as a connecting terminal. In the embodiment of the present application, a common current limiting resistor or MOS tube is used to form a voltage-dividing circuit, which can save circuit design costs while achieving the purpose of the invention.

[0016] In a possible implementation manner of the embodiment of the first aspect, the magnitude of the control power supply output by the first op amp as the output transistor in the driving pull-up branch is 0.5*VDDH-V1, and the magnitude of the control power supply output by the second op amp as the output transistor in the driving pull-down branch is 0.5*VDDH+V2, VDDH is the first power supply, V1 is the first preset threshold, and V2 is the second preset threshold. In the embodiment of the present application, by outputting two power supplies of specific magnitudes to eliminate the influence of the output transistor body effect, the signal quality output by the driving circuit can be further improved.

[0017] In the second aspect, an embodiment of the present application also provides an IO interface circuit, including a control logic circuit and an adaptive driving circuit provided in the above-mentioned first aspect embodiment and / or any possible implementation method combined with the first aspect embodiment, wherein the control logic circuit is used to provide a driving signal for the adaptive driving circuit.

[0018] In a third aspect, an embodiment of the present application further provides an IO interface chip, which integrates the IO interface circuit provided by the embodiment of the second aspect mentioned above.

[0019] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising a main body and an adaptive driving circuit provided by the above-mentioned first aspect embodiment and / or any possible implementation method combined with the first aspect embodiment, or an IO interface circuit provided by the above-mentioned second aspect embodiment.

[0020] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by implementing the embodiments of the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. As shown in the drawings, the above and other purposes, features and advantages of the present application will be clearer. The same reference numerals indicate the same parts in all the drawings. The drawings are not deliberately scaled to the actual size, and the focus is on showing the main purpose of the present application.

[0022] Figure 1 It is a schematic diagram of the circuit principle of the existing driving circuit.

[0023] Figure 2 A schematic structural diagram of an adaptive driving circuit provided in an embodiment of the present application is shown.

[0024] Figure 3 A structural schematic diagram of another adaptive driving circuit provided in an embodiment of the present application is shown.

[0025] Figure 4 A schematic diagram of the circuit principle of an adaptive driving circuit provided in an embodiment of the present application is shown.

[0026] Figure 5 A structural schematic diagram of another adaptive driving circuit provided in an embodiment of the present application is shown.

[0027] Figure 6 A circuit principle schematic diagram of another adaptive driving circuit provided in an embodiment of the present application is shown.

[0028] Figure 7 A circuit principle schematic diagram of another adaptive driving circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0030] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in an accompanying drawing, it is not necessary to further define and explain it in the subsequent drawings. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish an entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, article or equipment including a series of elements not only includes those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, article or equipment. In the absence of more restrictions, the elements limited by the statement "including one..." do not exclude the existence of other identical elements in the process, article or equipment including the elements.

[0031] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0032] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can also be an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] In view of the fact that the pull-up capability of the driving pull-up branch and the pull-down capability of the driving pull-down branch in the existing driving circuit do not match under different PVT (Process Voltage Temperature, a combination of process, voltage, and temperature) conditions, this will greatly deteriorate the problem of the output signal quality of the driving circuit, and the output on-resistance of the driving pull-up branch has a large deviation under different PVT conditions. In order to make the maximum on-resistance of the PMOS tube meet the design requirements when the gate-source voltage difference of the PMOS tube is small, it is necessary to increase the area of ​​the PMOS tube, which increases the layout area of ​​the entire driving circuit. The embodiment of the present application provides an adaptive driving circuit, which adopts an adaptive adjustment technology, uses a voltage divider circuit to divide the first power supply (such as VDDH), and uses the voltage obtained by the voltage division as the control power supply of the output transistor in the driving main circuit, so as to realize the dynamic adjustment function of the control power supply of the output transistor in the driving main circuit with the power supply VDDH, which can not only make the pull-up capability and the pull-down capability of the driving main circuit consistent under different PVT conditions, but also reduce the maximum on-resistance of the PMOS tube, thereby reducing the layout area of ​​the entire driving circuit.

[0034] For ease of understanding, the following will combine Figure 2 , the adaptive driving circuit provided in the embodiment of the present application is described. The adaptive driving circuit includes a voltage divider circuit and a driving main circuit.

[0035] The main driving circuit is used to output a driving signal, and the main driving circuit includes PMOS tubes P1 and P2, resistor R1, NMOS tubes N1 and N2, and resistor R2. Among them, resistor R1 and PMOS tubes P1 and P2 form a driving pull-up branch, and resistor R2 and NMOS tubes N1 and N2 form a driving pull-down branch. The resistance value of resistor R1 is consistent with the resistance value of resistor R2. Among them, transistor P2 and transistor N1 are output transistors in the main driving circuit. Figure 2 The pre_pgate is a square wave control signal of VDDL_1 to VDDH, and the pre_ngate is a square wave control signal of 0 to VDDL_1.

[0036] The control power supply of the output transistor in the driving main circuit is no longer a VDDL power supply independent of VDDH, but a power supply VDDL_1 obtained by dividing the first power supply (such as VDDH). Under different PVT conditions, VDDL_1 can dynamically change with the power supply VDDH and is affected by different PVT conditions in the same way.

[0037] Among them, the gate-source voltage |VGS| of the P1 tube when it is turned on is VDDH-VDDL_1, the |VGS| voltage of the P2 tube is vp1-VDDL_1, the |VGS| voltage of the N1 tube is VDDL_1-vn1, and the |VGS| voltage of the N2 tube is VDDL_1, where vp1 is the voltage at the source end of the P2 tube, vp1 is approximately equal to VDDH, and vn1 is the voltage at the source end of the N1 tube, and vn1 is approximately equal to 0. Assuming that VDDL_1 is 0.5*VDDH, the gate-source voltage |VGS| of the PMOS tube is 0.5*VDDHmin to 0.5*VDDHmax, and the gate-source voltage |VGS| of the NMOS tube is also 0.5*VDDHmin to 0.5*VDDHmax. Since the gate-source voltage |VGS| of the NMOS tube is equal to the gate-source voltage |VGS| of the PMOS tube, the on-resistance value of the NMOS tube is equal to the on-resistance value of the PMOS tube under different PVT conditions, that is, the on-resistance value of the driving pull-up branch is equal to the on-resistance value of the driving pull-down branch under different PVT conditions, so that the pull-up capability and pull-down capability of the driving main circuit are equal under different PVT conditions. Since the on-resistance value of the NMOS tube is equal to the on-resistance value of the PMOS tube under different PVT conditions, the pull-up capability and pull-down capability of the driving circuit are equal, thereby improving the output signal quality of the driving circuit.

[0038] Among them, the on-resistance formula of the MOS tube working in the linear region is:

[0039] Where μ is the carrier mobility of the MOS tube, Cox is the MOS gate oxide layer capacitance, W is the MOS tube channel width, L is the MOS tube channel length, |VGS| is the gate-source voltage of the MOS tube, and VTH is the MOS tube threshold voltage.

[0040] At the same time, the on-resistance of the PMOS tube has a smaller deviation under different PVT conditions than that of the traditional drive circuit. Under different PVT conditions, the minimum gate-source voltage of the PMOS tube changes from (VDDHmin-VDDLmax) to 0.5*VDDHmin relative to the traditional drive circuit. Compared with the traditional drive circuit, the gate-source voltage of the PMOS tube of the driving main circuit of the present application is larger, thereby making the maximum on-resistance of the PMOS tube smaller than that of the traditional drive circuit. In order to obtain the same effect as the maximum output resistance of the driving pull-up branch of the traditional drive circuit, the present application can reduce the layout area of ​​the drive circuit. It should be noted that under different PVT conditions, the influence on the power supply voltage is large, and its fluctuation range can reach 10%, that is, the voltage value under different PVT conditions can fluctuate within 10% above and below the standard value. For example, assuming the standard value is 2, the maximum value can be 2.2 and the minimum value can be 1.8.

[0041] For a better understanding, the gate-source voltage of the PMOS tube in the present application is larger than that in the traditional driving circuit. The following example is used to illustrate. If VDDH is 4, and VDDL=0.5VDDH is also assumed, then VDDHmin=4*0.9=3.6, VDDLmax=2*1.1=2.2, then the minimum gate-source voltage of the PMOS tube in the traditional driving circuit is VDDHmin-VDDLmax=3.6-2.2=1.4; and the minimum gate-source voltage of the PMOS tube in the present application is 0.5*VDDHmin=0.5*3.6=1.8. Compared with the traditional driving circuit, the gate-source voltage of the PMOS tube of the driving main circuit of the present application is larger, thereby making the maximum on-resistance of the PMOS tube smaller than that of the traditional driving circuit.

[0042] The first end of the voltage divider circuit is used to connect to the first power supply VDDH, the second end of the voltage divider circuit is grounded, the output end of the voltage divider circuit is connected to the driving main circuit, and the voltage divider circuit is used to output the control power supply of the output transistor (transistor P2, transistor N1) in the driving main circuit.

[0043] In an optional implementation manner, the voltage divider circuit includes: a voltage divider basic circuit and an operational amplifier, and its circuit diagram is shown as follows: Figure 3 As shown. The first end of the voltage divider basic circuit is used to connect to the first power supply, the second end of the voltage divider basic circuit is grounded, and the voltage divider basic circuit is used to output the internal power supply. The first input end of the operational amplifier is connected to the output end of the voltage divider basic circuit, the second input end of the operational amplifier is connected to its output end, and the output end of the operational amplifier outputs the control power supply of the output transistor in the driving main circuit. Optionally, the first input end of the operational amplifier is the in-phase input end, and the second input end of the operational amplifier is the inverting input end. Among them, the operational amplifier of the above connection method is equivalent to a unit gain buffer circuit. By further adding a unit gain buffer circuit, sufficient driving capability can be provided to enhance the driving capability of the voltage divider basic circuit.

[0044] When the voltage-dividing basic circuit includes only one output terminal, in one implementation mode, the voltage-dividing basic circuit includes: a first current-limiting device (such as represented by R3), a second current-limiting device (such as represented by R4), and its circuit diagram is as follows: Figure 4 As shown. The first end of the first current limiting device is connected to the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected to the first input end of the operational amplifier, and the second end of the first current limiting device is the output end of the voltage divider basic circuit. Optionally, the resistance value of the first current limiting device is consistent with the resistance value of the second current limiting device, so that VDDL_1 is 0.5*VDDH.

[0045] Among them, considering that the voltage of vp1 is not completely equal to VDDH, and the voltage of vn1 is not completely equal to 0, that is, the voltage between the source and substrate of the P2 tube is not equal to the voltage between the source and substrate of the N1 tube. Due to the influence of the MOS tube body effect, the threshold voltage of the P2 tube and the N1 tube will increase, and the on-resistance of the P2 tube and the N1 tube will increase. In order to offset the influence of the threshold voltage on the on-resistance, a voltage divider circuit can be used to generate two internal power supplies VDDL_1 and VDDL_2, where the voltage of VDDL_1 is equal to (0.5*VDDH-V1), and the voltage of VDDL_2 is equal to (0.5*VDDH+V2) to eliminate the influence of the body effect.

[0046] Wherein, V1 is the first preset threshold, V2 is the second preset threshold, optionally, V1=VDDH-vp1+ΔVth, V2=vn1+ΔVth, ΔVth is the threshold voltage change, wherein vp1 is the voltage at the source end of the P2 tube, vn1 is the voltage at the source end of the N1 tube, γ is the body effect coefficient, VSB is the source-substrate voltage difference, Φ F =(kT / q)ln(N sub / ni), k is the Boltzmann constant, T is the temperature, q is the charge, N sub is the doping concentration of the substrate, ni is the intrinsic carrier concentration. Since the value of ΔVth is very small and can be ignored, therefore, in one implementation, V1 = VDDH - vp1, V2 = vn1.

[0047] In another embodiment, the voltage-dividing basic circuit includes a first output terminal and a second output terminal, the first output terminal is used to output a first internal power supply (VDDL_1), and the second output terminal is used to output a second internal power supply (VDDL_2). Accordingly, the operational amplifier includes a first operational amplifier (such as buffer1) and a second operational amplifier (such as buffer2). The circuit diagram is shown in FIG. Figure 5 The first input terminal of the first op amp is connected to the first output terminal, the second input terminal of the first op amp is connected to the output terminal thereof, and the output terminal of the first op amp is output as a control power supply for an output transistor (P2) in a driving pull-up branch in the driving main circuit. The first input terminal of the second op amp is connected to the second output terminal, the second input terminal of the second op amp is connected to the output terminal thereof, and the output terminal of the second op amp is output as a control power supply for an output transistor (N1) in a driving pull-down branch in the driving main circuit.

[0048] When the voltage-dividing basic circuit includes two output terminals, in one implementation mode, the voltage-dividing basic circuit includes: a first current-limiting device (such as represented by R3), a second current-limiting device (such as represented by R4), and a third current-limiting device (such as represented by R5). The circuit diagram is shown in FIG. Figure 6The first end of the first current limiting device is connected to the first power supply, the second end of the first current limiting device is connected to the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is also connected to the first input end of the second op amp, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is also connected to the first input end of the first op amp, and the second end of the second current limiting device is the first output end.

[0049] When the voltage-dividing basic circuit includes two output terminals, in another implementation mode, the voltage-dividing basic circuit includes: the voltage-dividing basic circuit includes: a first current-limiting device (such as represented by R3), a second current-limiting device (such as represented by R4), a third current-limiting device (such as represented by R5), and a fourth current-limiting device (such as represented by R6), and its circuit diagram is shown in Figure 7 The first end of the first current limiting device is connected to the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected to the first input end of the first op amp, and the second end of the first current limiting device is the first output end; the first end of the third current limiting device is connected to the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is also connected to the first input end of the second op amp, and the second end of the third current limiting device is the second output end.

[0050] The current limiting device in the above-mentioned voltage-dividing basic circuit may be a resistor, or a MOS tube, a diode, etc. If the current limiting device is a MOS tube, the drain and gate of the MOS tube serve as a connection terminal, and the source of the MOS tube serves as another connection terminal. The MOS tube may be an NMOS tube or a PMOS tube. When it is an NMOS tube, the drain and gate of the MOS tube are grounded, and the source of the MOS tube is connected to the first power supply. When it is a PMOS tube, the drain and gate of the MOS tube are connected to the first power supply, and the source of the MOS tube is grounded.

[0051] It should be noted that, in an optional implementation, the voltage divider circuit may only include a voltage divider basic circuit. In this case, the voltage divider circuit is equivalent to the voltage divider basic circuit, so the voltage divider circuit including the voltage divider basic circuit and the operational amplifier cannot be understood as a limitation to the present application.

[0052] Based on the same inventive concept, the embodiment of the present application also provides an IO interface circuit, which includes a control logic circuit and the above-mentioned adaptive driving circuit. The control logic circuit is used to provide a driving signal for the adaptive driving circuit. For example, the control logic circuit is used to Figure 2 The adaptive driving circuit in provides a pre_pgate driving signal and a pre_ngate driving signal.

[0053] The adaptive driving circuit provided in the IO interface circuit embodiment has the same implementation principle and technical effects as those in the aforementioned adaptive driving circuit embodiment. For the sake of brief description, for matters not mentioned in the IO interface circuit embodiment, reference may be made to the corresponding contents in the aforementioned adaptive driving circuit embodiment.

[0054] Based on the same inventive concept, the embodiment of the present application also provides an IO interface chip, which integrates the above-mentioned adaptive driving circuit. The IO interface chip can be various commonly used IO interface chips, such as memory, processor, etc.

[0055] The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA). The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0056] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0057] The adaptive driving circuit provided in the IO interface chip embodiment has the same implementation principle and technical effects as those in the aforementioned adaptive driving circuit embodiment. For the sake of brief description, for matters not mentioned in the IO interface chip embodiment, reference may be made to the corresponding contents in the aforementioned adaptive driving circuit embodiment.

[0058] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes a body and the above-mentioned IO interface circuit or IO interface chip. The electronic device can be any electronic device including the IO interface circuit or IO interface chip, for example, a mobile phone, a tablet, a computer, a server, etc.

[0059] The adaptive driving circuit provided in the electronic device embodiment has the same implementation principle and technical effects as those in the aforementioned adaptive driving circuit embodiment. To briefly describe the parts not mentioned in the electronic device embodiment, reference may be made to the corresponding contents in the aforementioned adaptive driving circuit embodiment.

[0060] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0061] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An adaptive driving circuit, characterized in that: include: A driving main circuit, used for outputting a driving signal, wherein the power supply of the driving main circuit is a first power supply, the driving main circuit comprises a driving pull-up branch and a driving pull-down branch connected in parallel, the driving pull-up branch comprises a P-type output transistor, the driving pull-down branch comprises an N-type output transistor, and the P-type output transistor and the N-type output transistor are output transistors in the driving main circuit; A voltage divider circuit, wherein a first end of the voltage divider circuit is used to connect to a first power source, a second end of the voltage divider circuit is grounded, an output end of the voltage divider circuit is connected to the driving main circuit, and the voltage divider circuit is used to output a control power source as an output transistor in the driving main circuit, so that the gate-source voltage of the P-type output transistor is the same as the gate-source voltage of the N-type output transistor, so that the pull-up capability and the pull-down capability of the driving main circuit are consistent under different PVT conditions; Among them, the size of the control power supply of the output transistor in the driving pull-up branch output by the voltage divider circuit is 0.5*VDDH-V1, and the size of the control power supply of the output transistor in the driving pull-down branch output by the voltage divider circuit is 0.5*VDDH+V2, VDDH is the first power supply, V1 is the first preset threshold and is VDDH-vp1, V2 is the second preset threshold and is vn1, vp1 is the source voltage of the P-type output transistor, and vn1 is the source voltage of the N-type output transistor.

2. The adaptive driving circuit according to claim 1, characterized in that: The voltage divider circuit comprises: A voltage-dividing basic circuit, wherein a first end of the voltage-dividing basic circuit is used to connect the first power supply, a second end of the voltage-dividing basic circuit is grounded, and the voltage-dividing basic circuit comprises a first output end and a second output end, wherein the first output end is used to output a first internal power supply, and the second output end is used to output a second internal power supply; A first operational amplifier and a second operational amplifier, wherein the first input end of the first operational amplifier is connected to the first output end, the second input end of the first operational amplifier is connected to the output end thereof, and the output end of the first operational amplifier is output as a control power supply for an output transistor in a driving pull-up branch in the driving main circuit; The first input terminal of the second operational amplifier is connected to the second output terminal, the second input terminal of the second operational amplifier is connected to its output terminal, and the output terminal of the second operational amplifier is output as a control power supply for an output transistor in a driving pull-down branch in the driving main circuit.

3. The adaptive driving circuit according to claim 2, characterized in that: The voltage division basic circuit comprises: A first current limiting device, a second current limiting device, and a third current limiting device; The first end of the first current limiting device is connected to the first power supply, the second end of the first current limiting device is connected to the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is also connected to the first input end of the second op amp, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is also connected to the first input end of the first op amp, and the second end of the second current limiting device is the first output end.

4. The adaptive driving circuit according to claim 2, characterized in that: The voltage division basic circuit comprises: a first current limiting device and a second current limiting device, wherein the first end of the first current limiting device is connected to the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected to the first input end of the first operational amplifier, and the second end of the first current limiting device is the first output end; A third current limiting device and a fourth current limiting device, wherein the first end of the third current limiting device is connected to the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is also connected to the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end.

5. The adaptive driving circuit according to claim 2, characterized in that: The magnitude of the control power supply output by the first op amp as the output transistor in the driving pull-up branch is 0.5*VDDH-V1, and the magnitude of the control power supply output by the second op amp as the output transistor in the driving pull-down branch is 0.5*VDDH+V2, where VDDH is the first power supply.

6. An IO interface circuit, characterized in that: It comprises a control logic circuit and the adaptive driving circuit as described in any one of claims 1 to 5, wherein the control logic circuit is used to provide a driving signal for the adaptive driving circuit.

7. An IO interface chip, characterized in that: The IO interface circuit as claimed in claim 6 is integrated.

8. An electronic device, characterized in that: It comprises a main body and the IO interface circuit as claimed in claim 6, or the IO interface chip as claimed in claim 7.

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