Verification method and system of lrsc instruction in riscv instruction set

Abstract

The application relates to the technical field of processors, in particular to a verification method and system of an LRSC instruction in an RISCV instruction set, which comprises a single-core signal collector, a multi-core signal collector, an LR instruction queue, an SC instruction queue, a single-core controller, a multi-core controller, a local monitor, a global monitor, a memory model and a comparator; the application supports the LRSC instruction; if the address attribute of the LRSC instruction is cacheable, the related operation of lock grabbing is maintained in the local monitor; each core has an independent local monitor, and the cores perform lock grabbing operation through data consistency operation; if the address attribute of the LRSC instruction is non-cacheable, the related operation of lock grabbing is maintained in the global monitor; the global monitor is only one, monitors the LRSC access of all cores, and returns the access result. Through the verification method, whether the lock grabbing operation of the DUT is accurate can be effectively and accurately judged, and the verification method is suitable for processor verification of all RISCV architectures.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and specifically to a method and system for verifying LRSC instructions in the RISC-V instruction set. Background Technology

[0002] The RISC-CV instruction set includes two special instructions: LR (Load-Reserved) and SC (Store-Conditional). These instructions are used to implement synchronization between different processes. The LR instruction reads data from an address, the size of which can be one or two words, and stores it in the destination register, while setting a reserved bit in this address range. The SC instruction writes data to an address, the size of which can be one or two words, and checks whether the accessed address range has a reserved bit set. If not, it returns a non-zero value indicating failure; if so, it returns 0 to indicate success. If a process's SC instruction succeeds, it can execute the rest of its program. If SC fails, the LRSC instruction must be re-executed until SC succeeds before the rest of the program can proceed. This is the lock-preemption mechanism between different processes.

[0003] Existing technologies do not verify the LRSC instruction in the RISC-CV instruction set, and such verification requires tight coupling with the microarchitecture. Existing technologies may not be applicable to this project. This paper aims to verify whether the reserved bits are correctly set during the execution of LRSC and whether the result of SC is correct. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention discloses a verification method and system for the LRSC instruction in the RISC-CV instruction set. The method is used to verify whether the reserved bits are correctly set during the execution of LRSC and whether the result of SC is correct.

[0005] This invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a method for verifying LRSC instructions in the RISC-V instruction set, comprising the following steps:

[0007] S1 is initialized, monitoring DUT instruction emission information, determining the instruction type, and storing the instruction in the corresponding instruction queue;

[0008] S2 monitors the execution status of instructions in the DUT and synchronously updates the execution information to the corresponding instruction queue;

[0009] S3 determines whether the instruction has a cacheable address attribute. If so, it further determines whether the instruction has obtained data and then executes the instruction; otherwise, it proceeds to S5.

[0010] S4 monitors whether the SC instruction in the DUT is submitted, and further compares the result data of the DUT SC instruction with the result data of the SC instruction in the checker, or reports an error;

[0011] S5 monitors the read transmission on the bus interconnection in the DUT, and further executes the instruction to obtain data, or reports an error;

[0012] S6 monitors whether the instruction in the DUT obtains result data, and when the result data is obtained, the multicore controller stores the result data;

[0013] S7 monitors whether the LR instruction in the DUT is submitted, and further compares the data obtained by the DUT LR instruction with the data obtained by the LR instruction in the verification environment, or reports an error.

[0014] Further, in the method, the instruction type includes the LR instruction and the SC instruction.

[0015] Further, in the method, the execution of the instruction in the DUT is monitored, and the execution information is synchronously updated to the instruction queue, wherein the information includes the LR access address, the access size and the access address attribute.

[0016] Further, in the method, whether the instruction in the DUT obtains data is monitored, and when the instruction obtains data, the single-core controller in the verification environment starts to execute the instruction, accesses the memory model according to the information in the instruction queue to obtain data, and updates the information in the local monitor.

[0017] Further, in the method, whether the instruction in the DUT is submitted is monitored, and when the instruction is submitted, the data obtained by the DUT instruction is compared with the data obtained by the instruction in the verification environment, and if the data is inconsistent, an error is reported.

[0018] Further, in the method, if the LR instruction with the non-cacheable address attribute is executed in the verification environment, the read transmission on the bus interconnection in the DUT is monitored, and if the address attribute of the read transmission is non-cacheable and exclusive access, it is judged that the read transmission is initiated by a LR instruction with a non-cacheable address attribute.

[0019] Further, in the method, the multicore controller searches for the oldest LR instruction in the LR instruction queue which matches the write transmission address, the access size and the address attribute information, if such an LR instruction is found, the instruction is executed to access the memory model to obtain data, and the information in the global monitor is updated, and if such an LR instruction is not found, an error is reported.

[0020] Further, in the method, if the SC instruction with the non-cacheable address attribute is executed in the verification environment, the write transmission on the bus interconnection in the DUT is monitored, if the address attribute of the write transmission is non-cacheable and the access is exclusive, it is judged that the write transmission is initiated by the SC instruction with the non-cacheable address attribute.

[0021] Further, in the method, the multi-core controller searches the SC instruction queue for the oldest SC instruction matching the write transmission address, the access size, the address attribute and the like, if such SC instruction is found, the instruction is executed, the global monitor is accessed, and the following access results are returned:

[0022] If the core id matches the address range, the SC instruction successfully obtains the lock, the successful result is returned to the core, and the write data is written into the memory model;

[0023] If the core id does not match, the SC instruction fails, the global monitor does not need to be updated, the data does not need to be written into the memory, and the failure result of the SC instruction is returned to the core;

[0024] If the core id matches but the address range does not match, the SC instruction fails, the domain of the global monitor is cleared, the data does not need to be written into the memory, and the failure result of the SC instruction is returned to the core;

[0025] If no such SC instruction is found in the SC queue, an error is reported.

[0026] In a second aspect, the application provides a verification system of the LRSC instruction in the RISCV instruction set, which is used to implement the verification method of the LRSC instruction in the RISCV instruction set in the first aspect, and includes

[0027] The single-core signal collector is used to collect the LRSC instruction conditions of each core in the multi-core system of the DUT, including the access address, the address attribute, the access size, the read-write data and the instruction execution condition, and the LRSC instruction information is stored in the LR instruction queue and the SC instruction queue respectively, and the LRSC instruction execution information is transmitted to the single-core controller;

[0028] The multi-core signal collector is used to collect the LRSC-related transmission on the bus interconnection in the multi-core system of the DUT, including the access address, the access size, the read-write data and the core id information, and the information is transmitted to the multi-core controller;

[0029] The LR instruction queue is used to store the information of the LR instruction in each core, including the access address, the address attribute and the access size information;

[0030] The SC instruction queue is used to store the information of the SC instruction in each core, including the access address, the address attribute, the access size and the write data information;

[0031] Single core controller, if the LRSC address attribute is cacheable, the lock stealing operation in the verification environment is controlled by the single core controller, the single core signal collector delivers the execution of the LRSC instruction to the single core controller;

[0032] When the LR instruction in the DUT gets the data, the single core controller starts to execute the LR instruction in the verification environment, finds the corresponding LR instruction from the LR instruction queue, gets the address, access size and other information, accesses the memory model, gets the data, and at the same time accesses the local monitor, updates the address and access size fields in the local monitor, and sets the valid bit;

[0033] When the SC instruction in the DUT gets the result data, the single core controller starts to execute the SC instruction in the verification environment, finds the corresponding SC instruction from the SC queue, gets the address, access size, write data and other information, first accesses the local monitor, if the access range of the SC instruction is included in the range monitored by the local monitor and the valid bit is 1, it indicates that the result of the SC instruction is successful, otherwise it is a failure, if successful, the single core controller writes the write data of the SC instruction into the memory model, if failed, the memory model does not need to be updated; finally, the single core controller saves the result of the LRSC and waits for comparison with the DUT result;

[0034] Multi-core controller, if the LRSC address attribute is not cacheable, the lock stealing operation in the verification environment is controlled by the multi-core controller, the multi-core signal collector delivers the transmission information related to the LRSC on the bus interconnection to the multi-core controller;

[0035] If the transmission is a read request initiated by the LR instruction, the multi-core controller finds the corresponding LR instruction in the LR instruction queue according to the core id, access address and access size information in the transmission, and executes the LR instruction, accesses the memory model, and gets the data, at the same time, accesses the global monitor, updates the address, access size field and core id in the global monitor, and sets the valid bit;

[0036] If the transmission is a write request initiated by the SC instruction, the multi-core controller finds the corresponding SC instruction in the SC instruction queue according to the core id, access address and access size information in the transmission, first accesses the global monitor, if the core id and address range match and the valid bit is 1, it indicates that the SC instruction gets the lock and can return a successful result, at the same time, writes the write data of the SC instruction into the memory model, if the result of accessing the global monitor is failure, the data does not need to be written into the memory, and the SC failure result is returned at the same time;

[0037] If the transmission is a normal write transmission, the multi-core controller will access the global monitor to compare whether the address range overlaps, if there is overlap, the fields of the global monitor are cleared and the valid bit is 0;

[0038] Local monitor, LR instruction will set the local monitor of each domain, SC instruction will clear the local monitor of each domain, regardless of the result is failed or successful, the ordinary store instruction, if the access range is within the address range monitored by the local monitor, also clear the local monitor of each domain, store instruction can be the core, also from other cores in the multi-core system;

[0039] Global monitor, LR instruction will set the global monitor of each domain, when there is a new LR instruction, the domain of the global monitor will be updated. SC instruction is successful, will clear the global monitor of each domain, if failed, will not change the global monitor; ordinary store instruction write transmission, if hit in the same address range, also clear the global monitor domain, regardless of the write transmission from which core;

[0040] Memory model, used to verify the memory model in the environment, read operation reads data from the memory model, write operation updates data into the memory model.

[0041] Comparator, used to compare the LRSC result of DUT and the LRSC result in the verification environment, and print the comparison result.

[0042] The beneficial effects of the present application are:

[0043] The present application verifies the LRSC instruction in the RISCV instruction set, especially the lock stealing operation existing in the multi-core system, through the method of the present application, whether the DUT lock stealing operation is accurate can be effectively and accurately judged. At the same time, the verification method of the present application supports the verification of LRSC instruction with cacheable and non-cacheable address attributes, covering all mixed cases of LRSC and ordinary instructions. In addition, by modifying the interface with the DUT, the verification method of the present application can be applied to the verification of all RISCV architecture processors. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0045] Figure 1 It is a multi-core structure diagram supported by the LRSC instruction of the present application;

[0046] Figure 2 It is a verification method structure diagram of the present application. DETAILED DESCRIPTION

[0047] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0048] Embodiment 1

[0049] The embodiment provides a verification method of an LRSC instruction in an RISCV instruction set, and comprises the following steps:

[0050] S1 initialization, monitoring of DUT instruction transmission information, judgment of instruction type, storage of the instruction into a corresponding instruction queue;

[0051] S2 monitoring of execution of the instruction in the DUT, and synchronization of execution information to the corresponding instruction queue;

[0052] S3 judgment of whether the instruction is a cacheable address attribute, if yes, further judgment of whether the instruction obtains data, and then execution of the instruction; if no, S5 is entered;

[0053] S4 monitoring of whether the SC instruction in the DUT is submitted, and then comparison of result data of the DUT SC instruction and result data of the SC instruction in the checker, or error reporting;

[0054] S5 monitoring of read transmission on the bus interconnection in the DUT, and further execution of the instruction, obtaining of data, or error reporting;

[0055] S6 monitoring of whether the instruction in the DUT obtains result data, when the result data is obtained, the multi-core controller stores the result data;

[0056] S7 monitoring of whether the LR instruction in the DUT is submitted, and then comparison of data obtained by the DUT LR instruction and data obtained by the LR instruction in the verification environment, or error reporting.

[0057] Referring to Figure 1 If the address attribute of the LRSC instruction is cacheable, the related operation of lock stealing is maintained in the local monitor, each core has its own independent local monitor, and the cores perform the lock stealing operation through data consistency operation.

[0058] If the address attribute of the LRSC instruction is non-cacheable, the related operation of lock stealing is maintained in the global monitor, the global monitor is only one, monitors the LRSC access of all cores, and returns the access result.

[0059] The embodiment verifies whether the LRSC correctly sets the reserved bit during execution and whether the result of the SC is correct.

[0060] The embodiment verification method verifies the LRSC instruction in the RISCV instruction set; by establishing a local monitor and a global monitor, the LRSC instruction verification with cacheable and non-cacheable address attributes can be supported.

[0061] The embodiment verification method is applicable to a multi-core system under the RISCV architecture, and the number of cores can be configured; by modifying the DUT monitoring interface, the embodiment verification method can be effectively adapted to other RISCV architecture DUTs, and has universality.

[0062] Embodiment 2

[0063] At the specific implementation level, the embodiment provides an execution flow of the LR instruction with a cacheable address attribute in a verification environment:

[0064] The DUT instruction emission information is monitored, and if it is an LR instruction, the instruction is stored in the LR instruction queue;

[0065] The execution of the LR instruction in the DUT is monitored, and the execution information is synchronously updated to the LR instruction queue, and the information includes the LR access address, the access size, the access address attribute, etc.

[0066] It is monitored whether the LR instruction obtains data in the DUT, when the LR instruction obtains data, the single-core controller in the verification environment starts to execute the LR instruction, accesses the memory model according to the information in the LR instruction queue, obtains data, and updates the information in the local monitor;

[0067] It is monitored whether the LR instruction is submitted in the DUT, when the LR instruction is submitted, the data obtained by the DUT LR instruction and the data obtained by the LR instruction in the verification environment are compared, if they are inconsistent, an error is reported.

[0068] Embodiment 3

[0069] At the specific implementation level, the embodiment provides an execution flow of the SC instruction with a cacheable address attribute in a verification environment:

[0070] The DUT instruction emission information is monitored, and if it is an SC instruction, the instruction is stored in the SC instruction queue;

[0071] The execution of the SC instruction in the DUT is monitored, and the execution information is synchronously updated to the SC instruction queue, and the information includes the SC access address, the access size, the access address attribute, the write data, etc.

[0072] Monitoring whether the SC instruction in the DUT obtains result data, when the SC instruction obtains result data, the single-core controller starts to execute the SC instruction, accesses the memory model according to information in the SC instruction queue, and accesses the local monitor to obtain result data and update the local monitor;

[0073] Monitoring whether the SC instruction in the DUT is submitted, when the SC instruction is submitted, comparing result data of the DUT SC instruction with result data of the SC instruction in the checker, if the result data are inconsistent, an error is reported.

[0074] Embodiment 4

[0075] At the implementation level, the embodiment provides an execution flow of the LR instruction with the non-cacheable address attribute in the verification environment:

[0076] Monitoring DUT instruction emission information, if the instruction is an LR instruction, the instruction is stored in the LR instruction queue;

[0077] Monitoring execution of the LR instruction in the DUT, and synchronously updating execution information to the LR instruction queue, the execution information including LR access address, access size, access address attribute, etc.

[0078] Monitoring read transmission on the bus interconnection in the DUT, if the address attribute of the read transmission is non-cacheable and exclusive access, it can be judged that the read transmission is initiated by an LR instruction with a non-cacheable address attribute.

[0079] The multi-core controller in the embodiment finds the oldest LR instruction in the LR instruction queue which matches write transmission address, access size, address attribute, etc., if such an LR instruction is found, the instruction is executed, the memory model is accessed, data is obtained, and information in the global monitor is updated, if such an LR instruction is not found, an error is reported;

[0080] Monitoring whether the LR instruction in the DUT obtains data, when the LR instruction obtains data, the multi-core controller stores the data;

[0081] Monitoring whether the LR instruction in the DUT is submitted, when the LR instruction is submitted, comparing data obtained by the DUT LR instruction with data obtained by the LR instruction in the verification environment, if the data are inconsistent, an error is reported.

[0082] Embodiment 5

[0083] At the implementation level, the embodiment provides an execution flow of the SC instruction with the non-cacheable address attribute in the verification environment:

[0084] Monitoring DUT instruction emission information, if the instruction is an SC instruction, the instruction is stored in the SC instruction queue;

[0085] Monitoring the execution of SC instructions in the DUT, and synchronously updating the execution information to the SC instruction queue, which includes SC access address, access size, access address attribute, write data, etc.

[0086] Monitoring the write transmission on the bus interconnection in the DUT, if the address attribute of the write transmission is non-cacheable, and is exclusive access, it can be judged that the write transmission is initiated by a non-cacheable address attribute SC instruction, and the multi-core controller searches for the oldest SC instruction in the SC instruction queue that matches the write transmission address, access size, address attribute, etc.

[0087] If such an SC instruction is found, the instruction is executed, and the global monitor is accessed, and the following access results are obtained in this embodiment:

[0088] a) If the core id matches the address range, the SC instruction successfully obtains the lock, returns the successful result to the core, and writes the write data into the memory model;

[0089] b) If the core id does not match, the SC instruction fails, and the global monitor does not need to be updated, nor does the data need to be written into the memory, and the SC instruction failure result is returned to the core;

[0090] c) If the core id matches but the address range does not match, the SC instruction fails, the domain of the global monitor is cleared, the data does not need to be written into the memory, and the SC instruction failure result is returned to the core;

[0091] If no such SC instruction is found in the SC queue, an error is reported;

[0092] Monitoring whether the SC instruction in the DUT obtains the result data, when the SC instruction obtains the result data, the multi-core controller stores the result data;

[0093] Monitoring whether the SC instruction in the DUT is submitted, when the SC instruction is submitted, comparing the result data of the DUT SC instruction with the result data of the SC instruction in the checker, if they are inconsistent, an error is reported.

[0094] Embodiment 6

[0095] Referring to Figure 2 The embodiment provides a verification system of an LRSC instruction in a RISCV instruction set, which comprises

[0096] A single-core signal collector is configured to collect the LRSC instruction of each core in the DUT multi-core system, including access address, address attribute, access size, read-write data, instruction execution, etc., and store the LRSC instruction information into the LR instruction queue and the SC instruction queue respectively, and the LRSC instruction execution information is transmitted to the single-core controller.

[0097] A multi-core signal collector is used to collect the LRSC related transmission on the bus interconnection in the DUT multi-core system, including access address, access size, read / write data, core id number and other information, and deliver the information to the multi-core controller.

[0098] An LR instruction queue is used to store the LR instruction information in each core, including access address, address attribute, access size and other information.

[0099] An SC instruction queue is used to store the SC instruction information in each core, including access address, address attribute, access size, write data and other information.

[0100] A single-core controller is used to control the lock stealing operation in the verification environment if the LRSC address attribute is cacheable. The single-core signal collector delivers the execution of the LRSC instruction to the single-core controller.

[0101] When the LR instruction in the DUT obtains data, the single-core controller starts to execute the LR instruction in the verification environment, finds the corresponding LR instruction from the LR instruction queue, obtains the address, access size and other information, accesses the memory model, obtains the data, and accesses the local monitor to update the address and access size field in the local monitor and set the valid bit.

[0102] When the SC instruction in the DUT obtains result data, the single-core controller starts to execute the SC instruction in the verification environment, finds the corresponding SC instruction from the SC queue, obtains the address, access size, write data and other information, first accesses the local monitor, and if the access range of the SC instruction is included in the range monitored by the local monitor and the valid bit is 1, it indicates that the result of the SC instruction is successful, otherwise it is a failure. If successful, the single-core controller writes the write data of the SC instruction into the memory model, and if failed, the memory model does not need to be updated.

[0103] In addition, the single-core signal collector collects the data consistency request from the secondary cache, if the type of the request is to invalidate the cacheline in the primary cache, and the address is the same as the address recorded in the local monitor, the information of the local monitor needs to be cleared and the valid bit is set to 0.

[0104] Finally, the single-core controller saves the result of the LRSC and waits for comparison with the result of the DUT.

[0105] A multi-core controller is used to control the lock stealing operation in the verification environment if the LRSC address attribute is non-cacheable. The multi-core signal collector delivers the LRSC related transmission information on the bus interconnection to the multi-core controller.

[0106] If the transfer is a read request initiated by the LR instruction, the multi-core controller finds the corresponding LR instruction in the LR instruction queue based on the core ID, access address, access size, and other information in the transfer, and executes the LR instruction to access the memory model and obtain the data. At the same time, the controller accesses the global monitor, updates the address, access size field, and core ID in the global monitor, and sets the valid bit.

[0107] If the transfer is a write request initiated by an SC instruction, the multi-core controller finds the corresponding SC instruction in the SC instruction queue based on information such as the core ID, access address, and access size in the transfer. It first accesses the global monitor. If the core ID and address range match, and the valid bit is 1, it indicates that the SC instruction has acquired the lock, and a success result can be returned. Simultaneously, the write data of the SC instruction is written to the memory model. If the access to the global monitor results in failure, no data needs to be written to memory, and a failure result for the SC instruction is returned.

[0108] If the transfer is a normal write transfer, the multi-core controller will access the global monitor and compare whether the address ranges overlap. If they overlap, the global monitor's fields will be cleared and the valid bits will be set to 0.

[0109] The local monitor, whose structure is shown in the table below, allows each core to monitor only one address range. The LR instruction sets the various fields of the local monitor, and the SC instruction clears them, regardless of success or failure. Additionally, the regular store instruction, if accessing an address range within the monitored address range, will also clear the local monitor's fields. The store instruction can originate from the local core or from other cores in a multi-core system.

[0110] Domain Description Vld Valid bit Addr Address Rq len Access size, usually one or two words

[0111] The global monitor, whose structure is shown in the table below, has only one global monitor in a multi-core system and monitors only one address. The LR instruction sets the various fields of the global monitor, and updates them when a new LR instruction arrives. The SC instruction clears the global monitor's fields upon success; otherwise, it does not modify the global monitor. Ordinary store instructions, when writing data, also clear the global monitor's fields if they hit the same address range, regardless of which core the write originated from.

[0112] Domain Description Vld Valid bit Addr Address Cid Core's id number Rq len Access size, usually one or two words

[0113] The memory model is used to verify the memory model in the environment. Read operations read data from the memory model, and write operations update the data into the memory model.

[0114] a comparator for comparing the LRSC result of the DUT and the LRSC result in the verification environment and printing the comparison result.

[0115] In summary, the present application verifies the LRSC instruction in the RISCV instruction set, especially the lock stealing operation existing in the multi-core system. Through the method of the present application, it can effectively and accurately judge whether the DUT lock stealing operation is accurate. At the same time, the verification method of the present application supports the verification of LRSC instructions with cacheable and non-cacheable address attributes, covering all mixed cases of LRSC and ordinary instructions. In addition, by modifying the interface with the DUT, the verification method of the present application can be applied to the verification of all RISCV architecture processors.

[0116] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit it; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for verifying an LRSC instruction in a RISCV instruction set, characterized in that, The method comprises the following steps: S1 initialization, monitoring DUT instruction transmission information, judging instruction type, and storing the instruction into a corresponding instruction queue; S2 monitoring execution of the instruction in the DUT, and synchronously updating execution information to the corresponding instruction queue; S3 judging whether the instruction is a cacheable address attribute, if yes, further judging whether the instruction obtains data, and then executing the instruction; if no, entering S5; S4 monitoring whether the SC instruction in the DUT is submitted, if yes, further comparing result data of the DUT SC instruction with result data of the SC instruction in the checker, or reporting an error; S5 monitoring read transmission on the bus interconnection in the DUT, and further executing the instruction, if the instruction is executed, data is obtained, if the instruction cannot be executed, or an error is reported; if the LR instruction with the non-cacheable address attribute is executed in the verification environment, monitoring read transmission on the bus interconnection in the DUT, if the address attribute of the read transmission is non-cacheable and exclusive, it is judged that the read transmission is initiated by the LR instruction with the non-cacheable address attribute; if the SC instruction with the non-cacheable address attribute is executed in the verification environment, monitoring write transmission on the bus interconnection in the DUT, if the address attribute of the write transmission is non-cacheable and exclusive, it is judged that the write transmission is initiated by the SC instruction with the non-cacheable address attribute; S6 monitoring whether the instruction in the DUT obtains result data, when the result data is obtained, the multi-core controller stores the result data; S7 monitoring whether the LR instruction in the DUT is submitted, if yes, further comparing data obtained by the DUT LR instruction with data obtained by the LR instruction in the verification environment, or reporting an error. 2.The method of claim 1, wherein, In the method, the instruction type comprises an LR instruction and an SC instruction. 3.The method of claim 1, wherein, In the method, execution of the instruction in the DUT is monitored, and execution information is synchronously updated to the instruction queue, wherein the information comprises an LR access address, an access size and an access address attribute.

4. The verification method of an LRSC instruction in a RISCV instruction set according to claim 3, characterized in that, In the method, whether the instruction in the DUT obtains data is monitored, when the instruction obtains data, the single-core controller in the verification environment starts to execute the instruction, accesses the memory model according to information in the instruction queue, obtains data, and updates information in the local monitor.

5. The method of claim 4, wherein the LRSC instruction is a RISC-V instruction set. In the method, whether the instruction in the DUT is submitted is monitored, when the instruction is submitted, data obtained by the DUT instruction is compared with data obtained by the instruction in the verification environment, if the data is inconsistent, an error is reported.

6. The method of claim 1, wherein the LRSC instruction is one of a RISC-V instruction set. In the method, the multi-core controller searches for an oldest LR instruction matched with write transmission address, access size and address attribute information in the LR instruction queue, if such an LR instruction is found, the instruction is executed, the memory model is accessed, data is obtained, and information in the global monitor is updated, if such an LR instruction is not found, an error is reported.

7. The method of claim 1, wherein the LRSC instruction is one of a RISC-V instruction set. In the method, the multi-core controller searches for an oldest SC instruction matched with write transmission address, access size and address attribute information in the SC instruction queue, if such an SC instruction is found, the instruction is executed, the global monitor is accessed, and the following access result is obtained: If the core id matches the address range, the SC instruction successfully obtains the lock, returns the success result to the core, and writes the write data into the memory model; If the core id does not match, the SC instruction fails, the global monitor does not need to be updated, and the data does not need to be written into the memory, and the failure result of the SC instruction is returned to the core; If the core id matches but the address range does not match, the SC instruction fails, the domain of the global monitor is cleared, and the data does not need to be written into the memory, and the failure result of the SC instruction is returned to the core; If no such SC instruction is found in the SC queue, an error is reported.

8. A verification system of an LRSC instruction in a RISCV instruction set, the system is used to implement the verification method of the LRSC instruction in the RISCV instruction set according to any one of claims 1-7, characterized in that, The method comprises the following steps: a single-core signal collector is used to collect the LRSC instruction conditions of each core in the DUT multi-core system, including access address, address attribute, access size, read-write data, and instruction execution condition, and the LRSC instruction information is stored into the LR instruction queue and the SC instruction queue respectively, and the LRSC instruction execution information is transmitted to the single-core controller; a multi-core signal collector is used to collect the LRSC-related transmission on the bus interconnection in the DUT multi-core system, including access address, access size, read-write data, and core id number information, and the information is transmitted to the multi-core controller; an LR instruction queue is used to store the information of the LR instruction of each core, including access address, address attribute, and access size information; an SC instruction queue is used to store the information of the SC instruction of each core, including access address, address attribute, access size, and write data information; a single-core controller is used to verify the lock operation in the verification environment if the LRSC address attribute is cacheable, and the single-core signal collector transmits the execution condition of the LRSC instruction to the single-core controller; when the DUT obtains the data of the LR instruction, the single-core controller starts to execute the LR instruction in the verification environment, finds the corresponding LR instruction from the LR instruction queue, obtains the address and access size information, accesses the memory model, obtains the data, and accesses the local monitor to update the address and access size domain in the local monitor and set the valid bit; when the DUT obtains the result data of the SC instruction, the single-core controller starts to execute the SC instruction in the verification environment, finds the corresponding SC instruction from the SC queue, obtains the address, access size, and write data information, first accesses the local monitor, if the access range of the SC instruction is included in the range monitored by the local monitor and the valid bit is 1, it indicates that the result of the SC instruction is successful, otherwise it is a failure, if successful, the single-core controller writes the write data of the SC instruction into the memory model, if failed, the memory model does not need to be updated; finally, the single-core controller saves the result of the LRSC and waits for comparison with the DUT result; a multi-core controller is used to verify the lock operation in the verification environment if the LRSC address attribute is non-cacheable, and the multi-core signal collector transmits the LRSC-related transmission information on the bus interconnection to the multi-core controller. If the transmission is a read request initiated by the LR instruction, the multi-core controller finds the corresponding LR instruction in the LR instruction queue according to the core id, access address, access size information in the transmission, and executes the LR instruction to access the memory model to obtain data, and at the same time, the controller accesses the global monitor to update the address, access size domain, core id in the global monitor, and set the valid bit; If the transmission is a write request initiated by the SC instruction, the multi-core controller finds the corresponding SC instruction in the SC instruction queue according to the core id, access address, access size information in the transmission, and first accesses the global monitor. If the core id and address range are matched, and the valid bit is 1, it means that the SC instruction has obtained the lock, and a successful result can be returned, and at the same time, the write data of the SC instruction is written into the memory model. If the result of accessing the global monitor is failure, the data does not need to be written into the memory, and a SC failure result is returned; If the transmission is a normal write transmission, the multi-core controller will access the global monitor to compare whether the address range has overlap. If there is overlap, the domain of the global monitor is cleared, and the valid bit is 0; The local monitor, the LR instruction sets each domain of the local monitor, the SC instruction clears each domain of the local monitor, and the normal store instruction also clears each domain of the local monitor if the access range is within the address range monitored by the local monitor, regardless of the result being failure or success. The store instruction is from the local core or from other cores in the multi-core system; The global monitor, the LR instruction sets each domain of the global monitor, and when a new LR instruction comes, the domain of the global monitor is updated. When the SC instruction succeeds, each domain of the global monitor is cleared. If it fails, the global monitor will not be changed. If the normal store instruction write transmission hits the same address range, the domain of the global monitor will also be cleared, regardless of which core the write transmission comes from; The memory model is used to verify the memory model in the environment. The read operation reads data from the memory model, and the write operation updates data into the memory model; The comparator is used to compare the LRSC result of the DUT with the LRSC result in the verification environment, and print the comparison result.

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