Method and system for implementing fast deallocation of crq and cwq in l2
By using an arbitration module and queue management methods, the entry items of CRQ/CWQ can be quickly dealt and allocated, solving the queue overflow problem and improving CPU performance.
Patent Information
- Application Number
- CN202111369637.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-16
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2041-11-16
AI Technical Summary
CRQ and CWQ cannot be quickly dealt with in L2, leading to queue overflow, inability to accept new requests, and impacting CPU performance.
The arbitration module selects requests to enter the pipeline and allocates them according to the request type, TAG information and MESI status information in L2. It quickly deals and allocates CRQ/CWQ entries and manages requests using queues such as ORQ, WRQ, EFQ and CPQ to ensure smooth request processing.
Fast deallocation of CRQ/CWQ is achieved, which improves the overall performance of the CPU and ensures that L2 can receive new requests in a timely manner.
Smart Images
Figure CN114238173B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of CPU technology, and specifically to a method and system for fast deallocate of CRQ and CWQ in L2. Background Technology
[0002] The role of CRQ (core read queue) and CWR (core write queue) in L2 is to place LSU read and write requests in the queue. Each core has a CRQ and a CWR. If the queue cannot be dealt with quickly, it will become full quickly, thus preventing the core from receiving new requests. The speed of L1 reload request response will seriously affect the overall CPU performance.
[0003] To address this issue, we propose that the core read queue (CRQ) and core write queue (CWR) can deallocate the corresponding entry items as long as they have been arbitrated and are on the pipeline. If the CRQ / CWQ can complete normally, the LSU is responded normally; if it cannot complete normally, full access is given to the OQ (outstanding queue). This ensures that the CRQ / CWQ entry items are deallocated as quickly as possible. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention discloses a method and system for fast deallocate of CRQ and CWQ in L2, which solves the problem that the CRQ / CWQ entry item maintains the complete lifecycle of LSU read and write requests in L2, resulting in the CRQ / CWQ entry item being deallocated very late, and ultimately L2 being unable to receive new read and write requests from L1 due to CRQ / CWQ full.
[0005] This invention is achieved through the following technical solution:
[0006] In a first aspect, the present invention provides a method for fast deallocate of CRQ and CWQ in L2, comprising the following steps:
[0007] S1 receives requests from the core and external extends. The arbitration module receives requests from CRQ, CWQ, EPQ, ORQ, EFQ, and CPQ, and selects one of these requests to enter the pipeline.
[0008] S2 determines the data or permissions required by the downstream based on the request type and the TAG and MESI status information in the current L2, and allocates them accordingly.
[0009] S3 sends read or write requests to downstream memory via L2, and the downstream memory returns reload data to populate EFQ;
[0010] S4 runs on the L2de pipeline of EFQ and writes the reloaded data into L2$, while returning the data to the requested core.
[0011] Among them, the requests from the core are either load miss requests or lsu eviction requests.
[0012] Furthermore, in the method, receiving requests from the core and external extend includes receiving read requests from the core and placing them in a CRQ; receiving write requests from the core and placing them in a CWQ; and receiving probe requests from external sources and placing them in an EPQ.
[0013] Furthermore, the method is characterized in that, in the pipeline, it is determined whether it is possible to directly write to L2 based on the type of request and the TAG information and MESI status information in the current L2.
[0014] Can data be directly returned to the requester? Is it necessary to reload data or grant permissions to downstream memory? Is it necessary to generate an evict? Is it necessary to write data to downstream memory? Is it necessary to probe the core?
[0015] Furthermore, in the method, if it is determined that data or permissions need to be reloaded to the downstream memory, an ORQ is allocated; if it is determined that data needs to be written to the downstream memory, a WRQ is allocated; if it is determined that a probe to the core is needed, a CPQ is allocated. L2 sends probe requests to the core, all of which are accomplished through CPQ.
[0016] Furthermore, in the method, when a read request is sent to the downstream memory via L2, it is sent via ORQ to read the data from the downstream memory and obtain the corresponding permissions for the data.
[0017] Furthermore, in the method, when a write request is sent to the downstream memory via L2, data is written from L2 to the next level memory via WRQ.
[0018] Furthermore, the method includes the following steps when making a load miss request:
[0019] A load miss request is issued from the core, and a CRQ entry is allocated.
[0020] The CRQ's Load Miss request is uploaded to the pipeline and wins arbitration, then uploaded to the pipeline;
[0021] If tag_ram is hit, the corresponding entry in CRQ is directly deallocated;
[0022] If `miss`, then `tag_ram` will allocate the ORQ and deallocate the corresponding entry in the CRQ.
[0023] ORQ sends a reload request to the next level of memory and waits for the data to be refilled.
[0024] Lower-level memory backfill data is written into EFQ;
[0025] EFQ participated in and obtained pipeline arbitration;
[0026] Update L2 tag_ram and data_ram to return the data to the core, and deallocate the corresponding ORQ and EFQ entry items.
[0027] Furthermore, the method includes the following steps when making an lsu eviction request:
[0028] The lsu eviction request is issued from the core and allocates a CWQ entry item;
[0029] CWQ's lsu eviction request was submitted to the pipeline and won arbitration, submitted to the pipeline;
[0030] If tag_ram is hit, the corresponding entry in CWQ is directly deallocated, and a response is given to lsu.
[0031] If the tag_ram is missing, then allocate the WRQ and write the data into the WRQ. If the same tag already exists in the WRQ, then merge the eviction data into the WRQ.
[0032] WRQ writes the data to the next level of memory;
[0033] The lower-level memory will respond to WRQ and deallocate the entry item corresponding to WRQ.
[0034] Secondly, the present invention provides a fast deallocate implementation system for CRQ and CWQ in L2, the system being used to implement the fast deallocate implementation method for CRQ and CWQ in L2 as described in the first aspect, including probe, eviction, TAG RAM, DATA RAM, CRQ, CWQ, EPQ, ORQ, WRQ, EFQ and CPQ.
[0035] Furthermore, the probe is used for spying and listening, probing dirty data in the core or modifying the MESI status information in the core in order to obtain E privileges;
[0036] The eviction is used to keep the data stored in the cache relatively new, and is generated when data needs to be replaced out of the cache;
[0037] The TAG RAM is used to record the cacheline's addr and the cacheline's MESI status information in L2 and all L2 cores;
[0038] The DATA RAM is used to record cacheline data information;
[0039] The CRQ is a queue used to receive read requests from the core.
[0040] The CWQ is a queue used to receive write requests from the core;
[0041] The EPQ is a queue used to receive probe requests from external sources;
[0042] The ORQ is used when a request in L2, after being uploaded to the L2 pipeline, finds that the cacheline does not exist in the current cache or that the access permissions of the cacheline in the current cache are insufficient. In this case, an ORQ needs to be requested, and the data is reloaded to the next level of memory through the ORQ to obtain the corresponding permissions.
[0043] The WRQ is used when L2 needs to write a certain cacheline to the next level of memory. In this case, a request is made to provide a WRQ, and the data is written to the next level of memory through the WRQ.
[0044] The EFQ is used to first fill the data back into the EFQ when the L2 is filled by reload data, and then write the data to L2$ through the L2 pipeline on the EFQ while returning the data to the request module.
[0045] The CPQ is used to probe the corresponding core. The probe request is first stored in the CPQ, and then the probe request is sent to the corresponding core through the CPQ.
[0046] The beneficial effects of this invention are as follows:
[0047] In this invention, the core read queue (CRQ) and core write queue (CWR) can deallocate the corresponding entry items as long as they are arbitrated and on the pipeline. If the CRQ / CWQ can be completed normally, the LSU is responded normally. If it cannot be completed normally, the full permissions are handed over to the OQ (outstanding queue). In this way, the CRQ / CWQ entry items are deallocated as quickly as possible, thereby effectively improving the overall performance of the CPU. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a basic block diagram of embodiment L2 of the present invention;
[0050] Figure 2 This is a basic flowchart of a load miss request according to an embodiment of the present invention;
[0051] Figure 3 This is a basic flowchart of the lsu eviction request in an embodiment of the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0053] Example 1
[0054] Reference Figure 1 As shown in the figure, this embodiment discloses a basic block diagram of L2, and its basic functions are described as follows:
[0055] This embodiment receives requests from the core and external extend, including
[0056] Receive read requests from the core and place them in the CRQ (core read queue).
[0057] Receive write requests from the core and place them in the CWQ (core write queue).
[0058] Receive probe requests from external sources and place them in the EPQ (extend probe queue).
[0059] In this embodiment, the arbitration module receives requests from CRQ, CWQ, EPQ, ORQ, EFQ, and CPQ, and selects one of these requests to enter the pipeline.
[0060] In this embodiment, the pipeline determines the following based on the request type and the current L2 TAG and MESI status information:
[0061] Can it be written directly to L2?
[0062] Is it possible to directly return data to the requester?
[0063] Do I need to reload data or permissions to downstream memory?
[0064] Does it need to generate an evict?
[0065] Does it need to write data to downstream memory?
[0066] Is probe core needed?
[0067] In this embodiment, if it is determined that data or permissions need to be reloaded to the downstream memory, an ORQ (outstanding request queue) is allocated.
[0068] In this embodiment, if it is determined that data needs to be written to the downstream memory, a WRQ (writerequet queue) is allocated.
[0069] In this embodiment, if it is determined that a probe core is needed, a CPQ (core probe queue) is allocated. L2 sends probe requests to the core, all of which are completed through the CPQ (core probe queue).
[0070] In this embodiment, L2 sends a request to the downstream memory:
[0071] Read requests are sent via an ORQ (outstanding request queue) to retrieve data from downstream memory and obtain the corresponding permissions.
[0072] Write requests are processed via WRQ (write request queue) to write data from L2 to the next level of memory.
[0073] In this embodiment, the downstream memory returns reloaded data to fill the EFQ (Extend fill queue). Then, the L2de pipeline on the EFQ (Extend fill queue) writes the reloaded data into L2$, and simultaneously returns the data to the requested core.
[0074] Example 2
[0075] This embodiment provides a protocol for maintaining data consistency in a memory system, used to indicate the permissions granted to the current core of the cacheline, as detailed below:
[0076] M:modify indicates that the core has modified the cacheline. This cacheline only exists in this cache. If other caches need to access this cacheline, they need to use the probe function to obtain the latest dirty data and acquire the corresponding permissions.
[0077] E:Exclusive indicates that this cacheline exists only in this cache. If other caches need to access this cacheline, they need to obtain the corresponding data and permissions through probe.
[0078] S:Shared indicates that the cacheline exists not only in this cache but also in other caches. If other caches need to access this cacheline and obtain E / M status, they need to obtain the corresponding data and permissions through probe.
[0079] I:Invalid indicates that the cacheline is not in this cache.
[0080] Example 3
[0081] At the implementation level, this embodiment provides a basic flow for load miss and lsu eviction requests, which is the basic read-write process.
[0082] In this embodiment, as Figure 2 As shown, the basic process of a load miss request is as follows:
[0083] 1. A load miss request is sent from the core, and a CRQ entry is allocated.
[0084] 2. A CRQ load miss request is uploaded to the pipeline and wins arbitration; then it is uploaded to the pipeline.
[0085] 3. If tag_ram is hit, directly deallocate the corresponding entry in CRQ.
[0086] 4. If `miss`, then allocate the ORQ and deallocate the corresponding entry in the CRQ.
[0087] 5. ORQ sends a reload request to the next-level memory, and waits for the data to be refilled.
[0088] 6. Sub-level memory backfill data is written into EFQ.
[0089] 7. EFQ participated in and obtained pipeline arbitration.
[0090] 8. Update L2 tag_ram and data_ram, return the data to the core, and simultaneously deallocate the corresponding ORQ (outstanding request queue) and EFQ (extend probe queue) entry items.
[0091] In this embodiment, as Figure 3 As shown, the basic process of an lsu eviction request is as follows:
[0092] 1. The lsu eviction request is issued from the core and allocates a CWQ entry item.
[0093] 2. CWQ's lsu eviction request was submitted to the pipeline and won arbitration, thus being submitted to the pipeline.
[0094] 3. If tag_ram is hit, directly deallocate the corresponding entry in CWQ, and simultaneously provide a response to lsu.
[0095] 4. If `miss`, `tag_ram` is allocated in the WRQ, and the data is written into the WRQ. If the same `pa` already exists in the WRQ, the eviction data is merged into the WRQ.
[0096] 5. WRQ writes the data to the next level of memory.
[0097] 6. The lower-level memory will respond to WRQ and deallocate the corresponding entry item of WRQ.
[0098] In this embodiment, as can be seen from the above read and write process, as long as CRQ or CWQ wins arbitration and gets on the pipeline, it can be immediately deallocated, thus freeing up the entry item to receive new requests from LSU.
[0099] Example 4
[0100] This embodiment provides a fast deallocate implementation system for CRQ and CWQ in L2, including probe, eviction, TAG RAM, DATA RAM, CRQ, CWQ, EPQ, ORQ, WRQ, EFQ, and CPQ.
[0101] In this embodiment, the probe is used for spying and listening, probing the dirty data in the core or modifying the MESI status information in the core in order to obtain E privileges;
[0102] The eviction is used to keep the data stored in the cache relatively new, and is generated when data needs to be replaced out of the cache;
[0103] The TAG RAM is used to record the cacheline's addr and the cacheline's MESI status information in L2 and all L2 cores;
[0104] The DATA RAM is used to record cacheline data information;
[0105] The CRQ is a queue used to receive read requests from the core.
[0106] The CWQ is a queue used to receive write requests from the core;
[0107] The EPQ is a queue used to receive probe requests from external sources;
[0108] The ORQ is used when a request in L2, after being uploaded to the L2 pipeline, finds that the cacheline does not exist in the current cache or that the access permissions of the cacheline in the current cache are insufficient. In this case, an ORQ needs to be requested, and the data is reloaded to the next level of memory through the ORQ to obtain the corresponding permissions.
[0109] The WRQ is used when L2 needs to write a certain cacheline to the next level of memory. In this case, a request is made to provide a WRQ, and the data is written to the next level of memory through the WRQ.
[0110] The EFQ is used to first fill the data back into the EFQ when the L2 is filled by reload data, and then write the data to L2$ through the L2 pipeline on the EFQ while returning the data to the request module.
[0111] The CPQ is used to probe the corresponding core. The probe request is first stored in the CPQ, and then the probe request is sent to the corresponding core through the CPQ.
[0112] In summary, as long as the core read queue (CRQ) and core write queue (CWR) of this invention have obtained arbitration and are on the pipeline, the corresponding entry items can be dealt with. If the CRQ / CWQ can be completed normally, the LSU is responded normally. If it cannot be completed normally, the full permissions are handed over to the OQ (outstanding queue). In this way, the CRQ / CWQ entry items are dealt with as quickly as possible, thereby effectively improving the overall performance of the CPU.
[0113] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for implementing CRQ and CWQ fast deallocation in L2, characterized in that, The method comprises the following steps: S1, receiving requests from cores and external extensions, receiving requests from CRQ, CWQ, EPQ, ORQ, EFQ and CPQ by an arbitration module, and selecting one of the requests to enter a pipeline; S2, judging the data or authority required by the downstream according to the type of the request entering the pipeline and the TAG information and MESI state information in the current L2, and performing corresponding allocation; In the pipeline, it is determined according to the type of the request and the TAG information and MESI state information in the current L2 whether it can be directly written into L2, whether it can directly return data to the requester, whether it needs to reload data or authority to the downstream memory, whether it needs to generate evict, whether it needs to write data to the downstream memory, whether it needs to probe the core, and the like. If it is judged that data or authority needs to be reloaded to the downstream memory, an ORQ is allocated; if it is judged that data needs to be written to the downstream memory, a WRQ is allocated; if it is judged that the core needs to be probed, a CPQ is allocated, and the L2 sends a probe request to the core, which is completed through the CPQ; S3, sending a read request or a write request to the downstream memory by the L2, and returning the reload data to the EFQ; S4, entering the pipeline of the L2 by the EFQ, and writing the data returned by the reload into the L2, and returning the data to the core; The request from the core is a load miss request or an lsu eviction request. In the method, the request from the core is a read request, which is placed in the CRQ; the write request from the core is placed in the CWQ; and the probe request from the external extension is placed in the EPQ. In the method, the read request sent to the downstream memory by the L2 is sent through the ORQ, and the data read from the downstream memory is obtained.
2. The method of claim 1, wherein the CRQ and CWQ fast deallocation is implemented in L2. In the method, the write request sent to the downstream memory by the L2 is sent through the WRQ, and the data is written from the L2 to the next memory.
3. The method of claim 1, wherein the method is implemented in an L2 queue management manner. In the method of performing the load miss request, the following steps are included:
4. The method of claim 3, wherein the method further comprises: The load miss request is sent from the core and an CRQ entry item is allocated; 5. The method of claim 1, wherein the method is implemented in L2. The load miss request of the CRQ enters the pipeline and wins the arbitration to enter the pipeline; If the tag_ram is hit, the corresponding entry item in the CRQ is directly deallocated; If the tag_ram is not hit, the ORQ is allocated and the corresponding entry item in the CRQ is deallocated. ORQ sends reload request to next level memory, waits for refill data; Lower level memory fills data into EFQ; EFQ participates in pipeline arbitration and wins; Update TAG RAM in L2, return data in DATA RAM to core, and deallocate ORQ and EFQ entries.
6. The method of claim 1, wherein the method is implemented in L2. In the method, when lsu eviction request is sent, the following steps are included: lsu eviction request is sent from core and allocates a CWQ entry; lsu eviction request of CWQ enters pipeline and wins arbitration, enters pipeline; If tag_ram is hit, corresponding entry in CWQ is deallocated, and response is given to lsu; If tag_ram is not hit, WRQ is allocated, data is written into WRQ, and if the same addr exists in WRQ, eviction data is merged into WRQ; WRQ writes data into next level memory; Next level memory responds to WRQ and deallocates WRQ entry.
7. A system for implementing the method for implementing the CRQ and CWQ fast deallocation in L2 according to any one of claims 1-6, wherein, probe, eviction, TAG RAM, DATA RAM, CRQ, CWQ, EPQ, ORQ, WRQ, EFQ and CPQ are included.
8. The system for L2 in L2 CRQ and CWQ fast deallocation implementation according to claim 7, wherein, probe is used for peeking and listening, dirty data in core is probed down or MESI state information in core is modified to get E permission; eviction is used for keeping data in cache relatively new, and is generated when data needs to be replaced in cache; TAG RAM is used for recording addr of cacheline and MESI state information of the cacheline in L2 and all L2 COREs; DATA RAM is used for recording data information of cacheline; CRQ is used for receiving read request from core; CWQ is used for receiving write request from core; EPQ is used for receiving probe request from outside; ORQ is used for a request in L2 entering pipeline of L2, finding that the cacheline does not exist in the cache or access permission of the cacheline in the cache is not enough, then an ORQ is applied, data is reloaded from next level memory through ORQ, and corresponding permission is obtained. The WRQ is used to apply for writing a cacheline to a next-level memory when L2 needs to write the cacheline to the next-level memory, and data is written to the next-level memory through the WRQ; The EFQ is used to backfill data into the EFQ when the data is backfilled into L2 by reload, and then the data is written into L2 through the pipeline of L2 on the EFQ and returned to the request module; The CPQ is used to send a probe request to a core, and the probe request is first stored in the CPQ, and then the probe request is sent to the corresponding core through the CPQ.
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